200907804 24326twf.doc/p 九、發明說明： 【發明所屬之技術領域】 本發明是有關於-種電腦，且特別是有關於一種更新 基本輸入輸出系統（Basic Input/Output System，BIOS)之 方法以及使用該方法之電腦與系統。 【先前技術】 。目岫之電腦系統關於BI0S更新之技術眾多。例如， 在單一 BIOS之系統下，須要有一硬體機制去保護bi〇s 内之開機區塊（bootbloek) ’以免使用者操作不慎而毁壞 此一開機區塊。在電腦系統出貨後，常會因為需求（例如 要更新Intel之mem0Iy initializati〇n c〇de)而必需更新此 BIOS之開機區塊，此時必需透過此一硬體機制去更新此 BIOS 機區塊。然而，有可能在更新此m〇s開機區塊之 過程中，因意外（例如突發性斷電）造成BI〇s内容毀壞， 其將導致整個電腦系統無法順利開機。此時，使用者必需 將電腦送回廠商維修，以便更換Bi〇s。 另一個BIOS更新技術為使用雙BI〇s(dualBI〇s)， 此方法可解決箣述習知技術之缺點。當其中一個Bios毁 壞時’電腦可以切換至另一個BI〇s以順利開機。由於電 腦已經具備兩套BIOS，因此不用對BI0S之開機區塊提供 硬體保護。因為，縱使某一 BIOS之開機區塊受損壞，電 腦依然可以由另一 BIOS開機，並將受損之BI0S回復。 然而，此一習知技術必須要有雙BI〇s之支援，其所需要 之成本較高。 200907804 v / v 1 y jl 」4326twf_ciQc/p 【發明内容】 本發明提供一種更新基本輸入輸出系統（BIOS)之方 法，藉由使用基板管理控制器去更新BIOS，可從遠端裝置 透過網路對此本地端電腦進行BIOS更新。 本發明提供一種電腦與系統，不需要安排額外的硬體 機制去保護BIOS之開機區塊，不論BIOS記憶體有無完 好之BIOS’皆可從遠端裝置透過網路對此本地端電腦進行 BIOS更新。 為解決上述問題，本發明提出一種更新BIOS之方法。 遠端裝置透過網路對本地端電腦之基板管理控制器下達更 新命令。依據更新命令，該基板管理控制器透過網路接收 由运端裝置提供之新BIOS。基板管理控制器將新bios寫 入BIOS記憶體。 … 本發明提出一種電腦’包括中央處理單元、基板管理 控制器、BIOS記憶體、第一開關單元以及第二開關單元。 基板管理控制益連接至一網路，其中當電腦被關機時，基 ^ 板管理控制器依然為致能。BIOS記憶體用以儲存BI0S。 第一開關單元耦接於中央處理單元與BIOS記憶體之間； 第二開關單元耦接於基板管理控制器與BIOS記憶體之 間。其中，當遠端裝置透過網路對基板管理控制器下達一 更新命令以及提供新BIOS時，基板管理控制器控制第— 開關單元而禁能BIOS記憶體與中央處理單元之間的連 接，以及控制第二開關單元而致能Bi〇s記憶體與基板管 理控制器之間的連接，以便將新BI0S寫入扭〇8記憶體。 200907804 υ/uiyjaw 24326twf.doc/p 本發明提出一種電腦系統，包括遠端裝置、網路以及 本地端電腦。本地端電腦透過網路耦接至遠端裝置，其中 該本地立而電細包括中央處理單元、基板管理控制器、 §己憶體、第一開關單元以及第二開關單元。 本發明因使用基板管理控制器去更新BI〇s，因此不論 BIOS記憶體有無s好之BI〇s，皆可從遠端|置透過網路 對此本地端電腦進行BI0S更新。縱使BI〇s之開機區塊 之内谷毀壞（或是空的），也透過網路與基板管理控制器 將其回復。因此’此電腦可以被^計成單—BI〇s系統， 且不需要安排額外的硬體機制去保護BIQS之開機區塊， 而能安全的去對BIOS之開機區塊做更新之工作。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉較佳實施例，並配合所附圖式，作詳細說明如下。 【實施方式】 ^圖1是依據本發明實施例說明一種更新基本輸入輸出 系統（Basic Input/Output System，以下簡稱 BIOS )方法之 AL耘圖。於步驟S110中，遠端裝置透過一網路對本地端 =腦之基板管理控制器下達一更新命令。依據此一更新命 令，基板管理控制器可以透過該網路接收由遠端裝置提供 之新BIOS (步驟§120)。因此，基板管理控制器可以將 新Bl〇S寫入本地端電腦之BIOS記憶體（步驟S130)。 圖2是依據本發明實施例說明一種可更新BIOS之電 腦及其電腦系統。請參關2，電腦系統包括遠端裝置 210、網路220以及本地端電腦23〇。本地端電腦23〇透過 200907804 24326twf.doc/p 網路220耦接至遠端裝置210。網路220可以是任何形式 之網路，例如 IP/UDP (Internet Protocol / User Diagram Protocol) 'RMCP(Remote Management Control Protocol) > HTTP 等。 本地端電腦230包括中央處理單元231、北橋晶片 232、南橋晶片234、主記憶體233、輸入輸出晶片（super input/ontput，SIO ) 235、第一開關單元236、第二開關單元 238、第三開關單元240、BIOS記憶體237、基板管理控制 器（Baseboard Management Controller，以下簡稱 BMC )200907804 24326twf.doc/p IX. Description of the Invention: [Technical Field] The present invention relates to a computer, and in particular to a method for updating a Basic Input/Output System (BIOS) and Computers and systems using this method. [Prior Art]. The computer systems that have been witnessed are numerous in terms of BI0S updates. For example, in a single BIOS system, a hardware mechanism is needed to protect the bootbloek in the bios to prevent the user from inadvertently destroying the boot block. After the computer system is shipped, it is often necessary to update the boot block of this BIOS because of the need (for example, to update Intel's mem0Iy initializati〇n c〇de). In this case, the BIOS block must be updated through this hardware mechanism. However, it is possible that during the process of updating this m〇s boot block, the content of BI〇s is destroyed due to an accident (such as a sudden power outage), which will cause the entire computer system to fail to boot. At this point, the user must return the computer to the manufacturer for repair to replace the Bi〇s. Another BIOS update technique is to use dual BI〇s (dualBI〇s), which solves the shortcomings of the prior art. When one of the Bios is destroyed, the computer can switch to another BI〇s to boot up smoothly. Since the computer already has two sets of BIOS, there is no need to provide hardware protection for the boot sector of BI0S. Because, even if the boot block of a certain BIOS is damaged, the computer can still be powered on by another BIOS and reply the damaged BI0S. However, this prior art technology must have the support of double BI〇s, which requires a higher cost. 200907804 v / v 1 y jl ” 4326 twf_ciQc/p SUMMARY OF THE INVENTION The present invention provides a method of updating a basic input/output system (BIOS) by using a baseboard management controller to update the BIOS, from a remote device through a network pair This local computer performs a BIOS update. The invention provides a computer and a system, and does not need to arrange an additional hardware mechanism to protect the BIOS boot block, regardless of whether the BIOS memory has a good BIOS or not, the BIOS can be updated from the remote device through the network. . In order to solve the above problems, the present invention proposes a method of updating a BIOS. The remote device issues an update command to the baseboard management controller of the local computer through the network. According to the update command, the baseboard management controller receives the new BIOS provided by the transport device through the network. The baseboard management controller writes the new bios to the BIOS memory. The present invention proposes a computer 'including a central processing unit, a substrate management controller, a BIOS memory, a first switching unit, and a second switching unit. The baseboard management control is connected to a network where the baseboard management controller is still enabled when the computer is turned off. The BIOS memory is used to store BI0S. The first switch unit is coupled between the central processing unit and the BIOS memory; the second switch unit is coupled between the baseboard management controller and the BIOS memory. Wherein, when the remote device issues an update command to the baseboard management controller through the network and provides a new BIOS, the baseboard management controller controls the first switch unit to disable the connection between the BIOS memory and the central processing unit, and controls The second switching unit enables the connection between the Bi〇s memory and the substrate management controller to write the new BIOS to the torsion 8 memory. 200907804 υ/uiyjaw 24326twf.doc/p The present invention proposes a computer system comprising a remote device, a network, and a local computer. The local computer is coupled to the remote device through the network, wherein the local device includes a central processing unit, a baseboard management controller, a suffix body, a first switch unit, and a second switch unit. The present invention uses the baseboard management controller to update the BI〇s, so whether the BIOS memory has a good BI〇s or not, the BI0S update can be performed on the local computer from the remote end. Even if the valley inside the boot block of BI〇s is destroyed (or empty), it will be replied through the network and the baseboard management controller. Therefore, this computer can be counted as a single-BI〇s system, and there is no need to arrange an additional hardware mechanism to protect the boot block of BIQS, and it can safely update the boot block of the BIOS. The above described features and advantages of the present invention will become more apparent from the following description. [Embodiment] FIG. 1 is an AL diagram illustrating a method of updating a Basic Input/Output System (hereinafter referred to as BIOS) according to an embodiment of the present invention. In step S110, the remote device sends an update command to the baseboard management controller of the local end=brain through a network. According to this update command, the baseboard management controller can receive the new BIOS provided by the remote device through the network (step § 120). Therefore, the base management controller can write the new BlS to the BIOS memory of the local computer (step S130). 2 is a diagram showing a computer capable of updating a BIOS and a computer system thereof according to an embodiment of the present invention. Please refer to 2, the computer system includes the remote device 210, the network 220, and the local computer 23〇. The local computer 23 is coupled to the remote device 210 via the 200907804 24326 tw.doc/p network 220. The network 220 can be any form of network, such as IP/UDP (Internet Protocol / User Diagram Protocol) 'RMCP (Remote Management Control Protocol) > HTTP. The local computer 230 includes a central processing unit 231, a north bridge chip 232, a south bridge wafer 234, a main memory 233, an input/output chip (SIO) 235, a first switching unit 236, a second switching unit 238, and a third. The switch unit 240, the BIOS memory 237, and the baseboard management controller (BMC)
241、BMC 快閃記憶體（BMC flash memory ) 23 9 以及 BMC 之非揮發性記憶體(NVRAM)242。輸入輸出晶片235透過 低接腳數(Low Pin Count，簡稱LPC)匯流排耦接至南橋晶 片234，以及透過延伸匯流排XBUS耦接至第一開關單元 236。輸入輸出晶片235可以提供序列方式之LPC匯流排 與並列方式之延伸匯流排XBUS二者之間的資料轉換介 面。 BIOS記憶體237可以快閃記憶體實現之。BIOS記憶 體237用以儲存基本輸入輸出系統（BI〇s)韌體碼。第一 開關單元236搞接於中央處理單元231與BIOS記憶體237 之間。第一開關單元230受控於控制信號γ (由基板管理 控制态241所提供）。透過控制信號γ之控制，BI〇s記 憶體237可以在正常操作模式下，經由開關單元236、延 伸匯流排XBUS、輸入輸出晶片235、[pc匯流排、南橋 a曰片234、北橋晶片232而輕接至中央處理單元231。於本 200907804 24326twf.doc/p 實施例中，BIOS記憶體237是受控於控制信號χι (由基 板管理控制器241所提供）而決定其致能狀態。 第二開關單元23 8與第三開關單元2 4 〇耦接於基板管 .理控制器241與BIOS記憶體237之間。在正常操作模式 、下，第二開關單元238因受控於控制信號w (由基板管理 控制态241所提供）而保持戴止狀態，以避免快 記憶體239與BI0S記憶體237二者之存取操作相互干擾二 Π 在正常操作模式下，第三開關單元240受控於控制信號2 (由基板管理控制器241所提供）而保持導通狀態，使基 板管理控制器241得以存取BMC快閃記憶體239；於本^ 施例中’ BMC快閃記憶體239是受控於控制錢幻（二 基板管理控制盗241所提供）而決定其致能狀態。 BMC之非揮發性§己憶體242 _接至基板管理控制器 241°基板官理控制& 241透過其内部之網路介面控制器 (Network Interface C0ntr〇ller，以下簡稱赋）243 連接至 祕220。基板管理控制器24U吏用本地端電腦23〇之待 機電獅VSB，目此當本地端電腦23()被誠時，基板管 理控制器241依然為致能。其中，當遠端裝置21()透過網 路22〇對基板管理控制器加下達更新命令以及提供新 BIOS時’基板管理控制器、24丨控制第—開關單元236而禁 能BIOS記憶體237與中央處理單元231之間的連接，以 及控制第二開關單元238與第三開關單元24〇而致能班⑽ 記憶體237與基板管理控制器241之間的連接，以便將新 BIOS寫入BIOS記憶體237。 200907804 U /U iy^. 1 vv 24326twf.doc/p 圖3是依照本發明說明圖1之詳細實施範例。其中， 步驟S120包含子步驟S308、S316、S318，而步驟S130 包含子步驟S312、S314、S320。請同時參照圖2與圖3。 關於本地端電腦230之各種重要資料，可以利用每次開機 自我測試（Power On Self Test, POST)期間，將各種重要 資料備份在BMC之非揮發性記憶體242 (步驟S302)。 上述各種重要資料可以是系統管理BIOS ( system management BIOS，SMBIOS)資料，其可能包括 BIOS 資 訊（即 SMBIOS type 0)、系統資訊（即 SMBIOS type 1 )、 基板資訊（即SMBIOS type 2)及系統機箱資訊（system enclosure or chassis，即 SMBIOS type 3)等資料。本地端 電月白230可利用智慧平台管理介面（intenigent piatform Management Interface，以下簡稱IPMI)命令將上述各種重 要資料寫入BMC之非揮發性記憶體242。 步驟S304決定是否進行BI〇s更新。在此可以依據實 際操作需求而決定是否更新B〗〇 S。例如，使用者欲將新版 BIOS寫入BIOS記憶體237 ; BIOS記憶體237是空的； BIOS s己憶體237中’開機區塊（b〇〇t心成）之内容已被 室又壞’或者BIOS 6己憶體237中’ BIOS已被毀壞。若使用 者不需更新BIOS，或是BI〇S記憶體237所儲存之BI〇s 疋良好的，則本地端電腦230不需進行BI〇s更新（步驟 S306)。反之，若使用者欲更新則s，或是別⑽記憶體 237之内容已被毁壞，則進行步驟S3〇8。 10 200907804 „ --------- 24326twf*.d〇c/p 於步驟S308，遠端裳置2i〇傷妥新BI〇s (例如影像 檔BIOS.bin)以便猶後透過網路22〇傳送給本地端電腦 230。基於網路220之特性，以及基於基板管理控制器加 可以暫存貝料之記憶容量限制，遠端裝置21〇可能必需要 將f BIOS切分為多個BI〇s資料，然後一個接著一個地 將這些BIOS資料傳送給基板管理控制器如。當然，若傳 送環纟兄許可，遠端裝置210亦可以將新BI〇s 一次傳送給 基板管理控制器241而不需進行切割。 接著進行步驟S310，遠端裝置21〇透過網路22〇對本 地端電腦230之基板管理控制器241下達關機命令。此關 機命令可以是IPMI message (request)。基板管理控制器 241依據此一關機命令，使本地端電腦23〇關機。如前所 述’當本地端電腦230被關機時，基板管理控制器241依 然為致能。241, BMC flash memory 23 9 and BMC non-volatile memory (NVRAM) 242. The input and output chips 235 are coupled to the south bridge wafer 234 through a low pin count (LPC) bus bar, and to the first switch unit 236 through the extension bus bar XBUS. The input and output wafer 235 can provide a data conversion interface between the sequential LPC bus and the parallel extension bus XBUS. The BIOS memory 237 can be implemented by flash memory. The BIOS memory 237 is used to store the basic input/output system (BI〇s) firmware code. The first switch unit 236 is connected between the central processing unit 231 and the BIOS memory 237. The first switching unit 230 is controlled by a control signal γ (provided by the substrate management control state 241). Through the control of the control signal γ, the BI〇s memory 237 can be in the normal operation mode via the switch unit 236, the extension bus XBUS, the input/output chip 235, the [pc bus, the south bridge a 234, the north bridge 232 Lightly connected to the central processing unit 231. In the embodiment of the present invention, the BIOS memory 237 is controlled by a control signal ( (provided by the board management controller 241) to determine its enable state. The second switch unit 238 and the third switch unit 241 are coupled between the substrate controller 241 and the BIOS memory 237. In the normal operation mode, the second switching unit 238 is kept in a wearing state by being controlled by the control signal w (provided by the substrate management control state 241) to avoid the existence of both the fast memory 239 and the BIOS memory 237. The operation is mutually disturbed. In the normal operation mode, the third switching unit 240 is controlled to be in the on state by the control signal 2 (provided by the substrate management controller 241), so that the substrate management controller 241 can access the BMC flash. The memory 239; in the present embodiment, the 'BMC flash memory 239 is controlled by the control of the money magic (provided by the two substrate management control thief 241) to determine its enabling state. BMC's non-volatile § Remembrance 242 _ connected to the baseboard management controller 241 ° substrate official control & 241 through its internal network interface controller (Network Interface C0ntr〇ller, hereinafter referred to as Fu) 243 connected to the secret 220. The baseboard management controller 24U uses the local computer 23 to wait for the electromechanical lion VSB. Therefore, when the local computer 23 () is sincere, the substrate management controller 241 is still enabled. Wherein, when the remote device 21 () adds an update command to the baseboard management controller via the network 22, and provides a new BIOS, the 'baseboard management controller 24' controls the first switch unit 236 to disable the BIOS memory 237 and The connection between the central processing unit 231, and the control of the second switching unit 238 and the third switching unit 24 to enable the connection between the bank (10) memory 237 and the substrate management controller 241 to write the new BIOS to the BIOS memory. Body 237. 200907804 U /U iy^. 1 vv 24326twf.doc/p FIG. 3 is a diagram illustrating a detailed embodiment of FIG. 1 in accordance with the present invention. Step S120 includes sub-steps S308, S316, and S318, and step S130 includes sub-steps S312, S314, and S320. Please refer to FIG. 2 and FIG. 3 at the same time. Regarding various important materials of the local computer 230, various important data can be backed up in the non-volatile memory 242 of the BMC during each power on self test (POST) (step S302). The above various important materials may be system management BIOS (SMBIOS) data, which may include BIOS information (ie SMBIOS type 0), system information (ie SMBIOS type 1), substrate information (ie SMBIOS type 2) and system chassis. Information (system enclosure or chassis, SMBIOS type 3). The local end of the electricity white 230 can use the intenigent piatform management interface (IPMI) command to write the above various important data into the non-volatile memory 242 of the BMC. Step S304 decides whether or not to perform BI〇s update. Here, it is possible to decide whether to update B 〇 S according to actual operational needs. For example, the user wants to write a new version of the BIOS to the BIOS memory 237; the BIOS memory 237 is empty; the contents of the 'boot block (b〇〇t heart) in the BIOS 237 have been broken by the room' Or the BIOS 6 has recovered from the 237' BIOS has been destroyed. If the user does not need to update the BIOS, or the BI〇s stored in the BI〇S memory 237 is good, the local computer 230 does not need to perform BI〇s update (step S306). On the other hand, if the user wants to update s, or if the content of the other (10) memory 237 has been destroyed, step S3 〇 8 is performed. 10 200907804 „ --------- 24326twf*.d〇c/p In step S308, the remote device is 2i〇 and the new BI〇s (such as the image file BIOS.bin) is damaged so that it can pass through the network. 22〇 is transmitted to the local computer 230. Based on the characteristics of the network 220, and based on the substrate management controller plus the memory capacity limit that can temporarily store the bedding, the remote device 21 may need to split the f BIOS into multiple BIs. The data is transmitted to the baseboard management controller one by one. For example, if the transmission is approved, the remote device 210 can also transmit the new BI〇s to the substrate management controller 241 at a time. No further cutting is required. Next, in step S310, the remote device 21 transmits a shutdown command to the baseboard management controller 241 of the local computer 230 via the network 22. The shutdown command may be an IPMI message (request). According to the shutdown command, the local computer 23 is turned off according to the shutdown command. As described above, when the local computer 230 is turned off, the base management controller 241 is still enabled.
接著進行步驟S110，遠端裝置210透過網路220對基 板管理控制器241下達更新命令。此更新命令可以是〗pMI message (request)。基板管理控制器241便依據此一更新 命令而著手進行更新BIOS之準備工作。例如，進行步驟 S312與S314。於步驟S312，基板管理控制器241可以藉 由控制信號Y去控制開關單元236，以禁能BIOS記憶體 237與中央處理單元231之間的連接；以及藉由控制信號 W、Z去控制開關單元238與240，以致能BIOS記憶體 237與基板管理控制器241之間的連接。另外，基板管理 控制器241更藉由控制信號X2去禁能BMC快閃記憶體 11 200907804 ------- 24326twf. doc/p 239 ’以及藉由控㈣號X1去致能B腹記憶體撕。於 步驟S314 ’基板官理控制器241抹除Bl〇s記憶體之 内谷至此’更新BIOS之準備工作可以說已告一段落。 於步驟S316中，遠端裝置21〇透過網路22〇，將步驟 S308肋分之多筆BI0S資料中的其中一筆傳輸至基板管 理，制，241。在此’遠端裝置21〇可以利用 夾帶-筆BIOS資料給基板管理控制器241。當基板管理控 ^器241完整地接收到該些BI〇s資料其中之一時，基板 管理控制器241立即地進行步驟S318，以便將所接收到之 BIOS資料進行揪錯碼檢查（例如進行BI〇s 。 在確認無誤後，基板管理控制器241立即地將所接收到之 BIOS資料寫入BIOS記憶體237 (步驟S320)。 —在步驟S322中，遠端裝置210透過網路220發出IPMI 命令去問本地端電腦230之基板管理控制器241 ’是否此 次之BIOS資料已寫入BIOS記憶體237。若此次之BIOS 資料尚未寫入BIOS記憶體237,則遠端裝置210會暫停傳 送下一筆BIOS資料。若此次之BI〇s資料已成功寫入m〇s 記憶體237 ’則繼續進行步驟S324。 在步驟S324中’基板管理控制器241會判斷步驟S308 所切分之多筆BIOS資料是否已全數傳送至本地端電腦 230。若新BIOS已經完整地傳送給本地端電腦23〇，則遠 端裝置210會傳送IPMImessage至基板管理控制器241以 便告知多筆BIOS資料已全數傳送完畢。因此，若遠端裝 置尚未傳送表示BIOS傳送完畢之IPMI message，則 12 200907804 i w 24326twf.doc/p 繼續進行步驟S316，即遠端裝置210將下一筆BIOS資料 傳送給基板管理控制器241。若遠端裝置210已將表示 BIOS傳送完畢之IPMI message傳送給基板管理控制器 241，則進行步驟S326。 在步驟S326中，基板管理控制器241將步驟S302所 備份之重要資料寫回BIOS記憶體237。至此，更新BIOS 之工作可以說已告一段落。於本實施例中，基板管理控制 器241可以在此時對Bi〇S記憶體237進行檢驗，例如對 BIOS記憶體237之内容與遠端裝置21〇所提供之新m〇s 進行比對，以檢驗更新BIOS之操作是否成功。 在完成更新BIOS之操作後，繼續進行步驟S328。在 步驟S328中，基板管理控制器241可以藉由控制信號γ 去控制開關單元236’以致能BIOS記憶體237與中央處理 單兀231之間的連接；以及藉由控制信號w、z去控制開 關單兀238與240,以禁能BIOS記憶體237與基板管理控 制益241之間的連接，且致能BMC快閃記憶體239與基 板管理控制β 241之間的連接。另外，基板管理控制器 更藉由控制信號Χ2去致能BMC快閃記憶體239 ;以及藉 由控制信號XI去致能BIOS記憶體237。 在步驟S330中，遠端裝置21〇可以透過網路22〇對 基板管理控制器241下達詢問命令。此詢問命令可以是 IPMI message (request)。依據該詢問命令，基板管理杵 制器24i回報是否完整地將茅斤腦s冑入本地端電腦 之BIOS记憶體237。若基板管理控制器241回報之結果表 13 200907804 .. 24326twf.doc/p 示未成功更新BIOS，則再一次進行步驟3〇4。若基板管理 控制器241已完整地將新BIOS寫入m〇s記憶體237，則 遠端裝置210透過網路220對基板管理控制器241下達開 機命令（步驟S332)。此開機命令可以是IPMI message (request)。基板管理控制器241依據該開機命令，使本 地端電腦230重新開機。 綜上所述’上述實施例因使用基板管理控制器去更新 》 BIOS，因此不論Bi〇s記憶體有無完好之BI〇s ’皆可從 遠端裝置透過網路對此本地端電腦進行BIOS更新。縱使 BIOS之開機區塊之内容毀壞（或是空的）而導致本地端電 腦無法開機，也能透過遠端裝置、網路與基板管理控制器 將其回復。因此，此電腦可以被設計成單一 m〇S系統， 且不需要安排額外的硬體機制去保護BIOS之開機區塊， 而能安全的去對BIOS之開機區塊做更新之工作。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明’任何所屬技術領域中具有通常知識者，在不 脫離本發明之精神和範圍内，當可作些許之更動與潤飾， 因此本發明之保護範圍當視後附之申請專利範圍所界定者 為準。 【圖式簡單說明】 圖1是依據本發明實施例說明一種更新BIOS方法之 流程圖。 圖2是依據本發明實施例說明一種可更新BIOS之電 腦及其電腦系統。 ' 14 24326twf.doc/p 200907804 圖3是依照本發明說明圖1之詳細實施範例。 【主要元件符號說明】 S110〜S130 :本發明實施例中一種更新BIOS方法之 各步驟 210 :遠端裝置 220 :網路 230 :本地端電腦 231 :中央處理單元 232:北橋晶片 234 :南橋晶片 233 :主記憶體 235 :輸入輸出晶片 236 :第一開關單元 237: BIOS記憶體 238 :第二開關單元 239 : BMC快閃記憶體 L 240 :第三開關單元 241 :基板管理控制器（BMC) 242 : BMC之非揮發性記憶體 243 :網路介面控制器（NIC) LPC :低接腳數匯流排 XBUS :延伸匯流排 S302〜S332 :本發明實施例中另一種更新BIOS方法 之各步驟 15Next, in step S110, the remote device 210 issues an update command to the baseboard management controller 241 via the network 220. This update command can be a pMI message (request). The baseboard management controller 241 proceeds to prepare for updating the BIOS in accordance with this update command. For example, steps S312 and S314 are performed. In step S312, the substrate management controller 241 can control the switch unit 236 by the control signal Y to disable the connection between the BIOS memory 237 and the central processing unit 231; and control the switch unit by the control signals W, Z. 238 and 240, so that the connection between the BIOS memory 237 and the substrate management controller 241 can be enabled. In addition, the substrate management controller 241 further disables the BMC flash memory 11 200907804 ------- 24326 twf. doc/p 239 ' by the control signal X2 and enables the B belly memory by controlling the (4) X1 Body tearing. In step S314, the substrate official controller 241 erases the inner memory of the B1 memory, and the preparation for updating the BIOS can be said to have come to an end. In step S316, the remote device 21 transmits, via the network 22, one of the plurality of BIOS data of the step S308 to the substrate management system, 241. Here, the remote device 21 can utilize the entrainment-pen BIOS data to the baseboard management controller 241. When the substrate management controller 241 completely receives one of the BI〇s data, the substrate management controller 241 immediately proceeds to step S318 to perform error code check on the received BIOS data (for example, performing BI〇). After confirming the error, the baseboard management controller 241 immediately writes the received BIOS data to the BIOS memory 237 (step S320). - In step S322, the remote device 210 issues an IPMI command via the network 220. The baseboard management controller 241 of the local computer 230 asks whether the BIOS data of this time has been written into the BIOS memory 237. If the BIOS data of this time has not been written into the BIOS memory 237, the remote device 210 will suspend the transmission. BIOS data. If the current BI〇s data has been successfully written into the m〇s memory 237', proceed to step S324. In step S324, the baseboard management controller 241 determines the plurality of BIOS data segmented in step S308. Has it been transmitted to the local computer 230 in its entirety. If the new BIOS has been completely transmitted to the local computer 23, the remote device 210 will transmit the IPMImessage to the baseboard management controller 241 to inform the multiple BIOS. All the transmissions have been completed. Therefore, if the remote device has not transmitted the IPMI message indicating that the BIOS has been transmitted, then 12 200907804 iw 24326twf.doc/p proceeds to step S316, that is, the remote device 210 transmits the next BIOS data to the baseboard management control. If the remote device 210 has transmitted the IPMI message indicating that the BIOS has been transferred to the baseboard management controller 241, proceed to step S326. In step S326, the baseboard management controller 241 writes back the important data backed up in step S302. BIOS memory 237. At this point, the operation of updating the BIOS can be said to have come to an end. In this embodiment, the substrate management controller 241 can check the Bi〇S memory 237 at this time, for example, the contents of the BIOS memory 237. The new m〇s provided by the remote device 21〇 are compared to check whether the operation of updating the BIOS is successful. After the operation of updating the BIOS is completed, the process proceeds to step S328. In step S328, the substrate management controller 241 can Controlling the signal γ to control the switch unit 236' to enable the connection between the BIOS memory 237 and the central processing unit 231; and by controlling The signals w, z control the switch units 238 and 240 to disable the connection between the BIOS memory 237 and the substrate management control 241, and enable the connection between the BMC flash memory 239 and the substrate management control β 241. In addition, the substrate management controller further disables the BMC flash memory 239 by the control signal Χ2; and disables the BIOS memory 237 by the control signal XI. In step S330, the remote device 21A can issue an inquiry command to the baseboard management controller 241 via the network 22. This query command can be an IPMI message (request). In response to the inquiry command, the baseboard management controller 24i reports whether or not the mouse memory 237 is completely loaded into the BIOS memory 237 of the local computer. If the result reported by the baseboard management controller 241 is 13 200907804 .. 24326twf.doc/p, the BIOS is not successfully updated, and step 3〇4 is performed again. If the baseboard management controller 241 has completely written the new BIOS to the m〇s memory 237, the remote device 210 issues a power-on command to the baseboard management controller 241 via the network 220 (step S332). This boot command can be an IPMI message (request). The baseboard management controller 241 causes the local computer 230 to be powered on again according to the power-on command. In summary, the above embodiment uses the baseboard management controller to update the BIOS. Therefore, regardless of whether the Bi〇s memory has a good or not, the BIOS can update the local computer from the remote device through the network. . Even if the contents of the BIOS boot block are corrupted (or empty) and the local computer cannot be turned on, it can be replied to by the remote device, network and baseboard management controller. Therefore, this computer can be designed as a single m〇S system, and does not need to arrange an additional hardware mechanism to protect the BIOS boot block, but can safely update the BIOS boot block. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flow chart showing a method of updating a BIOS according to an embodiment of the present invention. 2 is a diagram showing a computer capable of updating a BIOS and a computer system thereof according to an embodiment of the present invention. ' 14 24326 twf.doc/p 200907804 FIG. 3 is a diagram illustrating a detailed embodiment of FIG. 1 in accordance with the present invention. [Main component symbol description] S110~S130: Step 210 of updating the BIOS method in the embodiment of the present invention: remote device 220: network 230: local computer 231: central processing unit 232: north bridge wafer 234: south bridge wafer 233 Main Memory 235: Input/Output Wafer 236: First Switch Unit 237: BIOS Memory 238: Second Switch Unit 239: BMC Flash Memory L 240: Third Switch Unit 241: Substrate Management Controller (BMC) 242 BMC non-volatile memory 243: network interface controller (NIC) LPC: low pin number busbar XBUS: extended bus bar S302~S332: another step 15 of updating the BIOS method in the embodiment of the present invention