CN116360570A

CN116360570A - Control method and control device for CPU power-on time sequence and electronic equipment

Info

Publication number: CN116360570A
Application number: CN202310264791.8A
Authority: CN
Inventors: 张�杰; 赵现普; 李岩
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2023-03-17
Filing date: 2023-03-17
Publication date: 2023-06-30

Abstract

The embodiment of the application provides a control method, a control device and electronic equipment for a CPU power-on time sequence, wherein the method comprises the following steps: under the condition that the CPLD of the main board sends a low-level first control signal to the CPU, the baseboard management controller acquires an updated firmware file, and writes the updated firmware file into the firmware of the voltage stabilizing controller so as to upgrade the firmware of the voltage stabilizing controller; determining whether the updated firmware file is successfully written into the firmware of the voltage stabilizing controller, and under the condition of successful writing, transmitting a high-level upgrade control signal to the main board CPLD, wherein the high-level upgrade control signal and the high-level second control signal enable the main board CPLD to transmit a high-level first control signal to the CPU after delaying for a preset time period. According to the method and the device, the problem that the power-on time sequence of the CPU does not meet the condition in the firmware upgrading process of the voltage stabilizing controller is solved, and the power-on time sequence of the CPU meets the power-on condition.

Description

Control method and control device for CPU power-on time sequence and electronic equipment

Technical Field

The embodiment of the application relates to the field of power-on control of servers, in particular to a control method and a control device of CPU power-on time sequence, a computer readable storage medium and electronic equipment.

Background

In the application field of a server, a VR Controller is used to supply power to a CPU in the server, and a provider of the voltage regulator Controller generally optimizes an FM (firmware, abbreviated as FM) of the voltage regulator Controller, and upgrades a firmware file to ensure stability of performance of the voltage regulator Controller. Since the server is generally applied to a machine room or a data center, it is very inconvenient to burn the firmware file offline, and thus it is necessary to implement an online upgrade function of the firmware file of the server. Currently, the BIOS (basic input output system, basic Input Output System, abbreviated as BIOS), BMC (baseboard management controller, baseboard Management Controller, abbreviated as BMC), CPLD (complex programmable logic device, complex Programmable Logic Device, abbreviated as CPLD) and VR (voltage regulator, voltage Regulator, abbreviated as VR) of a server generally develop firmware online upgrade functions. The online upgrade method of the server firmware generally connects the voltage stabilizing controller to the baseboard management controller through a Power Management Bus (PMBUS), so that the baseboard management controller can realize online upgrade of the voltage stabilizing controller through the power management bus.

Because the voltage-stabilizing controller is used for supplying power to the CPU, the firmware of the voltage-stabilizing controller is upgraded on line in a starting state, and the power supply of the CPU is possibly unstable, so that the server is down. In order to avoid downtime, the firmware of the voltage stabilizing controller of the CPU needs to be updated online in a shutdown state (S5 state). At present, the CPU Power supply of Intel is Main Power supply (Main Power) Power supply, and only the voltage stabilizing controller of the CPU has voltage output after the server is started, so that the firmware of the voltage stabilizing controller is upgraded in the S5 state, and the Power supply of the CPU is not affected after the server is started. In the state of S5, the CPU of the AMD Genoa platform needs two power supplies pvdd33_s5 and pvdd18_s5 to control power supply, and typically pvdd18_s5 is controlled by the voltage regulator controller to output, so that in the state of S5, the firmware file of the voltage regulator controller of pvdd18_s5 is updated, which affects the power-on timing sequence of the CPU. In order to avoid the damage to the CPU caused by unstable voltage in the online firmware upgrading process, the output of PVDD18_S5 needs to be closed before the firmware file is upgraded, and the output of PVDD18_S5 is controlled to be opened by the voltage stabilizing controller after the firmware file is upgraded. The power-on time sequence of the CPU in the S5 state needs to meet the following conditions: after the voltage stabilizing controller controls the power supply to be powered on completely and then delays for 10ms, the CPU can be powered on, namely, the power-on time sequence of the CPU needs to be updated after the level of the power supply changes (from high level to low level or from low level to high level). In the prior art, PVDD18_S5 normally supplies power to the CPU in the S5 state, the output of the PVDD18_S5 is required to be closed before the firmware of the voltage-stabilizing controller is upgraded, and the power-on time sequence of the CPU is not updated in the process after the firmware is upgraded, so that the CPU always maintains the power-on state, and the condition that the power-on time sequence of the CPU in the S5 state needs to be met is not met, therefore, the working state of the CPU is possibly abnormal.

Therefore, a method for solving the problem that the CPU timing does not meet the power-on condition due to the level change in the firmware on-line upgrade process of the voltage regulator controller is needed.

Disclosure of Invention

The embodiment of the application provides a control method, a control device, a computer readable storage medium and electronic equipment for a CPU power-on time sequence, which are used for at least solving the problem that the CPU power-on time sequence does not meet the condition in the firmware upgrading process of a voltage stabilizing controller in the related technology.

According to one embodiment of the present application, there is provided a control method for a power-on timing sequence of a CPU, including: under the condition that a low-level first control signal is sent to a CPU by a main board CPLD, a baseboard management controller acquires an updated firmware file, the updated firmware file is written into firmware of a voltage stabilizing controller to upgrade the firmware of the voltage stabilizing controller, wherein the low-level first control signal is sent by the main board CPLD under the condition that a low-level upgrade control signal sent by the baseboard management controller and a low-level second control signal sent by the voltage stabilizing controller are received, the upgrade control signal is used for indicating the upgrade state of the firmware of the voltage stabilizing controller, the upgrade state indicates whether the firmware of the voltage stabilizing controller is being upgraded, the second control signal is used for indicating the power supply state of the CPU corresponding to the power supply control signal of the voltage stabilizing controller, and the first control signal indicates the power-on time sequence of the CPU; determining whether the updated firmware file is successfully written into the firmware of the voltage stabilizing controller, and under the condition of successful writing, transmitting a high-level upgrade control signal to the main board CPLD, wherein the high-level upgrade control signal and the high-level second control signal enable the main board CPLD to transmit the high-level first control signal to the CPU after delaying for a preset time period, and the high-level second control signal is a signal transmitted to the main board CPLD by the voltage stabilizing controller under the condition of receiving the high-level power supply control signal.

In one exemplary embodiment, in a case where the motherboard CPLD outputs the first control signal of the low level, the baseboard management controller acquires the updated firmware file, including: determining whether a system in which the CPU is located is in a shutdown state; and when the system where the CPU is located is in the shutdown state and the baseboard management controller outputs the first control signal with low level, acquiring the updated firmware file.

In an exemplary embodiment, the second control signal of a low level is issued by the voltage regulator controller upon receiving the power supply control signal of a low level transmitted by the baseboard management controller.

In one exemplary embodiment, determining whether the updated firmware file is successfully written into the firmware of the voltage regulator controller includes: checking the updated firmware file written into the voltage stabilizing controller to obtain a checking completion instruction; under the condition that the verification completion instruction represents that verification is successful, determining that the updated firmware file is successfully written; and under the condition that the verification completion instruction represents verification failure, determining that the updated firmware file fails to be written.

In one exemplary embodiment, the high-level first control signal is sent by the motherboard CPLD when receiving the high-level upgrade control signal sent by the baseboard management controller and the high-level second control signal sent by the voltage regulator controller.

In an exemplary embodiment, the method further comprises: and under the condition that the updated firmware file fails to be written, writing the updated firmware file into the voltage stabilizing controller again.

In one exemplary embodiment, writing the updated firmware file to the firmware of the voltage regulator controller includes: and writing the updated firmware file into the firmware of the voltage stabilizing controller through a power management bus.

According to still another embodiment of the present application, there is provided a control method of a power-on timing sequence of a CPU, including: under the condition that a low-level upgrading control signal sent by a baseboard management controller and a low-level second control signal sent by a voltage stabilizing controller are received, a mainboard CPLD sends a low-level first control signal to a CPU, wherein the upgrading control signal is used for indicating the upgrading state of firmware of the voltage stabilizing controller, the upgrading state indicates whether the firmware of the voltage stabilizing controller is being upgraded or not, the second control signal is used for indicating the power supply state of the CPU corresponding to the power supply control signal of the voltage stabilizing controller, and the first control signal indicates the power-on time sequence of the CPU; and receiving the high-level upgrade control signal sent by the baseboard management controller and the high-level second control signal sent by the voltage stabilizing controller, and after delaying for a preset time period, sending the high-level first control signal to the CPU, wherein the high-level upgrade control signal and the high-level second control signal are generated and sent by triggering in the process that an updated firmware file is successfully written into the firmware of the voltage stabilizing controller, the updated firmware file is used for upgrading the firmware of the voltage stabilizing controller, and the firmware of the voltage stabilizing controller is triggered by the low-level upgrade control signal.

In one exemplary embodiment, in the case of receiving the low-level upgrade control signal sent by the baseboard management controller and the low-level second control signal sent by the voltage regulator controller, the main board CPLD sends the low-level first control signal to the CPU, including: determining whether a system in which the CPU is located is in a shutdown state; and when the system where the CPU is located is in the shutdown state and the main board CPLD receives the low-level upgrading control signal sent by the baseboard management controller and the low-level second control signal sent by the voltage stabilizing controller, the low-level first control signal is sent to the CPU.

In an exemplary embodiment, the upgrade control signal with a high level is sent by the baseboard management controller under the condition that a verification completion instruction represents that verification is successful, where the verification completion instruction is an instruction obtained after the baseboard management controller verifies a firmware file written into the voltage stabilizing controller.

In an exemplary embodiment, the second control signal of a high level is issued by the voltage regulator controller upon receiving the power supply control signal of a high level transmitted by the baseboard management controller.

In one exemplary embodiment, after transmitting the first control signal of high level to the CPU, further comprising: and controlling the voltage stabilizing controller to electrify the CPU according to the first control signal with high level.

In one exemplary embodiment, the upgrade control signal is sent by the baseboard management controller receiving the upgrade control signal over an I2C bus.

According to still another embodiment of the present application, there is provided a control method of a power-on timing sequence of a CPU, including: under the condition that a low-level power supply control signal sent by a baseboard management controller is received, a voltage stabilizing controller sends a low-level second control signal to a main board CPLD, the low-level second control signal and a low-level upgrading control signal enable the main board CPLD to send a low-level first control signal to a CPU, wherein the power supply control signal is used for indicating whether the voltage stabilizing controller supplies power to the CPU or not, the second control signal is used for indicating a power supply state of the CPU corresponding to the power supply control signal of the voltage stabilizing controller, the first control signal represents a power-on time sequence of the CPU, the low-level upgrading control signal is a signal sent by the baseboard management controller to the main board CPLD, and the upgrading control signal is used for indicating the upgrading state of firmware of the voltage stabilizing controller and indicates whether the firmware of the voltage stabilizing controller is being upgraded or not; and receiving an updated firmware file written by the baseboard management controller, and receiving the high-level power supply control signal sent by the baseboard management controller under the condition that the updated firmware file is successfully written by the voltage stabilizing controller, and sending the high-level second control signal to the main board CPLD, so that the main board CPLD sends the high-level first control signal to the CPU after delaying a preset time period under the condition that the high-level upgrade control signal sent by the baseboard management controller and the high-level second control signal sent by the voltage stabilizing controller are received.

In one exemplary embodiment, in the case of receiving the low-level power supply control signal sent by the baseboard management controller, the voltage regulator controller sends the low-level second control signal to the motherboard CPLD, including: determining whether a system in which the CPU is located is in a shutdown state; and when the system where the CPU is located is in the shutdown state and the voltage stabilizing controller receives the low-level power supply control signal sent by the baseboard management controller, sending the low-level second control signal to the mainboard CPLD.

In one exemplary embodiment, the low-level first control signal is sent by the motherboard CPLD upon receiving the low-level upgrade control signal sent by the baseboard management controller and the low-level second control signal sent by the voltage regulator controller.

In an exemplary embodiment, the first control signal of high level is used for controlling the voltage stabilizing controller to power up the CPU.

According to another embodiment of the present application, there is provided a control device for a power-on timing sequence of a CPU, including: the writing module is used for acquiring an updated firmware file by the baseboard management controller under the condition that the mainboard CPLD sends a low-level first control signal to the CPU, writing the updated firmware file into the firmware of the voltage stabilizing controller to upgrade the firmware of the voltage stabilizing controller, wherein the low-level first control signal is sent by the mainboard CPLD under the condition that the low-level upgrade control signal sent by the baseboard management controller and the low-level second control signal sent by the voltage stabilizing controller are received, the upgrade control signal is used for indicating the upgrade state of the firmware of the voltage stabilizing controller, the upgrade state indicates whether the firmware of the voltage stabilizing controller is being upgraded or not, the second control signal is used for indicating the power supply state of the CPU corresponding to the power supply control signal of the voltage stabilizing controller, and the first control signal indicates the power-on time sequence of the CPU; and the sending module is used for determining whether the updated firmware file is successfully written into the firmware of the voltage stabilizing controller, and sending a high-level upgrade control signal to the main board CPLD under the condition of successful writing, wherein the high-level upgrade control signal and the high-level second control signal enable the main board CPLD to send the high-level first control signal to the CPU after delaying for a preset time period, and the high-level second control signal is a signal sent to the main board CPLD by the voltage stabilizing controller under the condition of receiving the high-level power supply control signal.

According to another embodiment of the present application, there is provided a control device for a power-on timing sequence of a CPU, further including: the first sending module is used for sending a low-level first control signal to the CPU under the condition that the main board CPLD receives a low-level upgrading control signal sent by the baseboard management controller and a low-level second control signal sent by the voltage stabilizing controller, wherein the upgrading control signal is used for indicating the upgrading state of the firmware of the voltage stabilizing controller, the upgrading state indicates whether the firmware of the voltage stabilizing controller is being upgraded or not, the second control signal is used for indicating the power supply state of the CPU corresponding to the power supply control signal of the voltage stabilizing controller, and the first control signal indicates the power-on time sequence of the CPU; and the second sending module is used for receiving the high-level upgrade control signal sent by the baseboard management controller and the high-level second control signal sent by the voltage stabilizing controller, and sending the high-level first control signal to the CPU after delaying for a preset time period, wherein the high-level upgrade control signal and the high-level second control signal are generated and sent by triggering in the firmware of the voltage stabilizing controller when updated firmware files are successfully written in the firmware of the voltage stabilizing controller, the updated firmware files are used for upgrading the firmware of the voltage stabilizing controller, and the firmware of the voltage stabilizing controller is triggered by the low-level upgrade control signal.

According to another embodiment of the present application, there is provided a control device for a power-on timing sequence of a CPU, further including: the device comprises a first sending module, a second sending module and a CPU, wherein the first sending module is used for sending a low-level second control signal to a main board CPLD when receiving a low-level power supply control signal sent by a baseboard management controller, the low-level second control signal and a low-level upgrading control signal enable the main board CPLD to send a low-level first control signal to the CPU, the power supply control signal is used for indicating whether the voltage regulator controller supplies power to the CPU or not, the second control signal is used for indicating the power supply state of the CPU corresponding to the power supply control signal of the voltage regulator controller, the first control signal represents the power-on time sequence of the CPU, the low-level upgrading control signal is a signal sent by the baseboard management controller to the main board CPLD, and the upgrading control signal is used for indicating the upgrading state of firmware of the voltage regulator controller, and the upgrading state indicates whether the firmware of the voltage regulator controller is being upgraded or not; the second sending module is configured to receive the updated firmware file written by the baseboard management controller, receive the high-level power supply control signal sent by the baseboard management controller when the updated firmware file is successfully written by the voltage stabilizing controller, and send the high-level second control signal to the motherboard CPLD, so that the motherboard CPLD sends the high-level first control signal to the CPU after delaying a preset time period when receiving the high-level upgrade control signal sent by the baseboard management controller and the high-level second control signal sent by the voltage stabilizing controller.

According to a further embodiment of the present application, there is also provided a computer readable storage medium having stored therein a computer program, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.

According to a further embodiment of the present application, there is also provided an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.

According to the method and the device, the baseboard management controller sends the low-level upgrade control signal to the main board CPLD, so that the main board CPLD sends the low-level first control signal to the CPU after receiving the low-level upgrade control signal and the low-level second control signal so as to control the CPU to be powered down, and the low-level first control signal is sent to the CPLD after receiving the low-level power supply control signal sent by the baseboard management controller by the voltage stabilizing controller; and after the updated firmware file is successfully written, the high-level upgrade control signal is sent to the main board CPLD, so that the main board CPLD sends a high-level first control signal to the CPU after receiving the high-level upgrade control signal and the high-level second control signal so as to control the CPU to be electrified, and the high-level first control signal is sent to the CPLD by the voltage stabilizing controller after receiving the high-level power supply control signal sent by the substrate management controller. Compared with the method that the power-on time sequence of the CPU always keeps high level in the firmware upgrading process of the voltage stabilizing controller and cannot change according to the level change of the power supply control signal in the prior art, the method can control the level change of the first control signal by controlling the level change of the upgrading control signal and the level change of the second control signal, the level change of the second control signal can be controlled by controlling the level change of the power supply control signal, the change of the power-on time sequence of the CPU is further controlled by controlling the level change of the first control signal, and the power-on time sequence of the CPU also changes correspondingly after the level change of the power supply control signal, so that the condition that the power-on time sequence of the CPU becomes high level after the power supply control signal is high, namely the power supply for supplying power to the CPU is powered on is met, the problem that the power-on time sequence of the CPU does not meet the condition in the firmware upgrading process of the voltage stabilizing controller can be solved, and the power-on time sequence of the CPU meets the power-on condition.

Drawings

Fig. 1 is a hardware block diagram of a mobile terminal of a control method of a CPU power-on timing according to an embodiment of the present application;

FIG. 2 is a flow chart of a control method of CPU power-on time sequence in the prior art according to an embodiment of the present application;

FIG. 3 is a flowchart of a control method of CPU power-on sequence according to an embodiment of the present application;

FIG. 4 is a flowchart of a specific control method for CPU power-on sequence according to an embodiment of the present application;

FIG. 5 is a flowchart of another specific method for controlling CPU power-on timing according to an embodiment of the present application;

fig. 6 is a block diagram of a control device for a CPU power-on timing according to an embodiment of the present application.

Wherein the above figures include the following reference numerals:

102. a processor; 104. a memory; 106. a transmission device; 108. and an input/output device.

Detailed Description

Embodiments of the present application will be described in detail below with reference to the accompanying drawings in conjunction with the embodiments.

It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.

The method embodiments provided in the embodiments of the present application may be performed in a mobile terminal, a computer terminal or similar computing device. Taking the mobile terminal as an example, fig. 1 is a block diagram of a hardware structure of the mobile terminal of a control method of a CPU power-on sequence according to an embodiment of the present application. As shown in fig. 1, the mobile terminal may include one or more (only one is shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a microprocessor MCU, a processing device such as a programmable logic device FPG, a second control signal, etc.) and a memory 104 for storing data, wherein the mobile terminal may further include a transmission device 106 for communication functions and an input-output device 108. It will be appreciated by those skilled in the art that the structure shown in fig. 1 is merely illustrative and not limiting of the structure of the mobile terminal described above. For example, the mobile terminal may also include more or fewer components than shown in fig. 1, or have a different configuration than shown in fig. 1.

The memory 104 may be used to store a computer program, for example, a software program of application software and a module, such as a computer program corresponding to a control method of a CPU power-on sequence in the embodiment of the present application, and the processor 102 executes the computer program stored in the memory 104, thereby performing various functional applications and data processing, that is, implementing the above-mentioned method. Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory remotely located relative to the processor 102, which may be connected to the mobile terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The transmission device 106 is used to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the mobile terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, simply referred to as NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module, which is configured to communicate with the internet wirelessly.

Fig. 2 is a flowchart of a control method of a CPU power-on sequence in the prior art according to the embodiment of the present application, as shown in fig. 2, in the prior art, before a VR Controller (voltage regulator Controller) is upgraded online, a server is turned off, and then the server enters an S5 state (shutdown state). The BMC (baseboard management Controller) writes a register of the VR Controller through a PMBUS (power management bus), the output of the S5_VR (power supply control signal) is closed, then the BMC (baseboard management Controller) writes a new FW (firmware) file to the VR Controller through the PMBUS (power management bus), after the FW (firmware) file is successfully written and successfully written, the BMC (baseboard management Controller) writes the register of the VR Controller through the PMBUS (power management bus), the output of the S5_VR (power supply control signal) is opened, the S5_VR (power supply control signal) normally outputs power supply, the firmware of the VR Controller FW (firmware) is updated online, and the server normally works. Because the CPU needs power supply of S5, the CPU has a power-on timing requirement in the S5 state. For example, the power-up timing of the CPU of the Genoa platform requires that the rsmrst_n (first control signal) signal is continuously pulled down until all of the s5_vr (power control signal) of the CPU is powered up, and the rsmrst_n (first control signal) signal is pulled up after a delay of 10 ms. Before the existing VR Controller FW (firmware of the voltage stabilizing Controller) is updated online, the server is in the S5 state, and at this time, the s5_vr (power supply control signal) outputs a high level, so that power can be normally supplied to the CPU, and the rsmrst_n (first control signal) signal is in the high level state. When upgrading VR FW (firmware of a voltage stabilizing controller), firstly powering down S5_VR (power supply control signal), powering up PVDD18_S5 after upgrading, continuously pulling up RSMRST_N (first control signal) signals in the process, and after time delay of 10ms, pulling up CPU power-on time sequence requirements of RSMRST_N (first control signal) signals. Although the prior art solution has been verified in the laboratory, after the VR (voltage regulator controller) upgrade is completed, the server can be started up and work normally. However, the power-on time sequence of the CPU does not meet the requirement, so that the CPU cannot work normally. Therefore, the application provides a control method, a control device, a computer readable storage medium and electronic equipment for the power-on time sequence of a CPU, so as to at least solve the problem that the power-on time sequence of the CPU does not meet the condition in the firmware upgrading process of a voltage stabilizing controller in the related technology.

In this embodiment, a control method of a CPU power-on sequence running on the mobile terminal is provided, and fig. 3 is a flowchart of a control method of a CPU power-on sequence in the embodiment of the present application, as shown in fig. 3, where the flowchart includes the following steps:

in step S302, when the motherboard CPLD sends a low-level first control signal to the CPU, the baseboard management controller obtains an updated firmware file, writes the updated firmware file into the firmware of the voltage regulator controller, so as to upgrade the firmware of the voltage regulator controller, where the low-level first control signal is sent by the motherboard CPLD when receiving a low-level upgrade control signal sent by the baseboard management controller and a low-level second control signal sent by the voltage regulator controller, where the upgrade control signal is used to indicate an upgrade state of the firmware of the voltage regulator controller, where the upgrade state indicates whether the firmware of the voltage regulator controller is being upgraded, and the second control signal is used to indicate a power supply state of the CPU corresponding to a power supply control signal of the voltage regulator controller, and where the first control signal indicates a power supply timing of the CPU.

Specifically, the CPU in the server is powered by the voltage-stabilizing controller, and the power-on time sequence is controlled by the main board CPLD (complex programmable logic device, complex Programmable Logic Device, abbreviated as CPLD), that is, the main board CPLD controls the change of the high-low level in the power-on time sequence of the CPU, when the power-on time sequence is high level, the voltage-stabilizing controller can only power the CPU, and when the power-on time sequence is low level, the voltage-stabilizing controller stops powering the CPU. In order to meet the above power-up condition of the CPU, in step S202, when the motherboard CPLD informs the CPU of power-down by sending the low-level first control signal, after the CPU powers down, the baseboard management controller can obtain the updated firmware file and write the updated firmware file into the voltage-stabilizing controller to complete the firmware upgrade of the voltage-stabilizing controller, and the low-level first control signal is sent by the motherboard CPLD when the motherboard CPLD receives the low-level upgrade control signal sent by the baseboard management controller and the low-level second control signal sent by the voltage-stabilizing controller, the upgrade control signal is sent by the motherboard CPLD to indicate that the firmware to be updated is to be updated, i.e. the firmware to be upgraded is written into the voltage-stabilizing controller.

Step S304, determining whether the updated firmware file is successfully written into the firmware of the voltage regulator controller, and if the updated firmware file is successfully written, transmitting the upgrade control signal with a high level to the motherboard CPLD, where the upgrade control signal with a high level and the second control signal with a high level cause the motherboard CPLD to transmit the first control signal with a high level to the CPU after delaying for a preset period of time, where the second control signal with a high level is a signal transmitted to the motherboard CPLD by the voltage regulator controller when the voltage regulator controller receives the power supply control signal with a high level.

Specifically, after the updated firmware file is successfully written into the voltage stabilizing controller, the baseboard management controller sends a high-level upgrade control signal to the motherboard CPLD, which indicates that the firmware upgrade of the voltage stabilizing controller is completed, and simultaneously sends a high-level power supply control signal to the voltage stabilizing controller, which indicates that the voltage stabilizing controller can supply power to the CPU, where the high-level power supply control signal makes the voltage stabilizing controller send a high-level second control signal to the motherboard CPLD, so that the motherboard CPLD sends the high-level first control signal to the CPU after delaying for a preset period of time, where the starting time of the preset period of time is the time when the motherboard CPLD receives the high-level upgrade control signal and the high-level second control signal, and where the starting time of the preset period of time is the time when the motherboard CPLD receives the last received control signal, specifically, for example, may be set according to a specific application scenario: the preset time period may be set to 10ms. The numerical value of the above-mentioned preset time period is not particularly limited in the present application.

Through the steps, as the baseboard management controller sends the low-level upgrade control signal to the main board CPLD, the main board CPLD sends the low-level first control signal to the CPU after receiving the low-level upgrade control signal and the low-level second control signal so as to control the CPU to be powered down, and the low-level first control signal is sent to the CPLD after receiving the low-level power supply control signal sent by the baseboard management controller by the voltage stabilizing controller; and after the updated firmware file is successfully written, the high-level upgrade control signal is sent to the main board CPLD, so that the main board CPLD sends a high-level first control signal to the CPU after receiving the high-level upgrade control signal and the high-level second control signal so as to control the CPU to be electrified, and the high-level first control signal is sent to the CPLD by the voltage stabilizing controller after receiving the high-level power supply control signal sent by the substrate management controller. Compared with the method that the power-on time sequence of the CPU always keeps high level in the firmware upgrading process of the voltage stabilizing controller and cannot change according to the level change of the power supply control signal in the prior art, the method can control the level change of the first control signal by controlling the level change of the upgrading control signal and the level change of the second control signal, and the level change of the second control signal can be controlled by controlling the level change of the power supply control signal.

The main execution body of the above steps may be a server, but is not limited thereto.

In some embodiments of the present application, when the motherboard CPLD outputs the low-level first control signal, the baseboard management controller obtains the updated firmware file, including: determining whether a system in which the CPU is located is in a shutdown state; and when the system where the CPU is located is in the shutdown state and the baseboard management controller outputs the first control signal with a low level to the motherboard CPLD, acquiring the updated firmware file. By the method, the updated firmware file is acquired only when the CPU is determined to be in the shutdown state, so that the firmware of the voltage-stabilizing controller is updated, and the situation that the CPU cannot be supplied with power due to the fact that the firmware is updated by the voltage-stabilizing controller can be avoided.

Specifically, as described in the background art, the firmware upgrade of the voltage regulator controller needs to be performed when the server is in a shutdown state, that is, when the CPU of the server is in a shutdown state, and therefore, before the firmware upgrade is performed, it needs to be determined whether the CPU is in a shutdown state first.

In some embodiments of the present application, the low level of the second control signal is sent by the voltage regulator controller when the low level of the power supply control signal sent by the baseboard management controller is received. This allows the baseboard management controller to inform the voltage regulator controller to stop supplying power to the CPU by sending a low-level power supply control signal, and allows the voltage regulator controller to send a low-level second control signal to inform the motherboard CPLD after stopping supplying power to the CPU.

Specifically, the baseboard management controller sends a low-level upgrade control signal to the motherboard CPLD to indicate that a firmware upgrade is about to be performed, and sends a low-level power supply control signal to the voltage regulator controller to inform the voltage regulator controller that power is no longer supplied to the CPU, so that the voltage regulator controller sends a low-level second control signal to inform the motherboard CPLD that power supply to the CPU has stopped, and therefore the low-level second control signal is sent by the voltage regulator controller when the low-level power supply control signal sent by the baseboard management controller is received to indicate that the voltage regulator controller stops supplying power to the CPU.

In some embodiments of the present application, determining whether the updated firmware file is successfully written into the firmware of the voltage regulator controller includes: checking the updated firmware file written into the voltage stabilizing controller to obtain a checking completion instruction; under the condition that the verification completion instruction represents that verification is successful, determining that the updated firmware file is successfully written; and under the condition that the verification completion instruction represents verification failure, determining that the updated firmware file fails to be written. By the method, the voltage stabilizing controller can conveniently judge whether the firmware of the voltage stabilizing controller is upgraded or not so as to determine whether to continue to execute subsequent steps.

Specifically, after the updated firmware file is written into the firmware of the voltage stabilizing controller, the written firmware file is compared with the original updated firmware file, namely, the original updated firmware file is the firmware file before the firmware of the voltage stabilizing controller is not written, if the original updated firmware file is the same as the firmware file, the verification is output to be successful to indicate that the firmware is written, and if the original updated firmware file is different from the original firmware file, the verification is output to be failed to indicate that the firmware is written.

In some embodiments of the present application, the high-level first control signal is sent by the motherboard CPLD when receiving the high-level upgrade control signal sent by the baseboard management controller and the high-level second control signal sent by the voltage regulator controller. Therefore, after the firmware of the voltage stabilizing controller is successfully upgraded, the main board CPLD is informed of the success of the upgrade through the upgrade control signal of the high level and the second control signal of the high level, so that the main board CPLD sends the first control signal of the high level to the CPU to indicate that the power-on can be performed.

Specifically, after the firmware of the voltage regulator controller is successfully upgraded, the baseboard management controller sends a high-level upgrade control signal to the motherboard CPLD to indicate that the firmware upgrade is completed, and sends a high-level power supply control signal to the voltage regulator controller, so that the voltage regulator controller supplies power to the CPU and sends a high-level second control signal to the motherboard CPLD to indicate that the CPU can be powered on, and therefore, the high-level first control signal is sent by the motherboard CPLD when the high-level upgrade control signal sent by the baseboard management controller and the high-level second control signal sent by the voltage regulator controller are received, so that the CPU can be powered on.

In some embodiments of the present application, the method further includes: and when the updated firmware file fails to be written, writing the updated firmware file into the voltage stabilizing controller again. By the method, under the condition of writing failure, the firmware file is written again, so that the condition that the writing of the firmware file fails due to accidental factors can be avoided, and the updated firmware file can be ensured to be written into the firmware of the voltage stabilizing controller, so that the firmware of the voltage stabilizing controller is upgraded.

Specifically, in the case of a write failure, an instruction to verify failure is output, and at this time, the updated firmware file needs to be written into the voltage regulator controller again until the writing is successful.

In some embodiments of the present application, writing the updated firmware file into the firmware of the voltage stabilizing controller includes: and writing the updated firmware file into the firmware of the voltage stabilizing controller through a power management bus. By this method, the firmware file can be transferred from the baseboard management controller to the voltage stabilizing controller without adding an additional transfer device.

Specifically, in the server system, the baseboard management controller and the voltage stabilizing controller are physically connected through a power management bus, and on the basis, the firmware file is directly transmitted through the power management bus.

In this embodiment, a method for controlling a power-on time sequence of a CPU running on the mobile terminal is provided, where the process includes the following steps:

in step S402, when receiving the low-level upgrade control signal sent by the baseboard management controller and the low-level second control signal sent by the voltage regulator controller, the motherboard CPLD sends a low-level first control signal to the CPU, where the upgrade control signal is used to indicate an upgrade state of the firmware of the voltage regulator controller, the upgrade state indicates whether the firmware of the voltage regulator controller is being upgraded, the second control signal is used to indicate a power supply state of the CPU corresponding to a power supply control signal of the voltage regulator controller, and the first control signal indicates a power-on timing of the CPU.

Specifically, the CPU in the server is powered by the voltage-stabilizing controller, and the power-on time sequence is controlled by the main board CPLD (complex programmable logic device, complex Programmable Logic Device, abbreviated as CPLD), that is, the main board CPLD controls the change of the high-low level in the power-on time sequence of the CPU, when the power-on time sequence is high level, the voltage-stabilizing controller can only power the CPU, and when the power-on time sequence is low level, the voltage-stabilizing controller stops powering the CPU. The firmware in the voltage stabilizing controller generally needs to be upgraded, the CPU cannot be powered during the firmware upgrading process, so that the firmware is usually upgraded when the CPU is in a power-off state, that is, the server is in a power-off state, and after the firmware upgrading of the voltage stabilizing controller is completed, the CPU needs to be powered again, that is, the power-on state is changed from a power-down state to a power-on state, the condition that the power-on of the CPU is performed after all power supplies are powered on is completed, in order to meet the power-on condition of the CPU, in step S302, the main board CPLD informs the CPU of the power-down state by sending a low-level first control signal, and the low-level first control signal is sent by the main board CPLD when receiving a low-level upgrading control signal sent by the baseboard management controller and a low-level second control signal sent by the voltage stabilizing controller, the upgrade control signal is a low-level indicating that the updated firmware is to be written into the firmware of the voltage stabilizing controller, that the firmware of the voltage stabilizing controller is to be upgraded.

Step S404, receiving the upgrade control signal of high level and the second control signal of high level sent by the baseboard management controller, and after delaying for a preset period of time, sending the first control signal of high level to the CPU, wherein the upgrade control signal of high level and the second control signal of high level are generated and sent by triggering when the updated firmware file is successfully written into the firmware of the voltage stabilizing controller, the updated firmware file is used for upgrading the firmware of the voltage stabilizing controller, and the firmware of the voltage stabilizing controller is triggered by the upgrade control signal of low level.

Specifically, the main board CPLD sends the first control signal with a high level to the CPU after delaying for a preset period of time, where the first control signal with a high level is sent by the main board CPLD after receiving the upgrade control signal with a high level and the power supply control signal with a high level, and the power supply control signal with a high level makes the voltage regulator controller send the second control signal with a high level to the main board CPLD, where a start time of the preset period of time is a time when the main board CPLD receives the upgrade control signal with a high level and the second control signal with a high level, and where the upgrade control signal with a high level and the second control signal with a high level are not simultaneously received by the main board CPLD, the start time of the preset period of time is a time when the last received control signal is, specifically, may be set according to a specific application scenario, for example: the preset time period may be set to 10ms. The numerical value of the above-mentioned preset time period is not particularly limited in the present application.

Through the steps, as the main board CPLD receives the low-level upgrade control signal and the low-level second control signal, the low-level first control signal is sent to the CPU to control the CPU to power down, and the low-level first control signal is sent to the CPLD after the voltage stabilizing controller receives the low-level power supply control signal sent by the baseboard management controller; and after receiving the high-level upgrade control signal and the high-level second control signal, the main board CPLD transmits a high-level first control signal to the CPU to control the CPU to be electrified, wherein the high-level first control signal is transmitted to the CPLD after receiving the high-level power supply control signal transmitted by the baseboard management controller by the voltage stabilizing controller. Compared with the method that the power-on time sequence of the CPU always keeps high level in the firmware upgrading process of the voltage stabilizing controller and cannot change according to the level change of the power supply control signal in the prior art, the method can control the level change of the first control signal by controlling the level change of the upgrading control signal and the level change of the second control signal, and the level change of the second control signal can be controlled by controlling the level change of the power supply control signal.

In some embodiments of the present application, when receiving the low-level upgrade control signal sent by the baseboard management controller and the low-level second control signal sent by the voltage regulator controller, the main board CPLD sends the low-level first control signal to the CPU, including: determining whether a system in which the CPU is located is in a shutdown state; and when the system where the CPU is located is in the shutdown state and the main board CPLD receives the low-level upgrading control signal sent by the baseboard management controller and the low-level second control signal sent by the voltage stabilizing controller, the main board CPLD sends the low-level first control signal to the CPU. By the method, the CPU is determined to be in the shutdown state, so that the situation that the CPU cannot be supplied with power caused by upgrading firmware of the voltage-stabilizing controller can be avoided.

Specifically, as described in the background art, the firmware upgrade of the voltage regulator controller needs to be performed when the server is in a shutdown state, that is, when the CPU of the server is in a shutdown state, and therefore, before the first control signal is sent to indicate that the voltage regulator controller is about to perform the firmware upgrade, it needs to be determined whether the CPU is in the shutdown state first.

Specifically, the motherboard CPLD receives the low-level upgrade control signal sent by the baseboard management controller to indicate that a firmware upgrade is to be performed, and at the same time, the voltage regulator controller sends a low-level second control signal to inform the motherboard CPLD that power supply to the CPU is stopped, where the low-level second control signal is sent by the baseboard management controller to inform the voltage regulator controller that power supply to the CPU is no longer being performed, and therefore the low-level second control signal is sent by the voltage regulator controller when the low-level power supply control signal sent by the baseboard management controller is received to indicate that the voltage regulator controller stops power supply to the CPU.

In some embodiments of the present application, the upgrade control signal with a high level is sent by the baseboard management controller when the verification completion instruction represents that the verification is successful, where the verification completion instruction is an instruction obtained after the baseboard management controller verifies a firmware file written into the voltage stabilizing controller. By the method, the mainboard CPLD can judge that the firmware of the voltage stabilizing controller is successfully upgraded through the high-level upgrading control signal sent by the baseboard management controller.

Specifically, after receiving the high-level upgrade control signal sent by the baseboard management controller and the high-level second control signal sent by the voltage stabilizing controller, the main board CPLD sends the high-level first control signal to the CPLD, where the high-level upgrade control signal is sent by the baseboard management controller under the condition that the verification completion instruction characterizes that verification is successful, that is, the firmware of the voltage stabilizing controller is successfully upgraded.

In some embodiments of the present application, the high level of the second control signal is sent by the voltage regulator controller when the high level of the power supply control signal sent by the baseboard management controller is received. By the method, the main board CPLD can judge that the voltage stabilizing controller is in a state capable of supplying power to the CPU through the high-level second control signal.

Specifically, after receiving the high-level upgrade control signal sent by the baseboard management controller and the high-level second control signal sent by the voltage stabilizing controller, the main board CPLD sends the high-level first control signal to the CPLD, and the high-level second control signal is sent by the voltage stabilizing controller when the firmware upgrade of the voltage stabilizing controller, which is a high-level power supply control signal sent by the baseboard management controller, is successful.

In some embodiments of the present application, after sending the first control signal with a high level to the CPU, the method further includes: and controlling the voltage stabilizing controller to electrify the CPU according to the first control signal of the high level. By the method, the high-level first control signal enables the power-on time sequence of the CPU to meet the power-on condition, so that the CPU can be ensured to be powered on under the condition that the power-on time sequence is met, and the problem of abnormal working state of the CPU caused by power-on errors is avoided.

Specifically, after the low-level first control signal is sent by the motherboard CPLD and the firmware of the voltage stabilizing controller is successfully upgraded, the high-level first control signal is sent by the motherboard CPLD, and because the high-level second control signal of the voltage stabilizing controller already indicates that the voltage stabilizing controller can supply power to the CPU at this time, the high-level first control signal is sent to the CPU, and the power-on time sequence of the CPU meets the power-on condition, so that the voltage stabilizing controller is controlled to power on the CPU according to the high-level first control signal.

In some embodiments of the present application, the upgrade control signal is sent by the baseboard management controller through the I2C bus. By this method, the upgrade control signal can be transmitted from the baseboard management controller to the motherboard CPLD without adding additional transmission equipment.

Specifically, in the server system, the baseboard management controller and the motherboard CPLD are physically connected through a power management bus, and on the basis, upgrade control signals are directly transmitted through the power management bus.

in step 502, when a low-level power supply control signal sent by a baseboard management controller is received, a voltage regulator controller sends a low-level second control signal to a motherboard CPLD, the low-level second control signal and a low-level upgrade control signal cause the motherboard CPLD to send a low-level first control signal to a CPU, where the power supply control signal is used to instruct the voltage regulator controller whether to supply power to the CPU, the second control signal is used to instruct a power supply state of the CPU corresponding to the power supply control signal of the voltage regulator controller, the first control signal is a signal sent by the baseboard management controller to the motherboard CPLD, the upgrade control signal is used to instruct an upgrade state of firmware of the voltage regulator controller, and the upgrade state indicates whether the firmware of the voltage regulator controller is being upgraded.

Specifically, the CPU in the server is powered by the voltage-stabilizing controller, and the power-on time sequence is controlled by the main board CPLD (complex programmable logic device, complex Programmable Logic Device, abbreviated as CPLD), that is, the main board CPLD controls the change of the high-low level in the power-on time sequence of the CPU, when the power-on time sequence is high level, the voltage-stabilizing controller can only power the CPU, and when the power-on time sequence is low level, the voltage-stabilizing controller stops powering the CPU. The firmware in the voltage stabilizing controller usually needs to be upgraded, and cannot supply power to the CPU in the process of firmware upgrade, so that the firmware is usually upgraded when the CPU is in a power-off state, that is, the server is in a power-off state, and after the firmware upgrade of the voltage stabilizing controller is completed, the CPU needs to be powered up again, that is, the power-on state of the CPU is changed from a power-down state to a power-on state, and the power-on condition of the CPU is that the power-on is performed after all power supplies are powered up, in order to meet the power-on condition of the CPU, in step S402, the voltage stabilizing controller sends a low-level second control signal to the motherboard CPLD to indicate that the voltage stabilizing controller stops supplying power to the CPU.

Step 504, receiving the updated firmware file written by the baseboard management controller, and when the updated firmware file is successfully written by the voltage regulator controller, receiving the high-level power supply control signal sent by the baseboard management controller, and sending the high-level second control signal to the motherboard CPLD, so that the motherboard CPLD sends the high-level first control signal to the CPU after a delay of a preset period of time when receiving the high-level upgrade control signal sent by the baseboard management controller and the high-level second control signal sent by the voltage regulator controller.

Specifically, the voltage stabilizing controller receives the updated firmware file sent by the baseboard management controller, receives a high-level power supply control signal sent by the baseboard management controller to indicate that the firmware upgrade is successful when the updated firmware file is successfully written, supplies power to the CPU, and then sends a high-level second control signal to the motherboard CPLD to indicate that the power is supplied to the CPU. After receiving the high-level upgrade control signal and the high-level second control signal, the main board CPLD delays for a preset period of time, and sends the high-level first control signal to the CPU, where the starting time of the preset period of time is the time when the main board CPLD receives the high-level upgrade control signal and the high-level second control signal, and where the high-level upgrade control signal and the high-level second control signal are not simultaneously received by the main board CPLD, the starting time of the preset period of time is the time when the last received control signal, and specifically may be set according to a specific application scenario, for example: the preset time period may be set to 10ms. The numerical value of the above-mentioned preset time period is not particularly limited in the present application.

In some embodiments of the present application, when receiving the low-level power supply control signal sent by the baseboard management controller, the voltage stabilizing controller sends a low-level second control signal to the motherboard CPLD, including: determining whether a system in which the CPU is located is in a shutdown state; and when the system where the CPU is located is in the shutdown state and the voltage stabilizing controller receives the low-level power supply control signal sent by the baseboard management controller, the voltage stabilizing controller sends the low-level second control signal to the main board CPLD. By the method, the CPU is determined to be in the shutdown state, so that the situation that the CPU cannot be supplied with power caused by firmware upgrading of the voltage stabilizing controller can be avoided.

Specifically, as described in the background art, the firmware upgrade of the voltage regulator controller needs to be performed when the server is in a shutdown state, that is, when the CPU of the server is in a shutdown state, and therefore, before a low level second control signal is sent to indicate that the voltage regulator controller is about to perform the firmware upgrade, it needs to be determined whether the CPU is in a shutdown state first.

In some embodiments of the present application, the low-level first control signal is sent by the motherboard CPLD when receiving the low-level upgrade control signal sent by the baseboard management controller and the low-level second control signal sent by the voltage regulator controller. Thus, the firmware indicated by the upgrade control signal with low level and the second control signal with low level is to be upgraded and sent to the main board CPLD, so that the main board CPLD sends the first control signal with low level to inform the CPU to power down.

Specifically, the voltage regulator controller sends a low-level second control signal to the motherboard CPLD to indicate that the voltage regulator controller stops supplying power to the CPU, while a low-level upgrade control signal is sent by the baseboard management controller to the motherboard CPLD to indicate that the baseboard management controller is about to upgrade the firmware of the voltage regulator controller, so that the low-level first control signal is sent by the motherboard CPLD when receiving the low-level upgrade control signal sent by the baseboard management controller and the low-level second control signal sent by the voltage regulator controller.

In some embodiments of the present application, the upgrade control signal with a high level is sent by the baseboard management controller when the verification completion instruction represents that the verification is successful, where the verification completion instruction is an instruction obtained after the baseboard management controller verifies a firmware file written into the voltage stabilizing controller. By the method, after the firmware upgrade is completed, the baseboard management controller can be enabled to send a high-level upgrade control signal to the mainboard CPLD to indicate that the firmware upgrade is completed.

Specifically, the upgrade control signal with high level is sent by the baseboard management controller after the updated firmware file is written into the voltage stabilizing controller and the firmware file is written successfully, and because the baseboard management controller checks the firmware written into the voltage stabilizing controller, whether the writing is successful or not is judged through the checking completion instruction, the firmware file is written successfully under the condition that the checking completion instruction is characterized as successful, and the firmware file is written failed under the condition that the checking completion instruction is characterized as failed.

In some embodiments of the present application, the high-level first control signal is sent by the motherboard CPLD when receiving the high-level upgrade control signal sent by the baseboard management controller and the high-level second control signal sent by the voltage regulator controller. According to the method, after the firmware of the voltage stabilizing controller is successfully upgraded, the main board CPLD is informed of the success of the upgrade through the upgrade control signal of the high level and the second control signal of the high level, so that the main board CPLD sends the first control signal of the high level to the CPU to indicate that the power-on can be performed.

In some embodiments of the present application, the high level of the first control signal is used to control the voltage regulator controller to power up the CPU. Thus, the CPU can be powered on under the condition of meeting the power-on time sequence.

Specifically, after the firmware of the voltage stabilizer is successfully upgraded, the power supply control signal is high level, the first control signal is changed from low level to high level, the power-on time sequence of the CPU meets the power-on condition, and the voltage stabilizer controller can be controlled to power on the CPU.

In order to enable those skilled in the art to more clearly understand the technical solutions of the present application, the implementation process of the control method of the CPU power-on timing of the present application will be described in detail below with reference to specific embodiments.

The embodiment relates to a specific control method flow chart of a CPU power-on time sequence, as shown in fig. 4 and 5, comprising the following steps:

step S1: before the BMC (baseboard management Controller) prepares an FW (firmware) file of an online upgrade VR Controller, the server is powered off and enters an S5 state (power-off state);

step S2: the BMC (baseboard management controller) writes a CPLD register of the main board through the I2C, writes BMC_VR_UPDATE (upgrade control signal) into 0 (default 1), and informs the main board CPLD that the upgrade of VR_FW (firmware of the voltage-stabilizing controller) is started;

Step S3: the CPLD outputs bmc_vr_update (upgrade control signal) =0, continuously pulling rsmrst_n (first control signal of low level);

step S4: the BMC writes a VR Controller register through a PMBUS (power management bus), and turns off the output of S5_VR (power supply control signal) (low level);

step S5: the BMC writes VR FW (updated firmware file of the voltage stabilizing Controller) to VR Controller through PMBUS (power management bus) and checks, and carries out the next step when the writing is successful, and continuously carries out the step S5 when the writing is failed;

step S6: the BMC writes a VR Controller register through a PMBUS (power management bus), the S5_VR (power supply control signal) output is opened, a high level is output, and meanwhile, the VR Controller output VR_PWRGD (second control signal) is changed from a low level to a high level;

step S7: the BMC writes a CPLD register through the I2C, informs the CPLD of BMC_VR_UPDATE=1 (high-level upgrade control signal) that the upgrade of VR_FW (firmware of the voltage-stabilizing controller) is completed;

step S8: the CPLD acquires that VR_PWRGD (second control signal) changes from low level to high level, judges that S5_VR (power supply control signal changes from 0 to 1) normally supplies power, and meanwhile BMC_VR_UPDATE (upgrade control signal) changes from 0 to 1, and outputs RSMRST_N=1 (first control signal of high level) after delaying for 10 ms;

Step S9: the FW (firmware) file of CPU VR Controller (voltage regulator controller) is updated online.

From the description of the above embodiments, it will be clear to a person skilled in the art that the method according to the above embodiments may be implemented by means of software plus the necessary general hardware platform, but of course also by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/R second control signal M, magnetic disk, optical disk), comprising several instructions for causing a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method described in the embodiments of the present application.

The embodiment also provides a control device for the power-on time sequence of the CPU, which is used for implementing the foregoing embodiments and preferred embodiments, and is not described again. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

Fig. 6 is a block diagram of a control device for a CPU power-on sequence according to an embodiment of the present application, as shown in fig. 6, including:

a writing module 22, configured to, when the motherboard CPLD sends a low-level first control signal to the CPU, obtain an updated firmware file by the baseboard management controller, write the updated firmware file into the firmware of the voltage regulator controller, and upgrade the firmware of the voltage regulator controller, where the low-level first control signal is sent by the motherboard CPLD when receiving a low-level upgrade control signal sent by the baseboard management controller and a low-level second control signal sent by the voltage regulator controller, where the upgrade control signal is used to indicate an upgrade state of the firmware of the voltage regulator controller, where the upgrade state indicates whether the firmware of the voltage regulator controller is being upgraded, and where the second control signal is used to indicate a power supply state of the CPU corresponding to a power supply control signal of the voltage regulator controller, and where the first control signal indicates a power supply timing of the CPU;

and a transmitting module 24 configured to determine whether the updated firmware file is successfully written into the firmware of the voltage regulator controller, and if the updated firmware file is successfully written, transmit the upgrade control signal with a high level to the motherboard CPLD, where the upgrade control signal with a high level and the second control signal with a high level cause the motherboard CPLD to transmit the first control signal with a high level to the CPU after delaying for a preset period of time, where the second control signal with a high level is a signal that the voltage regulator controller transmits to the motherboard CPLD when receiving the power supply control signal with a high level.

In some embodiments of the present application, the writing module includes a determining submodule and a first obtaining submodule, where the determining submodule is used to determine whether a system where the CPU is located is in a shutdown state; the acquiring submodule is used for acquiring the updated firmware file under the condition that the system where the CPU is located is in the shutdown state and the baseboard management controller outputs the first control signal with low level on the main board CPLD. By the device, the updated firmware file is obtained only when the CPU is determined to be in the shutdown state, so that the firmware of the voltage-stabilizing controller is updated, and the situation that the CPU cannot be supplied with power due to the fact that the firmware is updated by the voltage-stabilizing controller can be avoided.

In some embodiments of the present application, the first sending module includes a second obtaining sub-module, a first determining sub-module, and a second determining sub-module, where the first sending sub-module is configured to verify the updated firmware file written into the voltage regulator controller, and obtain a verification completion instruction; the first determining submodule is used for determining that the updated firmware file is successfully written under the condition that the verification completion instruction represents that verification is successful; the second determining submodule is used for determining that the updated firmware file fails to be written in under the condition that the verification completion instruction represents verification failure. By the device, the voltage stabilizing controller can conveniently judge whether the firmware of the voltage stabilizing controller is upgraded or not so as to determine whether to continue to execute subsequent steps.

In some embodiments of the present application, the apparatus further includes: and the writing sub-module is used for writing the updated firmware file into the voltage stabilizing controller again when the updated firmware file fails to be written. By the device, under the condition of writing failure, the firmware file is written again, so that the condition that the writing of the firmware file fails due to accidental factors can be avoided, and the updated firmware file can be ensured to be written into the firmware of the voltage stabilizing controller, so that the firmware of the voltage stabilizing controller is upgraded.

In some embodiments of the present application, the writing module includes a writing sub-module, configured to write the updated firmware file into the firmware of the voltage regulator controller through a power management bus. By means of the device, the firmware file can be transmitted from the baseboard management controller to the voltage stabilizing controller without adding additional transmission equipment.

It should be noted that each of the above modules may be implemented by software or hardware, and for the latter, it may be implemented by, but not limited to: the modules are all located in the same processor; alternatively, the above modules may be located in different processors in any combination.

Embodiments of the present application also provide a computer readable storage medium having a computer program stored therein, wherein the computer program is configured to perform the steps of any of the method embodiments described above when run.

In one exemplary embodiment, the computer readable storage medium may include, but is not limited to: a usb disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing a computer program.

Embodiments of the present application also provide an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.

In an exemplary embodiment, the electronic device may further include a transmission device connected to the processor, and an input/output device connected to the processor.

Specific examples in this embodiment may refer to the examples described in the foregoing embodiments and the exemplary implementation, and this embodiment is not described herein.

It will be appreciated by those skilled in the art that the modules or steps of the application described above may be implemented in a general purpose computing device, they may be concentrated on a single computing device, or distributed across a network of computing devices, they may be implemented in program code executable by computing devices, so that they may be stored in a storage device for execution by computing devices, and in some cases, the steps shown or described may be performed in a different order than that shown or described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple modules or steps of them may be fabricated into a single integrated circuit module. Thus, the present application is not limited to any specific combination of hardware and software.

The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application should be included in the protection scope of the present application.

Claims

1. The control method of the CPU power-on time sequence is characterized by comprising the following steps:

under the condition that a low-level first control signal is sent to a CPU by a main board CPLD, a baseboard management controller acquires an updated firmware file, the updated firmware file is written into firmware of a voltage stabilizing controller to upgrade the firmware of the voltage stabilizing controller, wherein the low-level first control signal is sent by the main board CPLD under the condition that a low-level upgrade control signal sent by the baseboard management controller and a low-level second control signal sent by the voltage stabilizing controller are received, the upgrade control signal is used for indicating the upgrade state of the firmware of the voltage stabilizing controller, the upgrade state indicates whether the firmware of the voltage stabilizing controller is being upgraded, the second control signal is used for indicating the power supply state of the CPU corresponding to the power supply control signal of the voltage stabilizing controller, and the first control signal indicates the power-on time sequence of the CPU;

Determining whether the updated firmware file is successfully written into the firmware of the voltage stabilizing controller, and under the condition of successful writing, transmitting a high-level upgrade control signal to the main board CPLD, wherein the high-level upgrade control signal and the high-level second control signal enable the main board CPLD to transmit the high-level first control signal to the CPU after delaying for a preset time period, and the high-level second control signal is a signal transmitted to the main board CPLD by the voltage stabilizing controller under the condition of receiving the high-level power supply control signal.

2. The control method according to claim 1, wherein, in the case where the main board CPLD sends the first control signal of the low level to the CPU, the baseboard management controller acquires the updated firmware file, comprising:

determining whether a system in which the CPU is located is in a shutdown state;

and when the system where the CPU is located is in the shutdown state and the baseboard management controller outputs the first control signal with low level, acquiring the updated firmware file.

3. The control method according to claim 1, wherein the second control signal of a low level is issued by the voltage stabilizing controller upon receiving the power supply control signal of a low level transmitted by the baseboard management controller.

4. The control method according to claim 1, wherein determining whether the updated firmware file is successfully written in the firmware of the voltage regulator controller comprises:

checking the updated firmware file written into the voltage stabilizing controller to obtain a checking completion instruction;

under the condition that the verification completion instruction represents that verification is successful, determining that the updated firmware file is successfully written;

and under the condition that the verification completion instruction represents verification failure, determining that the updated firmware file fails to be written.

5. The control method according to claim 1, wherein the first control signal of a high level is issued by the main board CPLD upon receiving the upgrade control signal of a high level transmitted by the baseboard management controller and the second control signal of a high level transmitted by the voltage regulator controller.

6. The control method according to claim 1, characterized in that the method further comprises:

and under the condition that the updated firmware file fails to be written, writing the updated firmware file into the voltage stabilizing controller again.

7. The control method according to any one of claims 1 to 6, characterized in that writing the updated firmware file to firmware of a voltage regulator controller includes:

And writing the updated firmware file into the firmware of the voltage stabilizing controller through a power management bus.

8. The control method of the CPU power-on time sequence is characterized by comprising the following steps:

under the condition that a low-level upgrading control signal sent by a baseboard management controller and a low-level second control signal sent by a voltage stabilizing controller are received, a mainboard CPLD sends a low-level first control signal to a CPU, wherein the upgrading control signal is used for indicating the upgrading state of firmware of the voltage stabilizing controller, the upgrading state indicates whether the firmware of the voltage stabilizing controller is being upgraded or not, the second control signal is used for indicating the power supply state of the CPU corresponding to the power supply control signal of the voltage stabilizing controller, and the first control signal indicates the power-on time sequence of the CPU;

and receiving the high-level upgrade control signal sent by the baseboard management controller and the high-level second control signal sent by the voltage stabilizing controller, and after delaying for a preset time period, sending the high-level first control signal to the CPU, wherein the high-level upgrade control signal and the high-level second control signal are generated and sent by triggering in the process that an updated firmware file is successfully written into the firmware of the voltage stabilizing controller, the updated firmware file is used for upgrading the firmware of the voltage stabilizing controller, and the firmware of the voltage stabilizing controller is triggered by the low-level upgrade control signal.

9. The control method according to claim 8, wherein, in the case of receiving the low-level upgrade control signal transmitted by the baseboard management controller and the low-level second control signal transmitted by the voltage regulator controller, the main board CPLD transmits the low-level first control signal to the CPU, comprising:

and when the system where the CPU is located is in the shutdown state and the main board CPLD receives the low-level upgrading control signal sent by the baseboard management controller and the low-level second control signal sent by the voltage stabilizing controller, the low-level first control signal is sent to the CPU.

10. The control method according to claim 8, wherein the second control signal of a low level is issued by the voltage stabilizing controller upon receiving the power supply control signal of a low level transmitted by the baseboard management controller.

11. The control method according to claim 8, wherein the upgrade control signal of a high level is issued by the baseboard management controller when a verification completion instruction characterizes verification success, wherein the verification completion instruction is an instruction obtained after the baseboard management controller verifies a firmware file written into the voltage regulator controller.

12. The control method according to claim 8, wherein the second control signal of a high level is issued by the voltage stabilizing controller upon receiving the power supply control signal of a high level transmitted from the baseboard management controller.

13. The control method according to claim 8, characterized by further comprising, after transmitting the first control signal of a high level to the CPU:

and controlling the voltage stabilizing controller to electrify the CPU according to the first control signal with high level.

14. The control method according to any one of claims 8 to 13, characterized in that the upgrade control signal is transmitted by receiving the baseboard management controller through an I2C bus.

15. The control method of the CPU power-on time sequence is characterized by comprising the following steps:

under the condition that a low-level power supply control signal sent by a baseboard management controller is received, a voltage stabilizing controller sends a low-level second control signal to a main board CPLD, the low-level second control signal and a low-level upgrading control signal enable the main board CPLD to send a low-level first control signal to a CPU, wherein the power supply control signal is used for indicating whether the voltage stabilizing controller supplies power to the CPU or not, the second control signal is used for indicating a power supply state of the CPU corresponding to the power supply control signal of the voltage stabilizing controller, the first control signal represents a power-on time sequence of the CPU, the low-level upgrading control signal is a signal sent by the baseboard management controller to the main board CPLD, and the upgrading control signal is used for indicating the upgrading state of firmware of the voltage stabilizing controller and indicates whether the firmware of the voltage stabilizing controller is being upgraded or not;

And receiving an updated firmware file written by the baseboard management controller, and receiving the high-level power supply control signal sent by the baseboard management controller under the condition that the updated firmware file is successfully written by the voltage stabilizing controller, and sending the high-level second control signal to the main board CPLD, so that the main board CPLD sends the high-level first control signal to the CPU after delaying a preset time period under the condition that the high-level upgrade control signal sent by the baseboard management controller and the high-level second control signal sent by the voltage stabilizing controller are received.

16. The control method according to claim 15, wherein the voltage regulator controller sends the second control signal of the low level to the main board CPLD in the case of receiving the power supply control signal of the low level sent by the baseboard management controller, comprising:

and when the system where the CPU is located is in the shutdown state and the voltage stabilizing controller receives the low-level power supply control signal sent by the baseboard management controller, sending the low-level second control signal to the mainboard CPLD.

17. The control method according to claim 15, wherein the first control signal of a low level is issued by the main board CPLD upon receiving the upgrade control signal of a low level transmitted by the baseboard management controller and the second control signal of a low level transmitted by the voltage regulator controller.

18. The control method according to claim 15, wherein the upgrade control signal of a high level is issued by the baseboard management controller in a case that a verification completion instruction characterizes verification success, wherein the verification completion instruction is an instruction obtained after the baseboard management controller verifies a firmware file written into the voltage regulator controller.

19. The control method according to claim 15, wherein the first control signal of a high level is issued by the main board CPLD upon receiving the upgrade control signal of a high level transmitted by the baseboard management controller and the second control signal of a high level transmitted by the voltage regulator controller.

20. The control method according to any one of claims 15 to 19, characterized in that the first control signal of a high level is used to control the voltage regulator controller to power up the CPU.

21. A control device for a CPU power-on timing, comprising:

the writing module is used for acquiring an updated firmware file by the baseboard management controller under the condition that the mainboard CPLD sends a low-level first control signal to the CPU, writing the updated firmware file into the firmware of the voltage stabilizing controller to upgrade the firmware of the voltage stabilizing controller, wherein the low-level first control signal is sent by the mainboard CPLD under the condition that the low-level upgrade control signal sent by the baseboard management controller and the low-level second control signal sent by the voltage stabilizing controller are received, the upgrade control signal is used for indicating the upgrade state of the firmware of the voltage stabilizing controller, the upgrade state indicates whether the firmware of the voltage stabilizing controller is being upgraded or not, the second control signal is used for indicating the power supply state of the CPU corresponding to the power supply control signal of the voltage stabilizing controller, and the first control signal indicates the power-on time sequence of the CPU;

and the sending module is used for determining whether the updated firmware file is successfully written into the firmware of the voltage stabilizing controller, and sending a high-level upgrade control signal to the main board CPLD under the condition of successful writing, wherein the high-level upgrade control signal and the high-level second control signal enable the main board CPLD to send the high-level first control signal to the CPU after delaying for a preset time period, and the high-level second control signal is a signal sent to the main board CPLD by the voltage stabilizing controller under the condition of receiving the high-level power supply control signal.

22. A control device for a CPU power-on timing, comprising:

the first sending module is used for sending a low-level first control signal to the CPU under the condition that a low-level upgrading control signal sent by the baseboard management controller and a low-level second control signal sent by the voltage stabilizing controller are received, wherein the upgrading control signal is used for indicating the upgrading state of the firmware of the voltage stabilizing controller, the upgrading state is used for indicating whether the firmware of the voltage stabilizing controller is being upgraded or not, the second control signal is used for indicating the power supply state of the CPU corresponding to the power supply control signal of the voltage stabilizing controller, and the first control signal is used for indicating the power-on time sequence of the CPU;

and the second sending module is used for receiving the high-level upgrade control signal sent by the baseboard management controller and the high-level second control signal sent by the voltage stabilizing controller, and sending the high-level first control signal to the CPU after delaying for a preset time period, wherein the high-level upgrade control signal and the high-level second control signal are generated and sent by triggering in the firmware of the voltage stabilizing controller when updated firmware files are successfully written in the firmware of the voltage stabilizing controller, the updated firmware files are used for upgrading the firmware of the voltage stabilizing controller, and the firmware of the voltage stabilizing controller is triggered by the low-level upgrade control signal.

23. A control device for a CPU power-on timing, comprising:

the first sending module is configured to send a low-level second control signal to a motherboard CPLD by the voltage regulator controller when receiving a low-level power supply control signal sent by the baseboard management controller, where the low-level second control signal and a low-level upgrade control signal are used to enable the motherboard CPLD to send a low-level first control signal to a CPU, the power supply control signal is used to indicate whether the voltage regulator controller supplies power to the CPU, the second control signal is used to indicate a power supply state of the CPU corresponding to the power supply control signal of the voltage regulator controller, the first control signal indicates a power-on time sequence of the CPU, the low-level upgrade control signal is a signal sent by the baseboard management controller to the motherboard CPLD, and the upgrade control signal is used to indicate an upgrade state of firmware of the voltage regulator controller, where the upgrade state indicates whether the firmware of the voltage regulator controller is being upgraded;

the second sending module is configured to receive the updated firmware file written by the baseboard management controller, receive the high-level power supply control signal sent by the baseboard management controller when the updated firmware file is successfully written by the voltage stabilizing controller, and send the high-level second control signal to the motherboard CPLD, so that the motherboard CPLD sends the high-level first control signal to the CPU after delaying a preset time period when receiving the high-level upgrade control signal sent by the baseboard management controller and the high-level second control signal sent by the voltage stabilizing controller.

24. A computer readable storage medium, characterized in that the computer readable storage medium has stored therein a computer program, wherein the computer program when executed by a processor realizes the steps of the method of any of claims 1 to 7, or the steps of the method of any of claims 8 to 14, or the steps of the method of any of claims 15 to 20.

25. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor, when executing the computer program, implements the steps of the method of any one of claims 1 to 7, or the steps of the method of any one of claims 8 to 14, or the steps of the method of any one of claims 15 to 20.