CN103810113B - A kind of fusion memory system of nonvolatile storage and dynamic random access memory - Google Patents

A kind of fusion memory system of nonvolatile storage and dynamic random access memory Download PDF

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CN103810113B
CN103810113B CN201410041777.2A CN201410041777A CN103810113B CN 103810113 B CN103810113 B CN 103810113B CN 201410041777 A CN201410041777 A CN 201410041777A CN 103810113 B CN103810113 B CN 103810113B
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nonvolatile storage
memory
fusion
dram
data
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CN103810113A (en
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冯丹
刘景宁
童薇
冒伟
周文
张双武
李铮
罗锐
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Huazhong University of Science and Technology
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Abstract

The invention discloses the fusion memory system of a kind of nonvolatile storage and dynamic random access memory, nonvolatile storage and dynamic random access memory are merged, internal memory unified management collectively as computer system, wherein dynamic random access memory both can with nonvolatile storage unified addressing, the cache memory (cache) of nonvolatile storage can also be served as with portion capacity, the amount of capacity self-adapting data load properties in its cache space and dynamically can join, to accelerate the access speed of nonvolatile storage, and I/O access disk frequency can be reduced, improve computer system overall performance.

Description

A kind of fusion memory system of nonvolatile storage and dynamic random access memory
Technical field
The invention belongs to Computer Storage field, be specifically related to the fusion memory system of a kind of nonvolatile storage and dynamic random access memory.
Background technology
The appearance of novel nonvolatile memory (Non-VolatileMemory, NVM), provides new approach for extension calculator memory, has simultaneously facilitated computer change in system structure.Existing NVM has PCM (PhaseChangeMemory, phase transition storage), STT-RAM (SpinTransferTorqueRandomAccessMemory, spin-transfer torque random access memory), MRAM (MagneticRandomAccessMemory, magnetic RAM device), FeRAM (FerroelectricRandomAccessMemory, Ferroelectric Random Access Memory) etc..nullThe electric charge stream storage data that the utilization that the Ultrahigh of novel nonvolatile memory is no longer traditional electronically forms,But utilize magnetoresistance、Resistive effect should、Cholesteric-nematic transition etc. mechanism like this realizes the storage of data,Such characteristic makes them be provided with many legacy memory will not to have the advantage that,If phase transition storage is a kind of novel nonvolatile memory being made up of chalcogenide material,It utilizes the reversible phase transformation of material to store information,Phase-change memory material can occur from non-crystal state to crystal state under certain condition,Return again to the change of non-crystal state,Non-crystal state and crystal state in the process present different resistance characteristics and optical characteristics,Therefore,Amorphous state and crystalline state can be utilized to represent respectively, and " 0 " and " 1 " stores data,It provide non-volatile、Low energy consumption、The features such as random read-write speed is fast.Current Samsung and company of Micron Technology are proposed the PCM chip of 90nm and 45nm processing procedure successively.
The research in computer memory system field of the current novel nonvolatile storage, Main way has two: one to be use as external equipment, two is adopt nonvolatile storage and DRAM as mixing internal memory (HybridMemory), and namely DRAM is the cache of nonvolatile storage.
For DRAM, nonvolatile storage has non-volatile, it is possible to retain data for a long time, has high density characteristic simultaneously, and the development further of memory techniques is provided support by this;But meanwhile nonvolatile storage has relatively large delay, and writing speed and DRAM also have gap, the life-span of part nonvolatile storage is also relatively limited, if thinking, it can substitute DRAM, it is necessary for overcoming the problems such as himself life-span, energy consumption and delay, but existing research all carries out just for some in these problems mostly, do not consider and overcome many-sided restriction, therefore nonvolatile storage individually does internal memory and there is also a lot of challenge and predicament, also cannot accomplish the complete replacer of DRAM in a short time.At present normally only with the ROM portion of nonvolatile storage replacement computer original system, or research uses DRAM and nonvolatile storage to build mixing internal memory, namely the intermediate storage layer of computer memory system is made of nonvolatile storage, as: data storage passes sequentially through disk, nonvolatile storage, dynamic random access memory, Cache, CPU, data access level is too many, I/O path is long, does not give full play of the feature of nonvolatile storage.
Summary of the invention
Given this, it is an object of the invention to provide the fusion memory system of a kind of nonvolatile storage and dynamic random access memory, solution active computer internal memory power failure data is lost, starting up is slow, energy consumption reduces difficulty, frequently and the series of problems such as the IO degraded performance of disk swapping, can pass through dynamically to adjust the capacity merging core buffer space simultaneously, self adaptation application load is asked, and improves internal memory service efficiency.
A kind of nonvolatile storage of present invention proposition and the fusion memory system of dynamic random access memory, including:
Unified addressing, the nonvolatile storage (NVM) of unified management and dynamic random access memory (DRAM), wherein DRAM includes the DRAMcache part of serving as the cache of nonvolatile storage, and its spatial content is dynamically adapted;
Protocol conversion module, being used for nonvolatile storage phy chip package interface protocol conversion is the protocol memory that memory interface adopts;
Merge Memory Controller Hub, for according to nonvolatile storage and the work schedule of DRAM phy chip, upper strata call instruction and pin level signal condition, arranging worker state machine to complete corresponding operation, and provide the software interface driving memory chip;
Merge memory management module, for fusion internal memory is carried out unified management, dynamically adjust submodule including dram space capacity, wherein, described dram space capacity dynamically adjusts submodule for periodically monitoring the hit rate H of DRAMcache part, and detects read-write requests ratio R:
R=read request number ÷ write request number (1)
When hit rate H < K and read-write requests ratio R < during T, increasing DRAMcache capacity, wherein, K, T are predetermined threshold, and its value can custom-configure according to user's request, 0 < K < 1,0 < T < 1;
As hit rate H >=K and read-write requests ratio R >=T, reduce DRAMcache capacity.
Compared with prior art, the method have the advantages that the advantage having given play to nonvolatile storage and DRAM to greatest extent, by merging memory architecture, solve existing memory system power failure data lose, starting up slow, energy consumption reduces difficulty, frequently and the series of problems such as the IO degraded performance of disk swapping.
Accompanying drawing explanation
Fig. 1 is the fusion memory system Organization Chart of the embodiment of the present invention;
Fig. 2 is the fusion memory system hardware platform architecture figure of the embodiment of the present invention;
Fig. 3 is the non-volatile fusion internal memory hardware structure figure of the embodiment of the present invention;
Fig. 4 is the fusion memory management module figure of the embodiment of the present invention;
Fig. 5 is that parallel framework merges memory modules figure;
Fig. 6 is that vertical configuration merges memory modules figure.
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage clearly understand, below in conjunction with accompanying drawing and exemplary embodiment, the present invention is further elaborated.Should be appreciated that exemplary embodiment described herein is only in order to explain the present invention, the scope of application being not intended to limit the present invention.
Hereinafter, the fusion memory system of the embodiment of the present invention is described: merge memory system overall architecture, merge memory system hardware platform and merge memory management module from three aspects.
One, memory system overall architecture is merged
As shown in Figure 1, the fusion memory system of the embodiment of the present invention adopt nonvolatile storage (NVM) and dynamic random access memory (DRAM) build internal memory, CPU accesses fusion memory system by merging Memory Controller Hub, so-called fusion, namely the reflection in system level is addressing and the allocation manager scheme of the memory system being made up of nonvolatile storage and dynamic random access memory.
According to DRAM device location in the architecture, DRAM device is divided into two parts:
A part of DRAM is equal with the status of nonvolatile storage, and they carry out unified addressing, unified management, and both collectively form traditional internal memory.The feature of internal storage data is accessed, it is possible to directly data are stored in the dynamic random access memory part of internal memory or the nonvolatile storage part of internal memory according to CPU;
Another part DRAM serves as the cache of nonvolatile storage, for covering and alleviating the delay performance that nonvolatile storage is poor relative to DRAM, is called DRAMcache.The amount of capacity of this part dram space dynamically can be joined, and namely according to information such as the characteristic of upper layer data load and access frequencys, can dynamically adjust amount of capacity adaptively.
For whole fusion memory system, it is to DRAM and nonvolatile storage unified addressing, unified management, its address range for 0~n, upper strata can be regarded as a whole internal memory, concrete device type is invisible.Wherein, the address of nonvolatile storage part is a part for unified addressing, and this partial address immobilizes;The address of DRAM is another part of unified addressing, it is possible to dynamically change.Noticing that the address realm A of cache DRAM herein be 0~X, X is the maximum address of DRAM, address realm A dynamically adjusts according to the characteristic of upper layer request.Such as, if request is to read to write few type more, then A will diminish, and namely directly allows read request occur on nonvolatile storage;On the contrary, if request is to read to write many types less, then A can become big, namely utilizes more DRAM to serve as the cache of nonvolatile storage, to cover its writing rate, and improves the life-span.
Two, memory system hardware platform is merged
Adopt the embedded-development environment including but not limited to the processors such as ARM, FPGA, at these platform upper, memory system is merged in administration, make processor identification access fusion internal memory in the way of internal memory, it is achieved based on the fusion memory system of nonvolatile storage and DRAM.
(1) hardware platform overall architecture
As in figure 2 it is shown, hardware platform overall architecture includes with next several parts:
Processor module, includes but not limited to the processors such as ARM, FPGA;
Multiple internal memory physical interfaces, for providing the signaling protocol meeting memory techniques standard.Above-mentioned memory interface technical standard can be existing memory interface technical standard, such as DDR2, DDR3 etc..In these internal memory physical interfaces, reserve design system and have to use for memory interface, as processor controls the I/O mouth etc. that uses of corresponding internal memory, also to reserve the memory interface merged in memory system required for nonvolatile storage and DRAM device.
SD card interface module, is configured by SD card and starts processor system;
Universal serial port turns usb interface module, it is provided that debugging serial port function;
PCIe interface module, according to user's request and self-defined, support PCIe series (include a PCIe generation, secondary lower multiple passage configuration) physical layer protocol so that this hardware platform communicates with PCIe interface (PCIe2.0X8) and the HPI of definition;
Power supply adaptor module, supporting with ATX power interface, it is provided that multiple adaptive I/O mouth level, as provided 1.2V, 1.5V, 1.8V, 2.5V, 3.3V etc.;
Clock management module, for producing the clock required for corresponding module.
(2) nonvolatile storage merges internal memory hardware
Nonvolatile storage merges the concrete framework of internal memory hardware as shown in Figure 3, its mentality of designing is as follows: based on certain series of non-volatile memory chip, design and make nonvolatile storage and merge internal memory, this internal memory hardware interface type follows the memory standard signaling protocol that mainboard internal memory physical interface adopts, corresponding standard physical interface is provided, can be connected in memory interface with set form, support the DRAM internal memory hardware of same standard agreement simultaneously, by merging memory management and merging the work of Memory Controller Hub, make processor can access nonvolatile storage memorizer and DRAM memory according to the access mode of internal memory, realize the fusion memory system based on nonvolatile storage and dynamic randon access.
Wherein, owing to the interface protocol of internal storage access is standard agreement, and the nonvolatile storage phy chip on current market not all have employed the communication protocol consistent with memory standard.Therefore, in order to realize memorymodel access nonvolatile storage, it is necessary to change between the protocol memory that memory interface module adopts in nonvolatile memory chip package interface agreement and hardware plan overall architecture, or complete compatibility.For this, this fusion internal memory hardware includes a protocol conversion module, and being used for nonvolatile storage phy chip package interface protocol conversion is the protocol memory that memory interface adopts.
Meanwhile, level between distinct interface agreement needs isolation and changes that (the support level such as Micron Technology's LPDDR2 Series PC M chip is 1.2V, P8P series is 3.3V, and the level of DDR3 agreement support is 1.5V, the level of DDR2 agreement support is 1.8V), it is therefore preferred that, this fusion internal memory hardware also includes a level switch module, completes the level isolation between distinct interface agreement and conversion.
The concrete form of non-volatile memory hardware can be memory bar, according to demand selected nonvolatile memory chip, forms storage array;It can also be the form inserting subcard in master card, each subcard can adopt multi-disc, the operations such as constituting certain capacity solid state memory space, in subcard, each nonvolatile memory chip is an independent passage, the read-write between multiple subcards can complete parallel.
(3) Memory Controller Hub is merged
As traditional Memory Controller Hub, merge Memory Controller Hub according to nonvolatile storage and the work schedule of DRAM phy chip, upper strata call instruction and pin level signal condition, worker state machine is set to complete corresponding operation, and the software interface driving memory chip is provided.The hardware aspect of Memory Controller Hub, according to the order that the state machine and current upper strata that merge memory chip work call, completes corresponding operating;The software aspects of Memory Controller Hub, it is provided that to the function interface merging each orders such as memory system read-write.In Memory Controller Hub, the specific design of state machine is the state of the art, does not repeat them here.
Three, memory management module is merged
For the internal memory that nonvolatile storage is different with DRAM two class, merge memory management module and need to consider layout and the migration of data, pluses and minuses according to two class memorizeies, rationally place data, the internal storage data deposited in nonvolatile storage and DRAM is made to have certain difference, very fast to embody DRAM access rate, the feature that PCM is non-volatile, to crucial data if desired for height unanimously reliable metadata information, quickly starting and need configuration information, read-only system information is directly placed in nonvolatile storage.The memory space of both Appropriate application simultaneously, using the part DRAM internal memory Cache as nonvolatile storage, the data often accessed are placed in DRAM, nonvolatile storage stores as the rear end of DRAM, utilize the feature that DRAM access speed is fast, the shortcoming covering the write delay length of nonvolatile storage, and decrease nonvolatile storage write number of times, be beneficial to non-volatile storage life and write the restriction of energy consumption.Also having given play to the characteristic that nonvolatile storage power down is non-volatile, data consistency is good, persistence internal storage data simultaneously.
As shown in Figure 4, in the embodiment of the present invention, merge memory management module and carry out unified management to merging internal memory, including cold and hot data identification submodule, Data Migration submodule, initialization submodule, read-write requests scheduling sublayer module, address mapping submodule, wear leveling submodule etc..
Cold and hot data identification submodule: judge the cold and hot property accessing data according to access frequency and the time of access.Wherein, namely consider the temperature of data itself, it is further contemplated that many factors such as principles of locality during routine access, for nonvolatile storage used, dispose cold and hot data recognition mechanism;
Data Migration submodule: the recognition result according to cold and hot data, the data of cold data will be identified as in DRAM, move in DRAMcache or NVM (the Data Migration direction determining to be identified as by DRAM cold data with specific reference to the characteristic of selected NVM), by being identified as the data of dsc data in DRAMcache, move in DRAM.Such advantage is in that, make full use of the advantage that the read-write speed of DRAM is fast, reduce the time of data migration operation and postpone expense, simultaneously when data migrate in succession between, inreal is written in nonvolatile storage, decrease the write of redundancy or unnecessary data in nonvolatile storage device, be conducive to the life-span of nonvolatile storage;
Initialization submodule: when system first time initializes, predetermined critical data (such as the information needed for system start-up, needing high consistent metadata information reliably) is imported in nonvolatile storage.When follow-up operation, critical data also leaves in nonvolatile storage, is so started the next time making system and quickly carries out, and is no longer necessary to again import log-on message.
Read-write requests scheduling sublayer module: after upper layer request is assigned, issues address according to what request characteristic determined request, then request command is issued to fusion Memory Controller Hub, finally arrives and merge internal memory accordingly.Described request characteristic includes read-write type ratio, request load characteristic etc..
Address mapping submodule: for merging the address mapping table that memory system remains unified.This table leaves in nonvolatile storage, the logical address merging internal memory is separated with physical address, it is simple to carry out abrasion equilibrium and the read-write requests scheduling of nonvolatile storage device.
Abrasion equilibrium submodule: the read-write number of times of monitoring nonvolatile storage, utilizes Address Mapping to realize the abrasion equilibrium of nonvolatile storage when carrying out upper layer request distribution.Preferably, it is also possible to take into account Mobile state abrasion equilibrium in nonvolatile storage region, as being periodically written and read the exchange of thermal region address.Particularly as follows: add up the reading number of times of nonvolatile storage each region generation and write number of times, between read operation region and write operation region that I/O frequently occurs, carry out data, address replacement.
Preferably, merge memory management module and also include performance optimization submodule: perform optimisation strategy according to the characteristic of nonvolatile storage, including reducing write delay, writing time-out and write cancellation etc..Wherein, owing to the nonvolatile storage write delay relative to DRAM is bigger, and the restricted lifetime of nonvolatile storage, therefore to the performance optimisation mechanism of fusion memory system mainly for the write performance optimization of nonvolatile storage device, energy optimization etc., and solve nonvolatile storage restriction in life-span, write operation delay and energy consumption etc., the overall performance promoting fusion memory system to greatest extent.
Further, fusion memory management module also includes dram space capacity and dynamically adjusts submodule: the periodically hit rate H of monitoring DRAMcache part, and detects read-write requests ratio R:
R=read request number ÷ write request number (1)
As hit rate H < K, (K is a predetermined threshold, its value can custom-configure according to user's request, 0 < K < 1) and read-write requests ratio R < during T, (T is a predetermined threshold, its value can custom-configure according to user's request, 0 < T < 1), DRAMcache capacity is increased.Concrete operations are that the DRAM of unified addressing is rejected space, subregion, and it is addressed in DRAMcache, increase amount of capacity is former DRAMcache capacity γ times (γ is the volume change factor, 0 < γ < 1, this value can also be configured by User Defined);
As hit rate H >=K and read-write requests ratio R >=T, reduce DRAMcache capacity.Concrete operations are in the unified addressing being addressed to by the segment space in DRAMcache and merging internal memory, and the amount of capacity of reduction is θ times (θ is the volume change factor, 0 < θ < 1, this value can also be configured by User Defined) of former DRAMcache capacity.
As can be seen here, this memory system emphasizes the fusion of nonvolatile storage and DRAM, namely both status and effect are no longer simple mixed architecture or the memory architecture of individual course existence, but " fusion architecture ", namely nonvolatile storage and DRAM collectively form unified memory, wherein DRAM will address with nonvolatile storage uniform spaces, meanwhile mark off segment space in DRAM and be the buffer memory cache of nonvolatile storage;Difference according to factors such as data payload features, the capacity of the cache segment space serving as nonvolatile storage in DRAM is dynamic and configurable;Namely load characteristic is had perception, flexible configuration DRAMcache amount of capacity, to improve the hit rate of DRAMcache, improves the performance merging memory system.
It is pointed out that DRAM capacity adjustment likely become two extreme: 1. parallel construction: namely all of DRAM all with nonvolatile storage unified addressing, be not acting as the cache of nonvolatile storage, as shown in Figure 5;2. vertical stratification: namely all of DRAM act as the cache of nonvolatile storage, nonvolatile storage is as the rear end exented memory of DRAM, as shown in Figure 6.
Finally it may be noted that in the embodiment of the present invention that the nonvolatile storage merging memory system can be based on the memorizer of phase transition storage, it is also possible to be based on the memorizer of NANDFLASH or other can serve as the nonvolatile storage of internal memory.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all any amendment, equivalent replacement and improvement etc. made within the spirit and principles in the present invention, should be included within protection scope of the present invention.

Claims (10)

1. a fusion memory system for nonvolatile storage and dynamic random access memory, including:
Unified addressing, the nonvolatile storage (NVM) of unified management and dynamic random access memory (DRAM), wherein DRAM includes the DRAMcache part of serving as the cache of nonvolatile storage, and the spatial content of this DRAMcache part is dynamically adapted;
Protocol conversion module, being used for nonvolatile storage phy chip package interface protocol conversion is the protocol memory that memory interface adopts;
Merge Memory Controller Hub, for according to nonvolatile storage and the work schedule of DRAM phy chip, upper strata call instruction and pin level signal condition, arranging worker state machine to complete corresponding operation, and provide the software interface driving memory chip;
Merge memory management module, for fusion internal memory is carried out unified management, dynamically adjust submodule including dram space capacity, wherein, described dram space capacity dynamically adjusts submodule for periodically monitoring the hit rate H of DRAMcache part, and detects read-write requests ratio R:
R=read request number ÷ write request number (1)
When hit rate H < K and read-write requests ratio R < during T, increasing DRAMcache capacity, wherein, K, T are predetermined threshold, and its value can custom-configure according to user's request, 0 < K < 1,0 < T < 1;
As hit rate H >=K and read-write requests ratio R >=T, reduce DRAMcache capacity.
2. fusion memory system according to claim 1, also includes level switch module, has been used for the level isolation between distinct interface agreement and conversion.
3. fusion memory system according to claim 1, wherein, described fusion memory management module also includes cold and hot data identification submodule and Data Migration submodule, the described cold and hot data identification submodule cold and hot property for judging to access data according to access frequency and the time of access;Described Data Migration submodule, for the recognition result according to cold and hot data, will be identified as the data of cold data in DRAM, moves in DRAMcache or NVM, by being identified as the data of dsc data in DRAMcache, move in DRAM.
4. fusion memory system according to claim 1, wherein, described fusion memory management module also includes initialization submodule, for predetermined critical data being imported in nonvolatile storage when system first time initializes.
5. fusion memory system according to claim 1, wherein, described fusion memory management module also includes read-write requests scheduling sublayer module: after upper layer request is assigned, address is issued according to what request characteristic determined request, then request command is issued to fusion Memory Controller Hub, finally arrives and merge internal memory accordingly.
6. fusion memory system according to claim 1, wherein, described fusion memory management module also includes address mapping submodule, for for merging the address mapping table that memory system remains unified.
7. fusion memory system according to claim 1, wherein, described fusion memory management module also includes abrasion equilibrium submodule, for monitoring the read-write number of times of nonvolatile storage, utilizes Address Mapping to realize the abrasion equilibrium of nonvolatile storage when carrying out upper layer request distribution.
8. fusion memory system according to claim 7, wherein, described abrasion equilibrium submodule is additionally operable to the reading number of times of statistics nonvolatile storage each region generation and writes number of times, carries out data, address replacement between read operation region and write operation region that I/O frequently occurs.
9. fusion memory system according to claim 1, wherein, described fusion memory management module also includes performance optimization submodule, performs optimisation strategy for the characteristic according to nonvolatile storage, including reducing write delay, writing time-out and write cancellation.
10. fusion memory system according to claim 1, wherein, described nonvolatile storage be the memorizer based on phase transition storage (PCM), based on the memorizer of NANDFLASH or other can serve as the nonvolatile storage of internal memory.
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