JPH04369030A - Fault detecting system - Google Patents

Abstract

PURPOSE:To improve the reliability of request processing between a processor and a system controller. CONSTITUTION:A processor 0 (100) sends a request signal 13 to a system control device 101 and simultaneously writes request information in a request buffer 1 by means of a writing pointer 3. An arithmetic circuit 32 finds out exclusive OR between the value of the pointer 3 and the value of a processor number storing part 30 in accordance with the sending of the signal 13 and outputs a signal 33. The system controller 101 delays the signal 33 only by 5 machine cycles and outputs the delayed signal as a signal 28 together with a response signal 20. In the processor 0 (100), a signal 15 is read out of the buffer 1 by a reading pointer 2, exclusive OR between the value of the pointer 2 and the value of a processor number storing part 30 is found out by an arithmetic circuit 34 and compared with a signal 28, and at the time of detecting unmatched between both the signals, an error signal 16 is outputted.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure detection system in an information processing apparatus, and more particularly to a failure detection system associated with the processing of processing requests generated from a processing apparatus.

0002

2. Description of the Related Art Conventionally, in a system composed of a plurality of processing units, a system control unit, a main storage unit, etc.,
The structure was as follows. In other words, when a processing request such as memory access occurs in a processing device, the processing device sends a processing request to the system control device, and determines whether the processing request is a memory access, a write or a read, and other information regarding the processing request. Store the accompanying processing information in the request buffer. Processing requests are generated continuously within the processing device, and in order to improve the throughput of processing requests, processing requests are sent out one after another before a response to the processing request is returned. Therefore, the request buffer requires from several words to several tens of words, depending on the system performance.

This request buffer is controlled by a write pointer and a read pointer, and the write pointer is updated when a processing request is sent, and the read pointer is updated when a response to the processing request is returned. Further, as processing requests sent from the processing device to the system control device, only information necessary for actual processing such as addresses, commands, write data, write masks, etc. is sent.

[0004] Furthermore, the system control device has been configured to return only information such as main memory read data and processing request success information.

[0005]

[Problems to be Solved by the Invention] In the conventional configuration described above, it is difficult to correspond to processing requests and processing results due to incorrect updating of the write pointer and read pointer of the request buffer, etc., with respect to processing requests that occur continuously within the processing device. Discrepancies between processing requests and processing results due to interface failure between the processing device and system control device, mismatch between processing requests and processing results due to improper processing within the system control device, or processing device to which processing results are sent. Problems such as errors in data processing cannot be detected, and in the case of failures that occur in between, processes that have been mismatched will continue as they are, and in the worst case, this may cause data corruption. There is a point.

[0006]

[Means for Solving the Problems] A first invention comprises a plurality of processing devices and a system control device that receives processing requests from the plurality of processing devices and performs arbitration processing, and the processing device controls the system control device. At the same time as sending a processing request to the device, processing information indicating the contents of the request is written to the address indicated by the value of the write pointer of a request buffer provided in advance, and the processing result of the sent processing request is returned from the system control device. Then, in the failure detection method in the information processing system, in which the contents of the address indicated by the value of the read pointer of the request buffer are read out as the processing information, the processing device performs the write operation as the processing request is sent to the system control device. write pointer calculation means for outputting write pointer calculation information obtained by calculating the pointer value and identification information unique to the processing device prepared in advance according to a predetermined algorithm; Comparing means compares the identification information unique to the processing device with the value produced by the algorithm and the write pointer return information and outputs an error signal if they do not match, and the system control device calculates the write pointer together with the processing request. The present invention further includes a write pointer return means for receiving the information, delaying the write pointer calculation information by a predetermined time, and outputting the delayed write pointer calculation information as the write pointer return information together with the output of the processing result. Features.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 1 consists of a processor 0 (100), a system control device 101, and a processor 1 (102).
0) and processor 1 (102) are configured with the same logic. A case in which a processing request is issued from processor 0 (100) to system control device 101 will be described with reference to FIG. 1. First, when a processing request occurs in the processor 0 (100), a request signal 13 and request information 14 are sent from the main processing unit (not shown) to the system control device 100.
At the same time as the request information 14 is issued, the request information 14 is written into the designated word of the request buffer 1 according to the value of the write pointer information 18 designated by the write pointer 3. At the same time, the value of write pointer 3 is counted up by one. Processor number holding unit 30 is write pointer 3
This is a flip-flop configured with the same bit width as , and a value is stored in advance at reset, so that a different value can be set for each processor. The output signal 31 of this processor number holding unit 30 and the write pointer 3
The write pointer information 18, which is the output of 101. Processor 0 (100
), processing requests are generated one after another, and the same processing as described above is performed continuously.

In the system control device 101, processor 0
(100) and processor 1 (102), respectively. These are the request signals 13, 21
is input to the arbitration unit 5, and requests from each processor are selected according to a predetermined priority order. Here processor 0 (
100), the request signal 13 is turned on and the arbitration unit 5
When the request of the processor 0 (100) is selected by
3, the processor 0 (100) side is selected, and selection request information 25 and selection pointer 26 are output. The request acceptance signal 29 indicating that the processing request has been accepted by the arbitration unit 5 and the selection request information 25 are sent to the control unit (
(not shown) and processes such as memory access are performed.

After the request acceptance signal 29 is turned on, processing is completed in 5 machine cycles within the system control device, and processor 0 (100
), corresponding signals 20 and 27 are sent to processor 1 (102), respectively. During that time, the information of the selection pointer 26 is written to the write pointer buffers 8, 9, 10, 11, 12.
are sequentially propagated one machine cycle at a time and sent to each processor as write pointer return information 28. This is sent out at the same timing as the response signals 20 and 27 because the write pointer buffer is composed of five.

[0010] In processor 0 (100), response signal 20
When the request buffer 1 is received, the contents of the request buffer 1 are read according to the value of the read pointer information 17 specified by the read pointer 2, the request buffer information 15 is sent to the main processing section, and at the same time the contents of the read pointer 2 are incremented by one. Ru. Since the initial values of the contents of the read pointer 2 and the write pointer 3 are set to be the same, the information stored in the request buffer when the request is sent will be read when the response signal 20 is returned. Here, comparison circuit 4
The read pointer information 17 and the contents of the processor number holding section 30 are input to the arithmetic circuit 34, and the arithmetic circuit 34 performs the same arithmetic operation as the arithmetic circuit 32. The output of the arithmetic circuit 34 is input to the comparison circuit 4 and compared with the contents of the write pointer return information 28 at the return timing of the response signal 20. If they do not match, an error signal 16 is returned to the main processing section.

[0011] The result of calculating the contents of the write pointer when it is stored in request buffer 1 in response to a processing request and the result of performing the same calculation on the read pointer when the processing request is returned are as follows. If it is working normally, it should show the same content and the error signal 16
should be “0”.

According to the present invention, when the following failure occurs, the failure can be easily detected because the error signal 16 becomes "1". In other words, if a request is not transmitted to the system control device 101 due to an incorrect update of the write pointer 3 and read pointer 2 or a failure of the request signal 13, an incorrect request processing order or processing device selection in the control unit in the system control device, or an incorrect response. signal 20
It is possible to detect all cases in which there is a discrepancy between the request and the processing result due to various failures related to a series of request processing, such as when a corresponding signal is not returned to processor 0 (100) due to a failure. .

[0013]

[Effects of the Invention] As explained above, the present invention can detect various failures related to a series of request processing from the generation of a processing request to the return of processing results, and has the effect of greatly improving system reliability. be.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

1 Request buffer 2 Output pointer 3 Write pointer 4 Comparison circuit 5 Arbitration section 6 Request information selection circuit 7 Write pointer selection circuit 8, 9, 10, 11, 12 Write pointer buffer 30 Processor number holding section 32, 34 Arithmetic circuit 100 Processor 0 101 System control device 102 Processor 1

Claims (1)

[Claims] 1. Consisting of a plurality of processing devices and a system control device that receives processing requests from the plurality of processing devices and performs arbitration processing, the processing device simultaneously sends processing requests to the system control device. Processing information indicating the contents of the request is written to the address indicating the value of the write pointer of the request buffer that is provided in advance, and when the processing result of the sent processing request is returned from the system control device, the processing information is written in the request buffer as the processing information. In a failure detection method in an information processing system that reads the contents of an address indicated by a value of a read pointer, the processing device reads the value of the write pointer and the previously prepared process upon sending the processing request to the system control device. a write pointer calculation means for outputting write pointer calculation information obtained by calculating device-specific identification information according to a predetermined algorithm; and a write pointer calculation means that receives write pointer return information and calculates the read pointer value and the processing device-specific identification information by the algorithm. The system control device receives the write pointer calculation information together with the processing request and transmits the write pointer calculation information to the write pointer return information. A fault detection method characterized by comprising a write pointer return means for outputting the write pointer calculation information delayed by a predetermined time together with the output of the processing result as the write pointer return information.