JPS6158063A - Data processing device - Google Patents

Abstract

PURPOSE:To prevent interruption of an action of a data processing device by eliminating artificially a divided memory area having a faulty memory element. CONSTITUTION:A memory area of a RAM5 is devided to (n), and in a memory diagnosis when power source of a data processing device is turned on, a quality of a memory is judged by a memory diagnosis program at the divided memory area unit. An address converting circuit 10 is converted from a physical memory address to a logical memory address at the divided memory area unit. By the address converting circuit 10, an area, which can not be used by the memory diagnosis, can be artificially eliminated and the RAM5 can be accessed by the continuous memory address.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention provides a memory that is configured to diagnose a program storage memory when the power of a data processing device is turned on so that only a normal memory area can be effectively used. The present invention relates to a data processing device having a control function.

[Prior art]

FIG. 1 is a block diagram showing the configuration of a conventional data processing device of this type. In FIG. 1, (1) is a processor, (C) is a ROM (read-only memory) that stores a memory diagnostic program and an initial program loader,
(3) is a flexible disk that stores programs and data, (ri) is an external storage connection circuit for connecting the flexible disk (3), and (ri) is an initial program loader connected to the ROM. Run 1”
RAM to which programs and data read from the flexible disk (3) are transferred.
(Write/read memory), (6) is a display that displays characters, figures, etc. (7) is a display connection circuit for connecting display (6), (f) is between a host computer (not shown) A communication control circuit (9) that performs data communication based on a communication protocol determined in advance is a processor (1), a ROM, an external storage connection circuit (RAM Cr), and a display connection circuit (7).
and a communication control circuit (g), respectively.

Next, the operation of the above-described conventional data processing device will be explained. When the data processing device is powered on, the processor (1) first executes a memory diagnostic program stored in the ROM (2). This memory diagnostic program diagnoses the entire address area of RAM (j') and
This is to check whether it is good or bad.

If the memory diagnostic program determines that there is no abnormality in the RAM (r), then the initial program loader stored in the RoM (2) is executed. This initial program loader reads programs and data from the flexible disk (3) and transfers them to the RAM (5). When the transfer of the program and data is completed, the execution control of the processor (1) is transferred to the program transferred to the RAM (g) so as to execute the program transferred to the RAM (j).
By executing the program stored in M (, t), the functions given to the data processing device are realized.

However, if an abnormality is detected in RAM (-t) by executing the memory diagnostic program, the operation of the processor (1) is immediately stopped and the initial program is restarted.
Execution of the loader will be aborted.

FIG. 2 shows a conventional data processing device.

FIG. 2 is a flowchart showing the processing steps of a memory diagnostic program and an initial program loader stored in ROM (2).

If the memory diagnostic program detects an abnormality even in l pits in the memory elements that make up the RAM (!;), the memory diagnostic program
M (j) is judged to be defective and made! In order to stop h, even if all the remaining memory elements are normal,
An initial program loader is not executed, which makes the data processing device unable to implement a given sophisticated function.

Also, the memory address of the defective memory element detected by the memory diagnostic program is skipped and the flexible disk (
,? ) to RAM (y) Even if you use the initial program loader, it is not possible to access RAM (&) at consecutive memory addresses. Address management becomes difficult and impractical.

Conventional data processing devices have the above configuration and operation, so during memory diagnosis when the data processing device is powered on, it is possible to check whether even l bits are abnormal in the 11 storage elements of RAM (j). When detected, the program for realizing the function given to the data processing device is stored in RAM.
Since the operation is stopped without being stored in RAM (5), it is inevitable that the function of the data processing device will deteriorate and the performance will deteriorate, and the remaining normal memory in RAM (5) The drawback was that the device could not be utilized effectively.

[Summary of the Invention] The present invention was made with the purpose of eliminating the drawbacks of the conventional system as described above. A memory diagnosis program that determines the quality of memory in units of divided storage areas, and an address conversion circuit that converts addresses from physical memory addresses to logical memory addresses in units of divided storage areas, is provided. Although the number of divided storage areas (with storage elements) is reduced, the processor (1) can access the RAM (!r) at consecutive memory addresses, making its operation easier, and also has a memory control function. A processing device is provided.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 is a diagram showing a memory address conversion circuit in a data processing apparatus according to an embodiment of the present invention.

In FIG. 3, (io) inputs address signals Ai and Ais of the common bus (q) and converts address conversion signals a/F and a/j according to prespecified pit conversion information.
This is an address conversion circuit that outputs .

Address conversion signals a/rit and a/j are input to the address input sections All' and A15 of RAM (t), and the other address input sections A17-A/j are connected to the common bus (address signal AO of 9). -A/, l are input respectively.Here, the address signal AAt of the common bus (one is mf3B
(top pit), same address signal A (7 beam, SB
(the lowest pit), the address conversion circuit (10
) translates the memory address space of 1, for example, 6 hiro in units of /Ak. The data processing device according to the embodiment of the present invention is the same as that shown in FIG. 1, except that this address conversion circuit (lO) is provided between the common bus (te) and the RAM (j) ■There are no major structural differences between this and the conventional device ().

゛Data signals DO and D/ on the common bus (9) are used as bit conversion information specified in advance for address conversion, and the data signals are converted in synchronization with the I10 write strobe signal αW on the common bus (?). D0 and D/ are set in the address conversion circuit (10).

This bit conversion information is set by the processor (1) shown in FIG. 1 after the memory diagnosis of the RAM (Y) is completed, and the details will be described later.

Fig. 3 is an exemplary diagram in which the memory address space of RAM (g) in Fig. 3 is divided.
The memory area divided into 5Kt units is divided into areas 1. Area co.

Region J and region G are shown.

These areas 1 to 1 correspond to the memory address space whose address is converted by the address conversion circuit (10) in FIG. 3.

FIG. 3 is a diagram showing the relationship between the address input of RAM (j) in FIG. 3 and the division of the address space in FIG. The operation of the data processing device will be explained. Here, a case will be explained taking as an example a case where a defective memory element is detected in the area shown in FIG. FIG. 6 is a diagram showing conversion from a physical address to a logical address. The memory diagnosis executed when the data processing device is powered on is performed by individually diagnosing the area l or area designated by the physical address ~ζ shown in FIG. 6(a) to check whether there is an unusable area. do. As a result of this inspection, if it is found that the area is unusable, the 1j3
The processor (1) shown in FIG. 3 sets appropriate bit conversion information in the address conversion circuit (10) shown in FIG. -Enable area l, territory area, and area hiro to be assigned in order to BFFF (/ hexadecimal). By doing so, the processor (1) can access memory addresses oooo to BFFF (/A base) as a continuous address space.

Figure 7 shows that the area unit shown in Figure 6 has a usage rate of IIC.
FIG. 3 is a diagram showing pit conversion by the address conversion circuit (10) in the case where In this case, H is r/J, r
This indicates that any OJ temperature is good. With the pit conversion shown in FIG. 2, when processor (1) attempts to access area C, area J, and area J! House and area da will be used respectively. After the memory diagnosis is completed, the processor (1) starts the address replacement circuit (10).
) When the Hebit conversion information is set, the Hegerogram and data are transferred from the flexible disk C3) to the RAM (j). However, since the memo 1 address space that can be used in RAM (, t) is 0000 to BFFF (/hex), determine the program and data to be transferred in advance, and transfer it to RoM (2) K memory. All you have to do is program it into the initial program loader. For example, the available memory address space is from 0000 to . 7F
In the case of FF (/hex), a certain predetermined program IP,
The same memory address space is transferred from 0OQO to 7F.
In the case of FF (/A-adic), in addition to the above program I, a different program U may be transferred.

FIG. 3 shows the address conversion circuit (l) shown in FIG.
FIG. 3 is a flowchart showing the processing procedure of the diagnostic block stored in the ROM (co) and the initial program loader when using the ROM (co).

In the flowchart 1 shown in Figure 5, there is a process to store ■ area usage status while the memory diagnostic program is running, but in the case of this column, ■ (,1) is currently being diagnosed. Therefore, it cannot be used as a storage destination, so an appropriate register built into the processor (1) may be used.

Note that the explanation of the above embodiment is based on the memory of RAM (j).
Although it was done by dividing the address space into a wide area, it is not limited to this, but it is also possible to improve the memory address space, RAM (
It is only necessary to divide it by an appropriate value, taking into consideration the hardware configuration of jo), the structure of the program and data stored in RAM (!;), etc. In addition to the memory diagnostic program and initial program loader, the ROM (co) stores diagnostic programs for the external storage connection circuit (S), display connection circuit (S), and communication control circuit (S). (Also good.

〔Effect of the invention〕

As explained above, this invention performs a memory diagnosis for each divided area of the key area divided into n, and pseudo-deletes unused areas, so that the processor can access the memory using consecutive memory addresses. Even if a defective memory element is detected in the memory diagnosis, other possible solutions can be implemented without interrupting the operation of the data processing device By using such a memory element, a data processing device can be easily operated, which is an excellent effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a conventional data processing device, FIG. 2 is a flowchart of a program stored in the ROM in the data processing device of FIG. 1, and FIG. 3 is a device according to an embodiment of the present invention. Figure 5 is a diagram showing the division of the memory address space of ROM (j), and Figure 5 is a diagram showing the address input of RAM (r) and the memory address divided as shown in the above fga diagram. Figure 6 is an address conversion diagram from a physical address to a logical address, and Figure 6 is an address conversion circuit (1
FIG. 5 is a flowchart of a program stored in a ROM in a device according to an embodiment of the present invention. In the figure, (1) φ processor, (2) ROM
, (J)...Flexible disk, (Lee--External storage connection circuit, (s)...N head, (g)...Communication control circuit, (9--Common bus, (10)--Address This is a conversion circuit. In addition, the same reference numerals in the figures indicate the same parts or Buddhist priest parts. Method C〕 1985 2 Re 6th

Claims (1)

[Claims] A RAM that stores programs and data, the memory address space of which is divided into an arbitrary number of areas, a ROM that stores a diagnostic program for the RAM, and a processor that executes the programs stored in the RAM and ROM. and an address conversion circuit is provided between the RAM and the common bus, and when the power is turned on, the divided area of the RAM is determined by the diagnostic program. When it is diagnosed that an unusable portion exists in any area, the address conversion circuit converts the RAM memory excluding the unusable area based on a predetermined signal from the common bus. - A data processing device adapted to assign consecutive memory addresses to an address space.