JPH04275664A - Mutual monitoring method and device between processors - Google Patents

Abstract

PURPOSE:To present the mutual monitoring method and device to exactly monitor the operational states of processors concerning the monitoring method and device mutually between the processors at a system composed of the plural processors. CONSTITUTION:In a program BM-1 to be executed in each cycle t2 at a processor BM, the contents of a common memory D to write a message by a processor A are read out (S28), and it is discriminated (S29) whether a value read out this time is same as a value read out the last time or not. When the read-out data is the same as the last time data, the data of a common memory CM are cleared (S30) and when it is different from the value read out the last time, the data of the common memory CM are incremented (S31). Then, another program BM-2 compares the data of the common memory CM with a rated value in each fixed cycle and when the data is larger than the rated value, the abnormality of the processor A is judged.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for monitoring mutual processors in a computer system comprising a plurality of processors.

0002

[Prior Art] In a computer system consisting of a plurality of processors, each processor usually has a self-diagnosis function, and when it detects an abnormality in itself, it notifies other processors of the occurrence of the abnormality. There is.

With this self-diagnosis function, for example, in a computer system that controls a certain machine, if the controlling processor detects an abnormality in itself, other processors are notified of the occurrence of the abnormality, and the computer system is operating normally. Other processors can safely stop the machine.

[0004] However, for example, in the case of a failure where the processor itself stops operating, the self-diagnosis function also stops working, so there is a problem that other processors cannot know that an abnormality has occurred. there were.

[0005] Conventionally, a plurality of processors mutually monitor their operations, so that even if one processor fails and the self-diagnosis function does not work, other processors can detect an abnormality in that processor. There is.

[0006] Below, at least two processors A and B
A conventional mutual monitoring method will be explained by taking as an example a multiprocessor system consisting of a computer and common memories C and D accessed by these processors.

FIGS. 11 to 15 are flowcharts showing the processing contents of processor A and processor B in the conventional mutual monitoring method. In this processor system,
Programs A-1 and A-2 for mutual monitoring are executed in processor A every cycle t0 and t1, and programs B-1 and B-2 for mutual monitoring are executed in processor B every cycle t2 and t3. be done.

First, the processing on the processor A side will be explained with reference to FIGS. 11 and 12. In the processor A, a program A-1 shown in FIG. 11 is activated every cycle t0. In this program A-1, the common memory C is cleared to "0" as shown in step S1 of FIG.

Furthermore, in the processor A, a program A-2 shown in FIG. 12 is activated every cycle t1. In this program A-2, data in the common memory C is read in step S2, and in the next step S3 it is determined whether the data read this time and the data read last time match.

[0010] When the data do not match, the common memory C
is incremented by "1" by program B-1 on the processor B side, which will be described later. In this case, it is determined in step S4 that processor B is operating normally, and the process is Terminate it.

On the other hand, if the currently read data matches the previously read data in step S3, then in step S5 it is determined that some abnormality has occurred in processor B and the data in common memory C has not been incremented. It is determined that this is the case, and the process is terminated.

Next, processing on the processor B side will be explained with reference to FIGS. 13 and 14. In processor B, program B-1 shown in FIG. 13 is executed every cycle t2. In this program B-1, data in the common memory C is read in step S6 of FIG. 13, and the value is incremented in the next step S7. Furthermore, the incremented data is written to the common memory C in step S8.

Furthermore, in processor B, program B-2 shown in FIG. 14 is executed every cycle t3. In this program B-2, data in the common memory C is read in step S9 of FIG. 14, and it is determined in the next step S10 whether or not the data is less than a specified value.

When the data in the common memory C is less than the specified value, the contents of the common memory C, which are incremented by 1 by the program B-1 on the processor B side mentioned above, are incremented by 1 by the program A-1 on the processor A side. Period t0
This is the case where it is cleared every time.

In this case, it is determined in step S11 that processor A is operating normally, and the process is terminated. On the other hand, if the data in the common memory C is equal to or greater than the specified value in the determination in step S10, the data in the common memory C is incremented by the program B-1 while the program A-1 is not executed and the common memory C is not cleared. This is the case when the value exceeds the specified value.

In this case, it is determined in step S12 that an abnormality has occurred in the processor A, and in the next step S13, the specified value is written in the common memory C, and the process is terminated.

Incidentally, when the starting period t2 of program B-1 and the starting period t3 of program B-2 are equal, it is possible to combine these programs into one and create program B-0 shown in FIG. can.

In this program B-0, step S1
4, the data of the common memory C is read, and step S15
It is determined whether the read data is less than the specified value. If the read data is less than the specified value, step S16
Processor A determines that it is operating normally, increments the data in common memory C by "1" in step S17, writes that data to common memory C in step S18, and then ends the process. do.

On the other hand, if the data in the common memory C is equal to the specified value, it is determined in step S19 that an abnormality has occurred in the processor A, the specified value is set in the next step S20, and the specified value is set in step S18. After writing the specified value into the common memory C, the process ends.

Next, the operation of the processors when processors A and B are normal or when an abnormality occurs in processor A or B will be explained with reference to the operation time charts of FIGS. 16 to 18.

When processors A and B are operating normally, as shown in the operation time chart of FIG. , the contents of the common memory C are cleared every cycle t0 by program A-1.

At this time, in processor A, the period t1
By program A-2 executed every time, the common memory C
Since it can be detected that the value of is changing, it can be determined that processor B is operating normally.

Although not shown in FIG. 16, program B is executed in processor B every cycle t3.
-2, it can be detected that the data in the common memory C is less than the specified value, so it can be determined that the processor A is operating normally.

Next, the operation when an abnormality occurs in processor A will be explained with reference to the operation time chart of FIG. If an error occurs in processor A, processor B
Although the contents of the common memory C are incremented by the side program B-1, the contents of the common memory C are not cleared to "0" by the program A-1.
The value of the common memory C gradually increases as shown in FIG.

As a result, in processor B, the period t3
The program B-2 executed each time detects that the value in the common memory C is greater than or equal to the specified value, and the processor A is determined to be abnormal.

Next, the operation when an abnormality occurs in processor B will be explained with reference to the operation time chart of FIG. When an abnormality occurs in processor B, the value in common memory C is no longer incremented by the program B-1 described above, and the value in common memory C becomes a constant value as shown in FIG.

As a result, program A-1, which is executed by processor A every cycle t1, detects a match between the data read this time and the data read last time from common memory C, and processor B is determined to be abnormal. .

[0028] Even if an abnormality occurs in processor B, when the data in common memory C is read and compared before and after common register C is cleared by processor A, the current data and the previous data do not match. Therefore, processor B may be determined to be normal.

Even in this case, if the comparison of the data in the common memory C in program A-2 is repeated multiple times, if an abnormality occurs in the processor B, the data in the common memory C after being cleared can be Since the content is a constant value of "0", an abnormality in processor B can be reliably detected.

[0030] Note that the startup cycle of each program is t0, t
1 and t2 must satisfy the following relationship. t0 > t2
■t1 >t2
■t1
≠n×t0 (n=1, 2,...) ■■ Condition is a condition for the data in common memory C to increase during normal times, and conditions ■ and ■ are common during normal times. This is a condition for the previous read data of the memory C and the current read data not to match.

[0031]

However, in the conventional mutual monitoring method described above, a problem occurs when a program is started at the timing shown in FIG. 19, for example, when processor A and processor B operate asynchronously. .

As shown in FIG. 19, if processor A clears common memory C to "0" immediately after processor B reads data from common memory C, then program B-1 The incremented data is incremented and the incremented data is written to the common memory C.

As a result, the data in the common memory C is not cleared and continues to increase, and when the data exceeds the specified value, the program B-2 erroneously determines that an abnormality has occurred in the processor A.

An object of the present invention is to provide a method and apparatus for mutual monitoring between processors that can accurately detect the operating states of processors in a system consisting of a plurality of processors.

[0035]

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention. In a system consisting of a plurality of processors and common memories C and D that can be accessed by the plurality of processors, processor A, one of the processors A and B, which monitors each other's operations among the plurality of processors, A message is written to the common memory D every t0. Furthermore, the data in the common memory C is read every cycle t1, and the data read this time and the data read last time are compared. If the data do not match, processor B is determined to be normal; if the data match, processor B Determined as abnormal.

The other processor B reads the message from the common memory D every cycle t2, determines whether there is a message from the processor A, and if a message exists, clears the common memory C and determines that no message exists. In this case, the data in the common memory C is incremented or decremented. Further, the data in the common memory C is compared with a reference value every cycle t3, and if the data is less than the reference value, the processor A is determined to be normal, and if the data is greater than or equal to the reference value, the processor A is determined to be abnormal.

[0037]

[Operation] In the mutual monitoring method of the present invention, depending on whether one processor A writes a predetermined message to the common memory D, the other processor B clears or increments (or decrements) the data in the common memory C. I decided to do so.

Therefore, unlike in the past, the contents of the common memory C are not cleared while the data in the common memory C is being incremented (or decremented) depending on the program start timing. , it is possible to prevent the processor from being erroneously determined to be abnormal even though it is operating normally.

[0039]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram of a processor system according to a first embodiment of the present invention. Processor card A (e.g.
a board on which a processor A is mounted), N processor cards B [hereinafter, any processor on this card will be referred to as a processor BM (M=1, 2...N)],
A common memory card X that is commonly accessed by these processors is connected via a system bus E, respectively.

Processor card A and processor card B
and exchange data with each other via the common memory card X. There are many data storage areas in the common memory card
a common memory D into which messages are written and read out by processor BM; and N common memories CM (M=1 , 2, 3・
...N) etc. are provided.

In this embodiment, in order to detect the presence or absence of abnormality in N processors B, N common memories CM are used.
has been established. Next, processors A and B of the first embodiment
Regarding the mutual monitoring program executed in M, Figure 3~
This will be explained with reference to the flowchart in FIG.

FIG. 3 is a flowchart of a program A-1 executed by processor A every cycle t0. This program A-1 is a program that writes "0" or "1" into the common memory D as a message.

First, in step S21 of FIG. 3, it is determined whether "0" was written as a message in the common memory D last time. If "0" was written in the common memory D last time, the process advances to step S22, and the common memory D is written this time.
Write "1" as a message to .

On the other hand, if "1" was written in the common memory D last time, the process advances to step S23 and "0" is written in the common memory D as a message this time. Here, in program A-1, the reason why "0" and "1" are written alternately as messages to the common memory D is as follows.
This is to enable processor BM to determine whether processor A is operating normally.

Next, FIG. 4 shows that processor A has a period t1.
It is a flowchart of program A-2 executed every time. This program A-2 is a process for detecting an abnormality in the processor BM by comparing the data read this time from the common memory CM with the data read last time.

First, in step S24 of FIG. 4, data in the common memory CM is read. Next, in step S25, the data read out this time in the common memory CM is compared with the data read out last time, and it is determined whether or not they match.

If the data do not match, step S2
At step 6, the processor BM determines that it is operating normally and ends the process. On the other hand, if the data match, the processor BM executes the program BM-1, which will be described later.
is not executed and the value of the common memory CM is not incremented. In this case, it is determined in step S27 that an abnormality has occurred in the processor BM, and the process is terminated.

Next, FIG. 5 shows that the processor BM has a period t2.
It is a flowchart of program BM-1 executed every time. This program BM-1 is stored in the common memory D
Common memory CM depends on whether the value is the same as the previous value or not.
This is the process of clearing or incrementing .

First, in step S28 of FIG. 5, the contents of the common memory D are read. Then, in step S29, the contents of the common memory D read this time are compared with the contents of the common memory D read last time, and it is determined whether or not they match.

[0050] When the contents of the common memory D do not match,
This is a case where the above-mentioned program A-1 is executed by processor A and the value of common memory D is alternately rewritten from "0" to "1" or from "1" to "0" every cycle t0. In this case, the process advances to step S30, where the common memory CM is cleared to "0", and the process ends.

On the other hand, if the values in the common memory D match, it means that the program A-1 has not been executed during the time t0 and the value in the common memory D has not been rewritten. In this case, step S31 Go to "Common Memory CM"
1" increment and end the process.

Next, FIG. 6 shows that the processor BM has a period t3.
2 is a flowchart of program BM-2 that is executed every time. This program BM-2 is stored in the common memory C
This process detects an abnormality in processor A by comparing the data of M with a specified value (reference value).

First, in step S32 of FIG. 6, data in the common memory CM is read. Next, in step S33,
It is determined whether the read data of the common memory CM is less than a specified value.

When the data in the common memory CM is less than the specified value, the processor A rewrites the contents of the common memory D at every period t0, and based on the result, the program BM-1 rewrites the contents of the common memory at every fixed period t2. This is the case when CM is cleared to "0".

In this case, it is determined in step S34 that processor A is operating normally, and the process is terminated. On the other hand, when the data in the common memory CM is greater than the specified value, the data in the common memory CM is
Since the value of has not been rewritten, the program BM −
This is a case where the common memory CM is incremented by 1 and becomes equal to or greater than the specified value.

In this case, it is determined in step S35 that an abnormality has occurred in processor A, and in the next step S36, a specified value is set in the common memory CM to store that an abnormality has occurred in processor A. .

Next, common registers D and CM when the above program is executed by processors A and BM
The operation of each processor will be described with reference to the operation time charts of FIGS. 7 to 9, which show temporal changes in the value of .

First, the operations of the processors A and BM when they are normal will be explained with reference to the operation time chart of FIG. Assume that processor A executes program A-1 at a certain time and rewrites the data value of common memory D from "1" to "0", and then processor BM executes program BM-1. In this case, the value read from the common memory D this time and the value read last time do not match, so the program BM-1
M is cleared to "0".

During the period t0 until the next program A-1 is executed, the value of the common memory D remains "0" and does not change, so the processor BM executes the program BM.
-1 is executed, the value of the common memory CM increases sequentially.

[0060] Then, after the period t0, the program A is started again.
-1 is executed and the data value of the common memory D is rewritten from "0" to "1", the program BM-1 detects a mismatch between the current read value and the previous read value of the common memory D, Common memory CM is “0” again
cleared.

That is, when processor A is operating normally, the value of common memory D is alternately rewritten from "1" to "0" or from "0" to "1", and the program on processor B side is rewritten. Common register D at BM-1
A mismatch between the previous value and the current value is detected, and the common memory C is cleared. As a result, the value of the common memory CM is suppressed to a certain value or less, so that it is determined by the program BM-2 that the processor A is operating normally.

Furthermore, when processor B is operating normally, the value of the common memory CM is incremented by "1" every cycle t2 by the program BM-1, so changes in the value of the common memory CM are reflected in the processor. This is detected by program A-1 on the A side, and it is determined that processor B is operating normally.

Next, the operation when an abnormality occurs in the processor BM will be explained with reference to the operation time chart of FIG. As shown in FIG. 8, when an abnormality occurs in the processor BM, the program BM-1 on the processor BM side
will no longer be executed and the value in common memory CM will no longer be cleared or incremented. Therefore, common memory C
The data value of M does not increase and remains constant.

[0064] Then, the common memory C read out by the program A-2 executed by processor A every period t1
The current read value of M and the previous read value match. This allows processor A to detect that an abnormality has occurred in processor BM.

Next, the operation when an abnormality occurs in processor A will be explained with reference to the operation time chart of FIG. As shown in FIG. 9, when an abnormality occurs in the processor A, the program A-1 on the processor A side is no longer executed, and the values in the common memory D are no longer rewritten. When the value of the common memory D stops changing, the value of the common memory CM becomes "0" in the program BM-1 on the processor B side.
is not cleared, and its value gradually increases.

As a result, the period t3 in the processor BM
The program BM-2, which is executed every time, detects that the value in the common memory CM has exceeded the specified value. This allows processor BM to detect that an abnormality has occurred in processor A.

[0067] Here, we will examine the cause of erroneously determining that a processor is abnormal in the conventional mutual monitoring method. In the conventional mutual monitoring method, immediately after program B-1 of processor B reads data from common memory C,
A problem occurred when program A-1 of processor A cleared the value of common memory C to "0".

That is, in the conventional mutual monitoring method, program A- on the processor A side clears the common memory C, and program B-1 on the processor B side increments the data in the common memory C. Depending on the startup timing, the value of the common memory C may increase.

On the other hand, in the mutual monitoring method of this embodiment, based on whether processor A has rewritten the message (in this case, "0" or "1") in common memory D, processor B's Program BM-1 clears or increments (or decrements) the contents of common memory C.

Therefore, in principle, it is impossible for the value of the common memory C to increase depending on the start timing of the program, and it is possible to completely eliminate judgment errors. In this embodiment, the processor A itself changes the value of the common memory D from "0" to "1" (or from "1" to "0").
), the messages in the common memory can be rewritten independently from the program on the processor B side.

Next, a second embodiment of the present invention will be described. This embodiment basically has the same system configuration as the first embodiment shown in FIG. It's the same.

The features of the second embodiment will be explained below. In this embodiment, the program A-1 on the processor A side writes numerical data Y to the common memory D every cycle t0.

Then, if the content of the common memory D is numerical data Y, the program BM on the processor BM side
-1 is common memory D and common memory C every period t3.
M is cleared to "0", and if the content of the common memory D is not numerical data Y, the value of the common memory CM is incremented (or decremented) by "1".

[0074] Furthermore, program A-2 and program BM
-2 is the same as the second embodiment. According to the program described above, if, for example, an abnormality occurs in processor A and numerical data Y is no longer written to common memory D, program BM-1 on processor B side causes common memory CM to be written.
When the value of increases and reaches the specified value, it is determined that processor A is abnormal.

Next, a third embodiment of the present invention will be described. FIG. 10 is a system configuration diagram of a processor system according to the third embodiment. In this embodiment, the processor A mentioned above is N
This is an example where there is one processor B.

In FIG. 10, a processor card B equipped with a processor B and N processors AM (M
= 1, 2, ...N) and the common memory card X are connected to a common bus E.
It is connected to the.

The common memory card X contains one common memory C and messages from the processor AM (for example,
N common memories DM are provided in which numerical values ``1'' or ``0'' are written.

In addition, in the processor card B, there are N-1 memories CM that can be accessed by the processor B (in this embodiment, the N-1 memories that can be accessed by the processor B in the processor card B are the memory CM). ) is provided.

The program AM-1 executed on the processor AM side is started every cycle t0, and is a process for alternately writing "0" and "1" as messages in the common memory DM.

Furthermore, the program AM-2 has a period t1
It is started every time, reads the data of common memory C, compares the data read this time with the data read last time,
If they match, processor B is determined to be abnormal; if they do not match, processor B is determined to be normal.

Program B executed on processor B side
-1 is activated every cycle t2, reads the contents of the common memory DM, compares the value read this time with the value read last time, and if they match (if there is no message from the processor AM), the memory CM Increment (or decrement) the data in (including common memory C, the same applies hereinafter), and if there is a mismatch (processor AM
), memory C is set to ``0''
”.

Furthermore, the program B-2 is activated every cycle t3, compares the data value of the memory CM with a specified value, and if the data value is smaller than the specified value, the processor AM
is determined to be normal, and if the data value is greater than or equal to a specified value, processor AM is determined to be abnormal.

[0083] With these programs, the above-mentioned first
Similarly to the second embodiment, processor AM and processor B can detect abnormalities in each other's processors.

In this embodiment, since there is one processor B, the common memory C that needs to be read from N processors AM in order to detect an abnormality in processor B is one.
It is enough. Therefore, the common memory C is set to one, and N
- N-1 memories C necessary for detecting an abnormality in one processor AM (common memory C is used for the remaining one processor AM) can be accessed only by processor B. It is provided in card B.

[0085] As a result, the memory for detecting abnormalities in N processors A (corresponding to the common memory CM in the first embodiment) does not necessarily need to be a common memory, and the memory area in the processor card B can be used as a common memory. can be used, making memory configuration more flexible.

Next, a fourth embodiment of the present invention will be described. The system configuration of this embodiment is the same as that of the third embodiment shown in FIG.
The basic parts of each program executed by ,B are the same as the program of the third embodiment. The features of the fourth embodiment will be described below.

In this embodiment, the processor AM writes numerical data Y as a message to the common memory DM at regular intervals. Then, when the numerical data Y is written in the common memory DM, the processor B clears the common memory DM and the memory CM (including the common memory C, the same applies hereinafter) to "0" at regular intervals,
When numerical data Y is not written, memory C
I am trying to increment M.

The programs executed by processors AM and B will be explained below. The program AM-1 executed by the processor AM is activated every cycle t0 and writes numerical data Y into the common memory DM.

Program B- executed on processor B
1 is activated every cycle t2, reads the contents of the common memory DM, and if the read data is numerical data Y, clears the memory CM and the common memory DM to "0", and confirms that the read data is numerical data Y. If not, the process increments the memory CM by "1".

Furthermore, program AM-2 and program B-2 are the same as the programs of the third embodiment. With these programs, when the processor AM is operating normally and the numerical data Y is written in the common memory DM, the data in the memory CM is cleared to "0" at regular intervals, and the data in the memory CM is cleared to "0". is always less than the specified value. On the other hand, if an abnormality occurs in the processor AM, the data in the memory CM will exceed the specified value, so
It is possible to determine without error whether the N processors AM are normal or not.

Furthermore, it is possible to determine whether processor B is operating normally or not, depending on whether the value in memory CM has changed. As described above, in the above embodiment, in a processor system in which a plurality of processors operate asynchronously, at least two types of common memory areas are prepared (for example, common memory C and common memory D), and one processor A has a For example, "0" or "1" is alternately written as a message in the common memory D every cycle. Then, when the message in common memory D is being rewritten by processor A, another processor B clears the value in another common memory C to "0", and when the message has not been rewritten, common memory C
The data is incremented (or decremented).

[0092] As a result, when processor A is operating normally, the value of common memory C does not increase, and only when an abnormality occurs in processor A, the value of common memory C exceeds the specified value. . Therefore, by comparing the value in the common memory C with the specified value, it is possible to accurately detect an abnormality in the processor A.

Furthermore, whether or not processor B is operating normally is detected based on whether or not the value in common memory C has changed. Moreover, in the mutual monitoring method described above, one processor B clears the common memory C to "0" or increments (or decrements) the common memory C based on a message written to the common memory D by the other processor A. ing.

Therefore, unlike the conventional mutual monitoring method, the problem of the common memory C not being cleared and its value increasing depending on the program startup timing does not occur, and errors in detecting processor abnormalities can be eliminated. Can be done.

[0095] In the above embodiment, one processor A
(or B) and a plurality of processors BM (or AM), but there may be one each of processors A and B, or there may be a plurality of processors A and B.

[0096] Furthermore, the message to be written to the common memory D is not limited to "0", "1", or numerical data as described in the embodiment, but may be any message, and it is possible for one processor to write some information. Good.

[0097]

According to the present invention, in a system consisting of a plurality of processors, it is possible to eliminate errors in detecting the operating states of the processors that occur due to the start timing of programs of individual processors.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention.

FIG. 2 is a system configuration diagram of the first embodiment of the present invention.

FIG. 3 is a flowchart of a program A-1 executed by processor A of the embodiment.

FIG. 4 is a flowchart of a program A-2 executed by processor A of the embodiment.

FIG. 5 is a flowchart of a program BM-1 executed by the processor BM of the embodiment.

FIG. 6 is a flowchart of a program B-2 executed by the processor BM of the embodiment.

[Fig. 7] Processors A and BM in the mutual monitoring method of the embodiment.
is an operation time chart when is normal.

FIG. 8 is an operation time chart when an abnormality occurs in the processor BM in the mutual monitoring method of the embodiment.

FIG. 9 is an operation time chart when an abnormality occurs in processor A in the mutual monitoring method of the embodiment.

FIG. 10 is a system configuration diagram of a third embodiment.

FIG. 11 is a processing flowchart of processor A in a conventional mutual monitoring method.

FIG. 12 is a processing flowchart of processor A in a conventional mutual monitoring method.

FIG. 13 is a processing flowchart of processor B in a conventional mutual monitoring method.

FIG. 14 is a processing flowchart of processor B in a conventional mutual monitoring method.

FIG. 15 is a processing flowchart of processor B when t3 = t2.

FIG. 16 is an operation time chart when processors A and B are normal in a conventional mutual monitoring method.

FIG. 17 is an operation time chart when an abnormality occurs in processor A using the conventional mutual monitoring method.

FIG. 18 is an operation time chart when an abnormality occurs in processor B using the conventional mutual monitoring method.

FIG. 19 is an explanatory diagram of problems in the conventional mutual monitoring method.

[Explanation of symbols]

Claims (4)

[Claims] 1. A system comprising a plurality of processors and common memories C and D that can be accessed by the plurality of processors, wherein one of the processors A and B monitors each other's operations among the plurality of processors. Processor A of
Write a message to the common memory D every cycle t0, read the data from the common memory C every cycle t1, compare the data read this time with the data read last time, and if the data do not match, processor B is normal. If the data match, processor B is determined to be abnormal, and the other processor B reads the contents of the common memory D every cycle t2, determines whether there is a message from processor A, and determines that the message exists. If the message does not exist, the common memory C is cleared, and if there is no message, the data in the common memory C is incremented or decremented, and the data in the common memory C is compared with a reference value every cycle t3, A mutual monitoring method between processors, characterized in that processor A is determined to be normal if it is less than a reference value, and processor A is determined to be abnormal if it is greater than or equal to the reference value. 2. At least one processor A, N processors BM (M=1, 2...N), a common memory D and N common memories CM that are accessible from the processors A and BM. In this system, a processor A writes a message to the common memory D every cycle t0, reads data from the common memory CM every cycle t1, and compares the data read this time with the data read last time. , if the data do not match, the processor BM corresponding to the common memory CM is determined to be normal; if the data match, the processor BM is determined to be abnormal, and the processor BM updates the contents of the common memory D every cycle t2. , and determines the presence or absence of a message from processor A. If a message exists, clears the contents of the common memory CM, and if no message exists, increments or decrements the contents of the common memory CM. , the data in the common memory CM is compared with a reference value every cycle t3, and if it is less than the reference value, the processor A is determined to be normal, and if it is equal to or greater than the reference value, the processor A is determined to be abnormal. A mutual monitoring method between processors. Claim 3: N processors AM (M=1, 2...
・N) and at least one processor B, and N common memories DM accessible from the processors AM and B.
A system consisting of at least one common memory C and a plurality of memories Ci that can be accessed from the processor B, wherein the processor AM writes a message to the common memory DM every period t0, and the processor AM writes a message to the common memory DM every period t0.
Each time the data is read from the common memory C, the data read this time and the data read last time are compared. If the data do not match, processor B is determined to be normal, and if the data match, processor B is determined to be abnormal. Then, processor B reads the contents of the common memory DM every cycle t2, determines whether there is a message from the processor AM, and if there is a message, the processor B reads the contents of the common memory DM.
The contents of the common memory C or memory Ci corresponding to the message are cleared, and if there is no message, the contents of the common memory C or memory Ci are incremented or decremented, and the contents of the common memory C and memory Ci are cleared every period t3. data of the memory is compared with a reference value, and if the data is less than the reference value, the processor AM corresponding to the memory is determined to be normal, and if it is greater than or equal to the reference value, the processor AM is determined to be abnormal. Mutual monitoring methods. 4. A system comprising a plurality of processors and common memories C and D that can be accessed by the plurality of processors, wherein one of the processors A and B monitors each other's operations among the plurality of processors. Processor A of
Write a message to the common memory D every cycle t0, read the data from the common memory C every cycle t1, compare the data read this time with the data read last time, and if the data do not match, processor B is normal. If the data match, processor B is determined to be abnormal, and the other processor B reads the contents of the common memory D every cycle t2, determines whether there is a message from processor A, and determines that the message exists. If the message does not exist, the common memory C is cleared, and if there is no message, the data in the common memory C is incremented or decremented, and the data in the common memory C is compared with a reference value every cycle t3, A mutual monitoring device between processors, characterized in that processor A is determined to be normal if it is less than a reference value, and processor A is determined to be abnormal if it is greater than or equal to the reference value.