JPS59177799A - Checking system of read-only memory - Google Patents

Abstract

PURPOSE:To enable a test such as bit absence check etc. by making a specified address area of a read-only memory hold normality check information relating to the content of memory of all address areas excepting the specified address area or normality check information relating to the content of memory of all address areas including the specified address area. CONSTITUTION:When the operation of an ROM bit drop test program is started, the values of ROM reading address register 11 and a register for the test are initialized and read out data successively. The read data are set to an ROM reading data register 13 and added with the content of the register 14 for test, and the content of register 14 for test are updated. The sum of contents of areas from address 0 to n-1 and the content of read address n and the content of the register 14 for test are compared in a comparing circuit 17 under the control of an address judging circuit 16. If the two coincide, test is completed without error, and if they do not coincide, ROM bit absence error is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a checking method for detecting a dropped hint in a memory dedicated to one-shot output.

(b) Prior art and problems Conventionally, read-only memory (
In order to detect the ROM), a separate check RO is installed.
A method was adopted in which a parity ROM (ROM for parity) was created and checked, or a method was used in which a parity value calculated in advance before writing to the ROM was compared with a value calculated by actually reading ROM information.

FIG. 1 is a diagram showing an example in which a check ROM 2 is provided in addition to the ROMI under test. According to this method, a check ROM 2 and a parity check circuit (not shown) are required, and in a device that does not have a parity check circuit, The disadvantage is that it cannot be tested.

In addition, the method of comparing with the pre-calculated value mentioned above is based on the data contained in the ROM information, and the check high 1 such as sum check and hash total is stored in the diagnostic software and then stored in the ROM. The information read from the ROM when checking for missing bits (
It is compared with This method has the disadvantage that the diagnostic software must be changed every time the ROM information is changed.

(C) Purpose of the Invention The present invention enables a test device that does not have a parity check circuit for ROM to perform tests such as out-of-focus checks without requiring changes to diagnostic software even when ROM information is changed. The purpose is to

(d) Structure of the Invention In order to achieve the above object, the check method of the memory dedicated for continuous use according to the present invention performs a validity check on the storage contents of all address areas other than the specific address area in a specific address area of the memory only for continuous use. When testing the read-only memory by retaining information or check information including the specific address area, predetermined arithmetic operations or Executing a predetermined arithmetic operation on the storage contents of all address areas including the specific address area, and comparing the result information of the above arithmetic operation with the validity check information held in the above specific address area, or by the above arithmetic operation. The present invention is characterized in that the above-mentioned reprint-only memory is tested by comparing the result information with fixed data information prepared separately.

(E) Embodiment of the Invention FIG. 2 is a diagram for explaining the configuration of the ROM under test in the embodiment. In FIG. 1, normal data and programs are stored in the area of addresses 0-n-1. The remaining address n holds check information regarding the information stored in the area of addresses 0-n-1.

FIG. 3 is a block diagram of a test device for testing the ROM shown in FIG.
OM read address register, 12 is an increment circuit, 13 is an R, OM read 7 data register, 14 is a test register, 15 is a diagram showing the operation flow of the embodiment shown in FIG. 4 and FIG.

The operation of the embodiment will be described below with reference to the operation flow shown in FIG.

First, when the operation of the ROM bit drop test program is started, the values of the R'oM read address register 11 and the test register 14 are initialized. Next, R
Data is read out sequentially from OMI (I).The read data is set in the ROM iTh output data register 13, and then added to the contents of the test register 14.This addition result information is sequentially read out to the test register 14.
is set to

The contents of the test register 14 are updated.

In this way, the addresses 0 to n-1 shown in FIG.
After the sum of the contents of the area is set in the test register 14, when reading the last address n, the contents of the area of three successive addresses n and the contents of the area of the negative register 14 are determined by the control of the address judgment circuit 16. A comparison with the contents is performed in the comparison circuit 17. If both match,
The test ends without any errors, and if there is a discrepancy between the two.

A ROM bit drop error is detected.

FIG. 5 is a diagram showing the operation flow of another embodiment according to the present invention. The embodiment shown in FIG. 5 is an example of the address n shown in FIG.
The area is set as a gated area, and the calculation result of the contents of all address areas including the gated area is the same fixed information (fixed data value held in the diagnostic software).
This is a method in which the contents of the adjustment area are set.

Since the operation of the system shown in FIG. 5 is easily understood, detailed explanation will be omitted.

(f) Effects of the Invention According to the present invention, the configuration is simple, and the diagnostic software 1-1 can be easily configured using a dedicated memory (RO) without complicating the software.
M) can be tested.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional example of creating a check ROM,
FIG. 2 is a diagram explaining the configuration of the ROM under test in the embodiment, FIG. 3 is a block diagram of the test device of the embodiment, FIG. 4 is a diagram showing the operation flow of the embodiment shown in FIG. 3, and FIG. FIG. 7 is a diagram showing an operation flow of another embodiment according to the present invention. In Figure 3, 10 is the ROM under test, 11 is the ROM
13 is a read address register, 13 is a ROM Frjε output data register, and 14 is a test register. 15 is an adder circuit, and 17 is a comparison circuit. Kaya 1 Utsume? 3 figs ¥4 figs

Claims (1)

[Scope of Claims] Validity check information regarding the storage contents of all address areas other than the particular atlus fiMb) 2, or validity check information regarding the storage contents of all address areas including the particular address area, is stored in a specific address area of the successive-only memory. Preserve sensitive Che-tsuk information. When testing the above-mentioned read-only memory, predetermined arithmetic operations are performed on the storage contents of all address areas other than the above-mentioned specific address area of the above-mentioned read-only memory, or storage of all address areas including the above-mentioned specific address area. Execute a predetermined arithmetic operation on the content and compare the result information from the arithmetic operation with the validity check information held in the specific address area, or fixed data information prepared separately from the result information from the arithmetic operation. A method for checking a read-only memory, characterized in that the above-mentioned continuous read-only memory is tested by comparing the read-only memory.