JPS61208134A - Error detection system in information processor - Google Patents

Abstract

PURPOSE:To find a trouble which causes a disguise of data by comparing identification information accompanying to the frequency of request acceptance stored in a data buffer with identification information accompanying to the frequency of request execution read out of the data buffer. CONSTITUTION:When a request is sent out of a request origin data processor 1, data on a data line 9 and the contents of an output line 8 are written in the data buffer 2 and the contents of the 3rd counter 3 are updated. The contents of the data buffer 2 are read out in request execution and the contents of the 2nd counter 4 are updated with a request execution indication signal from a request accepting circuit 15. The contents of the 1st counter 3 read out to a data line 11 and the contents of the 2nd counter 5 obtained on an output line 10 are compared by a comparing circuit 5 with each other. When they are not coincident with each other, that is reported to an error detecting circuit 6, which sends out an error information signal through an output line 13.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to an information processing apparatus including a plurality of data processing apparatuses. This invention relates to an error detection method for detecting erroneous errors.

[Prior art]

Conventionally, this type of information processing device includes a data buffer that stores data from a requesting data processing device when data is transferred between each data processing device, and a first counter that provides a write address of the data buffer. , and a second counter giving a read address of the data buffer.

Then, the data accompanying the request from the requesting data processing device is written into the data buffer according to the write address given by the first counter.

The first counter is then updated. after that.

by the read address given by the second counter.

Data is read from the data buffer and the second counter is updated.

In such a configuration, for example, if the first counter fails and the write address becomes fixedly "0", the data accompanying subsequent requests from the requesting data processing device will be sent to the same address (address 0). ) will be written to. In this state, the data read from the data buffer by the subsequent read address given by the second counter will no longer match the data accompanying the request from the requesting data processing device. When such a failure occurs, the failure detection method used in the prior art, which performs a integrity check on data with integrity pits added, cannot detect the above failure. Needless to say, this method has the drawback of lowering the reliability of the information processing device by causing data corruption.

[Purpose of the invention]

An object of the present invention is to write identification information at the same time when writing data associated with a request to a data buffer, and to ensure that when data for the request is read from the data buffer, the read information corresponds to the request to be processed. An object of the present invention is to provide a highly reliable error detection method in an information processing device that can detect garbled data by determining whether the information is identification information.

[Structure of the invention]

The error detection method according to the present invention includes, in an information processing apparatus including a plurality of data processing apparatuses, a first counter that counts the number of requests received from a requesting data processing apparatus during data transfer between each data processing apparatus; a data buffer that stores data associated with the request and the contents of the first counter in response to a request from the requesting data processing device; a second counter that counts the number of times the request is executed for the request; and a second counter that counts the number of times the request is executed; a comparison circuit that compares the contents of a first counter read from the data buffer with the contents of a second counter; and when the comparison circuit detects a mismatch between the two, the mismatch signal and an error detection circuit that receives the error and sends out an error report signal.

[Embodiments of the invention]

Next, an embodiment of the error detection method according to the present invention will be described in detail with reference to two drawings.

In FIG. 1 showing an embodiment of the present invention, this information processing device includes a request source data processing device 1, a first counter 3 for counting the number of requests received from the request source data processing device 1, and a request source data processing device 1. a data buffer 2 that stores data sent in response to a request from the processing device 1 and the contents of the first counter 3;

A second counter 4 that counts the number of request executions for the above request, and a comparison circuit 5 that compares the contents of the first counter 3 and the second counter 4 read from the data buffer 2 at the time of accepting the request. and,
The comparator circuit 5 is comprised of an error detection circuit 6 which generates an error report signal when a mismatch is detected between both inputs of the comparison circuit 5.

During normal operation, when a request source data processing device 1 sends a request to the request line 7.

The data on data line 9 and the contents of output line 8 of first counter 3 are written to data buffer 2 and subsequently
counter 3 is updated. and.

When a request is executed, the data of the requesting data processing device stored in the data buffer 2 and the contents of the first counter 3 are read out. On the other hand, the second counter 4 is updated by a request execution instruction signal from the request reception circuit 15. At this time, in addition to the data read from the data buffer 2 to the data line 14, the contents of the first counter 3 read to the data line 11 and the contents of the second counter 4 obtained to the output line 10 are are compared by the comparison circuit 5. When the contents of the two human forces do not match, the Scherer detection circuit 6 is notified by a mismatch signal appearing on the output line 12. When error detection circuit 6 receives the mismatch signal, it sends out an error report signal via output line 13 to report the detection of an error.

FIG. 2 is a block diagram showing the configuration of the embodiment shown in FIG. 1 in more detail. Referring to FIG. 2, the operation will be described. Registers 1a and 1b respectively store the reference data a and the associated data k from the requesting data processing device. The first counter 3 is updated every time it receives the output from the register 1a. The data buffer 2 stores the output t of the register 1b and the most significant pit output cf of the first counter 3 with the output of the register 1a as a write enable and the output d of the first counter 3 as a write address. The second counter 4 is
It is updated by +1 every time a request execution instruction signal is received from the request receiving circuit 16 that has received the request execution number from the requesting data processing device. Register λ7 stores data m read from data buffer 2 using output e of second counter 4 as a read address. Comparison circuit 5
compares the most significant bit output f of the second counter 3 read from the data buffer 2 and the most significant bit output g of the second counter 4, and when they do not match, a mismatch signal i is sent.
Send out. When the error detection circuit 6 receives the mismatch signal i'z, it sends out an error report signal j.

During normal operation, the first counter 3.

The data accompanying Riffnis) a from the requesting data processing device and the most significant bit of the counter itself are stored in data buffer 2.
At the same time, it is updated by +1 to indicate the write address of the data associated with the next request. When the request reception circuit 16 accepts Sirikunis)b, the second
Data m and the most significant bit f of the first counter 3 are read out from the data buffer 2 by the counter 4 .

Thereafter, the second counter 4 is updated by the request execution instruction signal, and data at the next address in the data buffer 2 is read. The most significant bit output C (value before update) of the first counter 3 read from the data buffer 2 and the most significant bit output g of the second counter 4 are 9
Usually matched.

However, if there is some kind of failure 2, for example, the first counter 3 malfunctions and the counter is no longer updated, the write address to the data buffer 2 is fixed at 1, for example, 0 address. For that reason, hereafter Rifnis)
Data accompanying a is always written to the same address (address 0). To explain in more detail, the value of the most significant bit output C of the first counter 3 is always O, and the data t associated with the request a is only written to the O address of the data buffer 2. However, the second
Since the counter 4 is normally updated in response to the request execution instruction signal, the most significant bit of the first counter 3 read from the most significant bit output g of the second counter 4 and the data output 2 The bit output f does not match when the read address e of the data buffer 2 becomes O for the second time.

In other words, the most significant bit output f read from address 0
(always “O”) and the value of the most significant bit output g (“1”5) when the read address becomes O for the second time are compared in the comparator circuit 5, and a mismatch between the two is detected. be done.

This mismatch signal i is detected by the error detection circuit 6 and sent out as an error report signal n.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, there are two types of information: identification information associated with the number of request receptions stored in the data buffer together with data accompanying the request, and identification information associated with the number of request executions read from the data buffer. By comparing the data, it is possible to discover failures that cause data corruption that could not be detected using conventional parity checking methods, and this has a significant effect on improving reliability.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment according to the present invention;
FIG. 2 is a block diagram showing the configuration of the embodiment shown in FIG. 1 in more detail. In the figure, 1 is the requesting data processing device #11Ll1b
is a register, 2 is a data buffer, 3 is a first counter, 4 is a second counter, and 5 is a comparison circuit. 6 is an error detection circuit, and 16 is a request reception circuit. 17 is a register.

Claims (1)

[Claims] 1. In an information processing device including a plurality of data processing devices, a first method for counting the number of requests received from a requesting data processing device when data is transferred between each data processing device.
a data buffer that stores data accompanying the request and the contents of the first counter in response to a request from the requesting data processing device; and a second counter that counts the number of times the request is executed in response to the request. , a comparison circuit that compares the contents of a first counter and the contents of a second counter read from the data buffer at the time of executing the request; and when the comparison circuit detects a mismatch between the two; An error detection method comprising: an error detection circuit that receives a mismatch signal and sends out an error report signal.