JPS60200352A - Memory diagnosis system - Google Patents

Abstract

PURPOSE:To simplify the hardware of a CPU by directly accessing the address of the error data through a service processor to obtain the collection data. CONSTITUTION:The data read out of a buffer memory BS is held by an address register CAR of a controller MCU via a service processor SVP after a parity is checked together with detection of an error. The controller MCU accesses to a main memory MSU with the address of the register CAR and reads out the correct answer data to set it to a collection data register CDR. At this time point, the processor SVP scans out the information on an error data register ERDR, an error way number register ERWNR and the register CDR respectively. The 1-byte data of the register ERDR is compared with that of the register CDR to obtain the position of a discordant bit. This bit position is combined with the way information to point out a faulty memory element of the memory BS.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a memory device diagnostic method for pointing out a failure in a memory element of a buffer memory of a computer system.

Conventional technology and problems In computer systems, the central processing unit (CPU) stores data fetched from the main memory in a buffer memory.
If the required data is in the buffer memory at the time of subsequent fetching, it is fetched from there, but it is necessary to always check whether the buffer memory is normal or not and whether there is a failure in the memory element. be. Conventionally, this type of memory diagnostic method reads the correct data from the main memory and corrects the error, since the buffer memory does not have an ECC mechanism and even if a parity error is detected in the read data, the error can only be pointed out in byte units. By comparing data at the bit level, faulty memory elements are identified. The procedure is shown below.

(2) Hold error data, its address, and associative memory number in the CPU.

■The instruction control unit retries the same data as the erroneous read data to the main memory (Retr
y; retry) sequence. At this time, reading performed during retry is called retry fetch.

■Check the match between the address of the error data and the retry fetch address.

■When a match is detected, the retry-fetched correct data is held in the register, and the scan-out function scans out the error data, correct data, and associative memory number.

(2) Compare error data and correct data at the bit level, find out which memory element in the buffer memory has a failure from the mismatched bits and associative memory number, and point out (display) this.

However, this method requires complex hardware such as an address match detection circuit and a correct data information analysis circuit in the CPU, and the probability that correct data corresponding to error data is fetched in the retry sequence is 100.
%, the problem is that memory device diagnostics are uncertain.

OBJECTS OF THE INVENTION The present invention aims to eliminate the above-mentioned drawbacks of the prior art, simplify the configuration of a central processing unit, and ensure memory device diagnosis with greater efficiency.

Composition of the Invention The present invention, when it is detected that there is an error in the data read from the buffer memory, reads the correct data corresponding to the erroneous data from the main memory containing the correct data, and processes these data at the bit level. In a memory device diagnostic method that identifies a faulty memory element in a buffer memory by comparison, when it is detected that there is an error in the read data, the error data, the address of the error data, and the content addressable memory number of the buffer memory are ERDR and ERAR are held in the central processing unit and are used to notify the service processor of the address of the error data, the error data, and the content addressable memory number using the scan alarm 1-.

(The timing for scanning out the ERWNR is not determined), the service processor directly accesses the main memory based on the address, reads out the correct data, compares it with the error data at the bit level, and points out the faulty memory element. However, this will now be explained with reference to examples.

Embodiment of the Invention FIG. 1 shows an embodiment of the invention, in which MSU is a main storage device;
BS is a buffer memory, and SvP is a service processor. In this example, the buffer memory BS is a so-called set associative type buffer memory consisting of 16 ways called ways with the same capacity and format, as shown in FIG. The way groups of WayO=WayF are accessed for reading at the same time, and which line is accessed is selected by the address signal ADD. Also, if there is no corresponding data in any way, LRU (Least Re
A predetermined way is selected by logic or the like, and the data fetched from the main memory is registered in the line of the way. The MCU is a control unit for the MSU and is a register CD of correct (collect) data.
R and a register CAR for the address of the data.

The SVP has a function of scanning out and capturing data in the CPU and MCU, and the SOC is its scanout collection circuit. The CPU includes the above buffer memory, align/select circuit AL&S, buffer data/
Check register BDCR, error data register ER
DR, error address register ERAR1 error way number register ERWNR.

Effective address register EAR, tag circuit TAG.

A blank frame including a match circuit MCH or the like indicates an intermediate register or launch.

To explain the diagnosis procedure, data read from the buffer memory BS is sent to the instruction control section calculation section via the align/select circuit AL&S, and is held in the register BDCH. Data in register BDCR In this example, the parity check circuit PC checks the parity of 8 bytes in byte units, and if an error is detected, the data (
1 byte) is held in register ERRD. At this time,
The address of the a-data is taken from register EAR to register ERAR, and the way information in the buffer memory (the way numbers 〇-F mentioned above) is transferred to tag times r/3.
It is determined by TAG and match circuit MCI and held in register ERWNR.

The address of the error data in the register ERAR is then scanned out and held in the register CAR of the control unit MCU via the service processor SvP. The control unit MCU accesses the main storage unit MSU using the address stored in this register CAR, reads out the correct data (1 byte) at that address, and holds it in the register CDR. Here, the service processor SVP registers ER
DR.

By scanning out the information in ERWNR and CDR, comparing 1 byte data in register ERDR and 1 byte data in register CDR at the bit level to locate the mismatched bit, and combining this with way information, the buffer memory BS is Point out the faulty memory element.

That is, I10 in this example sends a signal to the printer to print out the address of the failed memory element.

In this method, the SVP directly accesses the MSU and retrieves the collect data based on the address of the error data, so there is no need to detect a match in the address as in the case of retry fetch performed by the instruction control unit of the CPU. , the CPU hardware can be simplified. That is, there is no need to provide an address match circuit, a correct data information analysis circuit, etc. in the CPU. Also CP
In the retry fetch performed by the instruction control unit of U, ■ retry may not be possible depending on the type and timing of the instruction; ■ If the instruction that was previously fetched is not executed due to a branch instruction, etc., processing for machine check is performed. Because it is not executed, retry is not performed, etc.
Although there is no guarantee that correct data will be obtained with 100% certainty, S
If the main memory is directly accessed by vP, correct data can be obtained with certainty, and therefore a faulty memory element can be reliably pointed out.

Effects of the Invention As described above, according to the present invention, the hardware of the CPU, especially its memory device diagnostic circuit section, can be reduced, and since the SVP directly accesses the main memory to retrieve collect data, it is possible to compare correct and incorrect data, Error bits can be detected reliably, and the reliability of the computer can be further improved by enriching the machine check circuit.

[Brief explanation of the drawing]

1 and 2 are block diagrams showing embodiments of the present invention. In the drawing, BS is a buffer memory, MSU is a main storage device,
ERDR is an error data register, ERAR is an address register for error data, ERWNR is a content addressable memory number register, CDR is a register for correct data, and CAR is an address register for correct data. Applicant Fujitsu Co., Ltd. Representative Patent Attorney Minoru Aoyagi

Claims (1)

[Claims] When it is detected that there is an error in the data read from the buffer memory, correct data corresponding to the incorrect data is read from the main memory containing the correct data, and these data are compared at the bit level to detect a buffer memory failure. In a memory device diagnostic method that identifies a memory element, when an error is detected in read data, the error data, the address of the error data, and the associative memory number of the buffer memory are retained in the central processing unit. , the address of the error data, the error data, and the content addressable memory number are notified to the service processor by scanning out, and the service processor directly accesses the main memory using the address, reads the correct data, and compares it with the error data at the bit level. A memory device diagnostic method characterized by pointing out a faulty memory element.