JPH05241974A - Memory device - Google Patents

Abstract

PURPOSE:To shorten access time and cycle time in write by attaching a check bit by an error, detecting means without generating the check bit when a write request is accepted. CONSTITUTION:At an error detecting part 13, a correctable error can be corrected by data and the check bit 1 when no write display is performed on stain display information, and it is transferred to a controller 3 via an access control part 14 and a processor bus 4 as readout data. When the write display is performed, the content of a data memory array 111 is read out as it is without performing ordinary error detection, and is transferred to the access control part 14, the processor bus 4, and the controller 3 as the data. An error monitoring part 15 reads out stain display and a data check bit periodically from each address of a data storage part 11, and delivers them to the error detecting part 13. At the error detecting part 13, the data is delivered as it is when the write display is performed, and the data after correction when no such display is performed to the monitoring part 15 similarly as in the readout of the data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device, and more particularly to a storage device for an information processing device.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing an example of a conventional storage device.

In the conventional storage device shown in FIG. 2, when a write request is issued from the control device 3 through the processor bus 4, the access control unit 24 in the storage device 2 accepts the write request.
The write data is given a corresponding error correction code in the check bit generation unit 22 and written in the data memory array 213 and the check bit memory array 212 in the data storage unit 21. The error monitoring unit 25 periodically reads the data of all addresses in the data storage unit 21 through the error detection unit 23, corrects the correctable error, and again adds the correct error correction code by the check bit generation unit 22 to obtain the data. The operation of writing in the storage unit 21 is repeated.

When the write request is a part of the address unit of the data storage unit 21, the access control unit 24 transfers the data of the corresponding address to the data memory array 213 and the check bit memory array 212 in the data storage unit 21.
From the check bit generator 2 according to the normal writing method described above.
The data is written in the data storage unit 21 via 2.

[0005]

In the above-mentioned conventional memory device, since the check bit generating means is always passed at the time of writing, it takes time for the writing operation. Further, at the time of partial writing, there is a problem that a longer time is required because the reading and writing operations are performed as described above.

[0006]

A storage device of the present invention holds a data memory array that can be read from and written to at any time, and redundant information for detecting and correcting an error in data at each address of this memory array. A check bit memory array, a data storage unit including a dirty display memory array that holds at least 1 bit of information indicating that writing has been performed to each address of the data memory array, and is connected to the data storage unit. Check bit generation means for generating redundant information corresponding to the content of write data, error detection means connected to the data storage section for detecting and correcting an error based on the content of read data and redundant data, and the check bit. Another device connected to the generation means and the error detection means by an address bus and a data bus Access control means for accepting read / write access from the memory array to read / write data from / to the memory array of the data storage unit and writing information indicating that data has been written to the dirty display memory array during writing. A storage device comprising: an error monitoring unit connected to the check bit generating unit and the error detecting unit to periodically read all addresses and correct the error by the information of the check bit array and the information of the data memory array, At the time of a write access, the check bit is not generated and the transferred data with the information written in the corresponding dirty display memory array is directly written to the data memory array and the check bit is added later by the error monitoring means. Is characterized by.

[0007]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a storage device of the present invention.

The storage device 1 of the present embodiment is a data storage unit 11 comprising a data memory array 111, a check bit memory array 112 and a dirty display memory array 113.
A check bit generator 12, an error detector 13,
The access control unit 14 includes the dirty display generation unit 141 and the error monitoring unit 15. The storage device 1 is generally connected to the control device 3 through a processor bus 4 and receives requests for reading and writing data from the control device 3.

A write request from the control unit 3 is accepted by the access control unit 14, and the dirty display generation unit 141 adds information for displaying the write to the write data, and the dirty display memory array 113 of the data storage unit 11 is added.
And write directly to the data memory array 111. At the time of reading, the data memory array 1 in the data storage unit 11
The data in 11 and the corresponding check bit and stain display information are stored in the check bit memory array 112,
The data is read from the dirty display memory array 113 and delivered to the error detection unit 13.

If there is no written display in the dirty display information, the error detection unit 13 corrects an error that can be corrected by the data and the check bit 1, and the read data is sent to the control device 3 through the access control unit 14 and the processor bus 4. Forward. If there is a write indication, the contents of the data memory array 111 are read out as they are without performing normal error detection and transferred as data to the access control unit 14, processor bus 4 and control device 3.

The error monitoring unit 15 periodically receives data from the data storage unit 1.
The dirty display, data, and check bit are read from each address of 1 and passed to the error detection unit 13. Similar to reading
In the error detection unit 13, if there is a writing display, the data remains as it is.
Hand over to 5. The error monitoring unit 15 passes the data received from the error detection unit 13 to the check bit generation unit 12, adds a corresponding error detection code, and adds the data to the data storage unit 11.
The data is written in the data memory array 111 and the check bit memory array 112 inside. At this time, the data having no writing display at the corresponding address of the dirty display memory array 113 is written.

As described above, in this embodiment, when the write request is accepted, the check bit is not generated, and the check bit is added by the error detecting means.

[0013]

As described above, according to the present invention, since the check bit is not generated at the time of write access, the write access time and cycle time are shortened. Further, even in partial writing, it is not necessary to perform the two steps of reading and writing as in the conventional method described above, so that there is an effect that speedup and hardware simplification are possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a storage device of the present invention.

FIG. 2 is a block diagram showing an example of a conventional storage device.

[Explanation of symbols]

 1, 2 Storage device 3 Control device 4 Processor bus 11, 21 Data storage unit 12, 22 Check bit generation means 13, 23 Error detection means 14, 24 Access control means 15, 25 Error monitoring means 111, 213 Data memory array 112, 212 Check Bit Memory Array 113 Dirty Display Memory Array 141 Dirty Display Generating Means

Claims (1)

[Claims] 1. A data memory array that can be read and written at any time, a check bit memory array that holds redundant information for detecting and correcting an error in data at each address of the memory array, and a data memory array of the data memory array. A data storage unit including a dirty display memory array that holds at least 1-bit information indicating that writing has been performed for each address, and redundant information corresponding to the contents of write data connected to the data storage unit Check bit generation means for generating, error detection means connected to the data storage section for detecting and correcting an error based on the contents of read data and redundant data, and an address connected to the check bit generation means and error detection means. Accepts read and write access from other devices via bus and data bus Access control means for writing / reading data to / from the memory array of the data storage unit and writing information indicating that data has been written to the dirty display memory array at the time of writing, the check bit generating means and error detection. A memory device connected to the means for periodically reading all addresses and correcting an error based on the information of the check bit array and the information of the data memory array, and generating a check bit at the time of write access. The storage device is characterized in that the data transferred with the information written in the corresponding dirty display memory array is directly written in the data memory array as it is, and a check bit is added later by the error monitoring means.