JPH11164261A - Digital video signal processing unit and digital video signal reproduction device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow a conceal circuit to conduct correction normally even in the slow reproduction mode. SOLUTION: A field detection section 103 detects a field of an input image data. Image data corrected by a conceal processing section 102 based on a write permission signal fed from the detection section 103 are written in a memory A105 or a memory B106 corresponding respectively to a 1st field or a 2nd field which is coincident with an input field. A selector 107 selects the memory 105 or 106 coincident with the input field. The conceal processing section 102 receives image data read from the memory, input image data and a current error flag. The conceal processing section 102 uses them to apply correction processing to them.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal processing apparatus and a digital video signal reproducing apparatus capable of performing modification without causing image quality deterioration during variable speed reproduction such as slow reproduction.

[0002]

2. Description of the Related Art For example, using a magnetic tape as a recording medium,
Record / reproduce video signals in digital format,
Digital video cassette recorders (hereinafter abbreviated as DVCRs) have become widespread. In such a DVCR,
For digital video signals, for example, DCT (Discret
e Cosine Transform), and error correction coding is performed by, for example, product coding using Reed-Solomon code. Then, the encoded digital signal is recorded on a magnetic tape.

[0003] Recording on a magnetic tape is performed by, for example, a helical scan method in which tracks are formed diagonally on a tape wound diagonally around a rotary head.

In order to perform recording / reproduction more reliably, subsampling is performed on a digital video signal. FIG. 16 schematically illustrates this subsampling. The frame is divided, for example, in the line direction into a group consisting of even-numbered (white circles in FIG. 16) pixels and a group consisting of odd-numbered (black circles in FIG. 16) pixels.

For example, when the above-mentioned DCT is performed by a DCT block of 8 samples × 8 lines, first, a frame is divided into a block 200 composed of 16 samples × 8 lines shown in FIG. 16A. Then, as shown in FIG. 16B, the pixels in the block 200 are divided into two DCT blocks 201 each composed of 8 samples × 8 lines in the line direction.
A and 201B, and sub-sampling is performed.

[0006] The above-described compression encoding is performed for each DCT block obtained in this manner, and subsequent error correction encoding is performed. Also, when recording on magnetic tape,
For example, tracks recorded for each group are distinguished.
By performing sub-sampling in this way, for example, data can be mutually compensated between groups, and data reliability increases.

For a signal reproduced from a magnetic tape,
First, the error correction code is decoded. At this time,
If the signal contains an error equal to or greater than the error correction capability of the error correction code, an error flag is set at the corresponding position. The digital video signal subjected to error correction decoding is decompressed and supplied to a concealing circuit. The concealing circuit corrects the data including the error based on the error flag added when decoding the error correction code. The signal thus modified is output as a final digital video signal.

As one of the retouching methods, a method using the above-described subsampling is known. FIG. 17 schematically shows the modification using the sub-sampling. It is assumed that a pixel G in the frame 202 before the modification is a pixel in which an error has occurred. By sub-sampling, the pixel data is divided into a group composed of odd-numbered pixel data in the horizontal direction and a group composed of even-numbered pixel data. That is,
In this example, if the pixel G is odd-numbered pixel data,
Pixels A, B, C, D, E, and F are even-numbered pixels.

In the frame 202, since the pixel G has an error, it is necessary to create data by modification. When performing the modification, first, the motion of the pixel is detected.
Corresponding to the positions of pixels A, B, C, D, E, and F,
Between the pixels A ', B', C ', D', E ', and F' in the corresponding frame 202 'one frame before and the pixels A, B, C, D, E, and F in the frame 202 Then, the data between the pixels at the corresponding positions are compared, and if the maximum value among them exceeds a predetermined threshold value R,
It is determined that there is movement. Otherwise, it is determined that it is stationary.

That is, the pixels A ', B', C ', D',
E ′ and F ′, and pixels A, B,
Between C, D, E, and F, R = max (| AA ′ |, | BB ′ |, | CC ′ |, | DD ′ |, | E−E ′ |, | FF ′ |) (1) is calculated. The function max () takes the maximum value of each of the elements.

If it is determined that the vehicle is stationary as a result of the calculation of equation (1), the correction in the time direction, that is,
The modification is performed by using the pixel G ′ at the same position in the frame 202 ′ one frame before as the pixel G of the frame 202. That is, G = G '(2).

On the other hand, if it is determined that there is a motion as a result of the equation (1), spatial modification is performed, that is, in the same frame 202, an adjacent pixel belonging to a different group from the pixel in which the error has occurred belongs. The data of the pixel G is created by weighting the pixel data according to the distance between the position of the pixel G and another pixel. For example, G = (A + B + 2C + 2D + E + F) / 8 (3) The data of the pixel G is created and modified as described above.

FIG. 18 shows an example of the configuration of a concealment circuit 203 according to the prior art which performs such processing. The concealed image data is supplied to the terminal 210. The image data of the first field is the terminal 21
From 0, it is supplied to the concealing processing unit 211 and written into the field memory A212. An error flag corresponding to each of the pixels in the first field is output to terminal 2
14 to the error flag memory A215.

In a second field period following the first field, image data is read from the field memory A 212, and the read image data is written to the field memory 213. At the same time, the image data of the second field is stored in the field memory A via the terminal 210.
212 is written. Similarly, the error flag read from the error flag memory A 215 during the second field period is written into the error flag memory B 216, and the error flag memory A 215 stores the error flag corresponding to each pixel of the second field. The written error flag is written.

Further, in the third field following the second field, data is read and written in the field memory A212 and the field memory B213 and the error flag memory A215 and the error flag memory B216 in the same manner. Then, the image data read from the field memory B 213 and the error flag read from the error flag memory B 216 are supplied to the concealment processing unit 211, respectively. That is, in the third field period, the concealment processing unit 211 is supplied with the image data of the third field and the image data of the first field, and is supplied with corresponding error flags.

In reproduction at normal speed in which reproduction is performed at the same speed as at the time of recording, image data for one frame is stored in the field memory A212 and the field memory B213. Therefore, by using the image data of the field memory A 212 and the field memory B 213, the modification based on the above-described equations (1), (2), and (3) can be performed.

[0017]

However, in the modification by the conventional method, a problem occurs when slow reproduction is performed. FIG. 18 shows an example in which the concealing processing unit 211 modifies image data obtained by slow reproduction. In this example, the reproduction is performed at 0.5 times speed, that is, half the speed at the time of recording. FIG.
8A, FIG. 18B, and FIG.
0, image data in the field memory A212 and the field memory B213. In the figure,
Symbols such as “A” and “B” represent frames, and “1”,
“2” represents a first field and a second field, respectively.

In 0.5-times speed reproduction, for example, a track formed on a magnetic tape is scanned twice, and image data of the same field is reproduced twice. Therefore, as shown in FIG. 18A, the first and second fields of the frame A, the first and second fields of the frame B,.
Thus, the image data of each field is supplied twice. As a result, the field memory A212 and the field memory B213 also store in FIG.
As shown in FIG. 8C, the image data of the same field is written twice, each being shifted by one field period.

For this reason, at the time of this 0.5 × speed reproduction,
The image data shown in FIG.
12 and the field memory B 213 in FIG.
As shown in FIG. 18B and FIG. 18C, there is no image data one frame before. Therefore, the motion detection at the time of the retouching by the above formula (1) is not correctly performed, and the retouching process by the above formulas (2) and (3) cannot be performed correctly. As a result, there is a problem that the concealing processing unit 211 cannot perform appropriate modification, and causes deterioration in image quality.

Accordingly, an object of the present invention is to provide a digital video signal processing device and a digital video signal reproducing device that can perform normal modification even in slow reproduction.

[0021]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a digital video signal processing apparatus for correcting a digital video signal having an error exceeding an error correction capability by an error correction code. , A first field storing a first field of the input video signal
, A second memory for storing a second field of the input video signal, detection means for detecting the first and second fields of the input video signal, and a first memory and Of the second memory,
Selecting means for selecting a memory on the side that matches the field of the input video signal; an input video signal; and a video signal read from the memory selected by the selecting means from the first memory and the second memory And a concealment processing means for modifying a pixel indicating an error based on an error flag corresponding to the input video signal using the input video signal.

According to another aspect of the present invention, there is provided a digital video signal processing apparatus for correcting a digital video signal having an error exceeding an error correction capability by an error correction code. A first memory for storing a first field of the video signal; a second memory for storing a second field of the video signal;
Detecting means for detecting the first and second fields of the input video signal, and selecting a memory corresponding to the field of the input video signal from the first memory and the second memory based on a detection result by the detecting means Means for selecting,
An error is detected based on an error flag corresponding to the input video signal, using the input video signal and the video signal read from the memory selected by the selection unit out of the first memory and the second memory. Concealment processing means for modifying a pixel indicating that the video signal is stored in the first memory and the second memory is a video signal modified by the concealment processing means. Is a digital video signal processing device.

According to another aspect of the present invention, there is provided a digital video signal reproducing apparatus for reproducing a digital video signal stored in a storage medium, the digital video signal being reproduced from a recording medium. Error correcting means for correcting an error of a video signal based on the error correction code thus obtained, compression decoding means for decompressing a video signal error-corrected by the error correcting means, and compression decoding means If the video signal decompressed by the compression has an error exceeding the error correction capability of the error correction code, the concealing means has a concealing means for modifying the video signal.
A first memory for storing a first field of the input video signal input to the concealing means, a second memory for storing a second field of the input video signal, and detecting the first and second fields of the input video signal Detecting means for
Selecting means for selecting, from the first memory and the second memory, a memory corresponding to a field of the input video signal based on a detection result by the detecting means; an input video signal; a first memory and a second memory; Concealment processing means for correcting a pixel indicating an error based on an error flag corresponding to an input video signal using a video signal read from a memory selected by the selection means among the memories A digital video signal reproducing apparatus characterized by using a digital signal processing apparatus comprising:

According to another aspect of the present invention, there is provided a digital video signal reproducing apparatus for reproducing a digital video signal stored in a storage medium, the digital video signal being reproduced from a recording medium. Error correcting means for correcting an error of a video signal based on the error correction code thus obtained, compression decoding means for decompressing a video signal error-corrected by the error correcting means, and compression decoding means Concealing means for modifying the digital video signal when the digital video signal decompressed and encoded by the digital video signal has an error exceeding the error correction capability of the error correction code, the concealing means comprising: A first memory for storing the first field and a second memory for storing the second field of the video signal. And Li, and detecting means for detecting the first and second fields of the input video signal input to conceal means, based on the detection result by the detecting means, first
Selecting a memory corresponding to the field of the input video signal from the memory and the second memory; and selecting the input video signal and the memory selected from the first memory and the second memory. Concealment processing means for modifying a pixel indicating an error based on an error flag corresponding to the input video signal using the video signal read from the memory on the
The video signal stored in the second memory and the second memory is a digital video signal reproducing device using a digital signal processing device that is a video signal modified by concealing processing means.

As described above, according to the present invention, the first and second fields of the video signal are stored in dedicated memories, respectively, and the input video signal and the fields of the input video signal are modified at the time of modification by the concealing means. The video signal read from the matching memory is used.
Therefore, the concealing means can always perform the retouching process using the video signal one frame before.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. First, a DVCR to which the present invention can be applied will be described to facilitate understanding of the present invention. The DVCR shown in this example is 1125 / 60H
The video signal is handled by the z system. Recording performed by the DVCR is performed by a helical scan method in which a track is formed obliquely with respect to a magnetic tape by a magnetic head provided on a rotating drum, for example. The azimuth method is used in which the azimuth is made different in adjacent tracks by the magnetic head and recorded.

FIGS. 1 and 2 show an example of this recording method. As shown in an example in FIG.
Magnetic heads 2A, 2B, 2C, and 2D for recording
Is provided. The four magnetic heads 2A, 2B, 2C, and 2D are set as a set of two magnetic heads, and are disposed at positions facing each other. 180 ° opposed magnetic heads 2A, 2C
And the magnetic heads 2B and 2D have the same azimuth, and these sets have different azimuths.

A magnetic tape is wound around the rotary drum 1 at a winding angle of, for example, 180 °. Each time the rotating drum 1 rotates by 180 °, the signal to the magnetic head opposed thereto is switched. This switching point is called a switching point. Thus, when the channels corresponding to the respective heads are A, B, C, and D, these four magnetic heads 2A, 2B, 2C, and 2D
As shown in FIG. 2, tracks A and B are formed on the magnetic tape 4 by the magnetic heads 2A and 2B, and tracks C and D are formed by the magnetic heads 2C and 2D.

Of the tracks formed, A and C,
B and D are tracks with the same azimuth. At this time, a segment is composed of two adjacent tracks (A and B channels and C and D channels) having different azimuths. Also,
One frame of the video signal includes 12 tracks. Therefore, one frame of the video signal is composed of six segments. Each of these six segments is assigned a segment number from 0 to 5. In addition, 4
The audio data having a channel is arranged, for example, at the center of a track so as to be sandwiched between video data.

The rotating drum 1 is further provided with reproducing magnetic heads 3A, 3B, 3C and 3D. The arrangement of these magnetic heads 3A, 3B, 3C, and 3D and the relationship of azimuth are the same as those of the above-described recording magnetic heads 2A, 2B, 2C, and 2D. When reproducing from a magnetic tape, these magnetic heads 3A, 3A
B, 3C, and 3D are used.

FIGS. 3 and 4 show an example of the configuration of the digital video tape recorder. FIG. 3 shows an example of the configuration on the recording side, and FIG. 4 shows an example of the configuration on the reproducing side. The configurations shown in FIGS. 3 and 4 are separately illustrated, but some configurations can be shared. Here, it is assumed that a video signal by the above-mentioned 1125 lines / 60 Hz system is handled.

In the configuration on the recording side shown in FIG. 3, the input terminal 10 has 1.48 based on the S-004 standard of BTA.
A serial digital A / V signal having a rate of 5 Gbps (bits per second) is input. FIG. 5 shows a transmission format of the serial digital A / V signal.
The numbers in the vertical direction indicate line numbers, and the numbers in the horizontal direction indicate sample numbers. According to the order of the line numbers, data is serially transmitted for each line in the order of the video sample number. One frame of image and sound is transmitted by 2200 samples in the horizontal direction and 1125 lines in the vertical direction.

In the horizontal direction, the 0th sample to the 1919th sample
1920 samples of the sample are used as the effective image area,
A video signal is transmitted in a line other than the vertical blanking period. SAV indicating the beginning of this effective video area
Is inserted between the 2196th sample and the 2199th sample. The EAV indicating the end of the effective video area is the 19th.
It is inserted between the 20th sample and the 1923th sample. The audio signal is transmitted by 268 samples from the 1928th sample to the 2195th sample. The line number LN is inserted into the 1924th sample and the 1925th sample. CRCC (Cyclic Redundancy Check C
odes) is 1926th sample, 1927th
Inserted into the sample.

In the vertical direction, the first line to the 40th line, the 558th line to the 602nd line, and the 112th line
Line 1 to line 1125 are the vertical blanking period. The video signal for one field is transmitted by the above-described 0th to 1919th samples on the 41st to 557th lines and the 603rd to 1120th lines.

Incidentally, the configuration on the recording side has a timing generator 30, and 1125 lines / 60 Hz,
1125 lines / 59.94 Hz, or 525 lines / 5
A system clock, such as 9.94 Hz, is supplied according to the applied system. Then, based on the system clock, clocks such as the horizontal synchronization signal Hsync and the frame synchronization signal Fsync required for the configuration on the recording side shown in FIG. 3 are generated. further,
In this example, 74.25 MHz and 46.4 (46.
40625) Clocks corresponding to MHz are respectively generated.

The serial signal supplied to the S / P converter 11 is converted into a parallel signal at a rate of 74.25 MHz and output. In the parallel signal, the supplied serial signal includes a luminance signal Y and color difference signals Pr and Pb, and has a data width of, for example, 8 bits.
It is converted into a 2: 2 signal. The converted 4: 2: 2 signal is supplied to the coprocessor 12. The coprocessor 12 has, for example, one ASIC (Applicati
on Specific Integrated Circuit).

The coprocessor 12 performs processing on the supplied parallel signal. By this processing, the digital audio signal, the line number LN, the CRCC detection code, and the SA included in the supplied 4: 2: 2 signal are obtained.
V and EAV are separated and taken out. Of these, the digital audio signal is the audio signal processing circuit 1
6. On the other hand, other data, that is, the line number LN, CRCC detection code, and SAV, EAV are
Each 4: 2: 2 signal is added for each horizontal cycle.

FIG. 6A conceptually shows a 4: 2: 2 signal to which data such as a line number has been added by the coprocessor 12. The luminance signal Y is sequentially transmitted according to a clock having a frequency of 74.25 MHz. On the other hand, the color difference signals Pr and P
b is transmitted with the data amount halved because of the band compression. For example, the luminance signals Y ₀ and Y ₁ include the color difference signal P
b ₀ and Pr ₀ correspond to each other, and the luminance signals Y ₂ and Y ₃ correspond to the color difference signals Pb ₁ and Pr ₁ , respectively.

Based on the Hsync supplied from the timing generator 30, four SAVs and four EAVs are provided for the beginning and end of the 1920 clocks indicating the effective video area in the supplied 4: 2: 2 signal. Can be After the EAV, the line numbers LN ₀ and LN ₁ generated based on the line number LN are inserted. Further, CRCC detection codes CR ₀ and CR ₁ are inserted after these line numbers LN ₀ and LN ₁ .

Since the number of effective lines in the vertical direction is 1125, the line number LN can be represented by 11 bits. FIG. 7 shows an example of bit assignment in the line numbers LN ₀ and LN ₁ in which the line number LN is represented by 2 bytes. In this example, all bits of LN ₀ (L ₇ to L ₇ )
L ₀ ) and 3 bits from the LSB of LN ₁ (L ₁₀ to L ₁₀ )
L ₈ ), the line number is represented by 11 bits, and M of LN ₁
SB indicates whether this line is a first field or a second field. L ₆ ~L ₃ of LN ₁ are not used.

Thus, the audio signal is separated by the coprocessor 12 and the 4: 2: 2 signal to which the data such as the line number is added is supplied to the input filter 13. Note that for this input filter 13,
A 4: 2: 2 signal can be supplied directly from the input terminal 15. In this case, the digital audio signal is supplied to the audio signal processing circuit 16 via the input terminal 17.
Supplied to

The input filter 13 performs band compression on the supplied signal. For example, one ASI
C. Also, this input filter 13 includes:
The memory 14 is connected, and clocks of 74.25 MHz and 46.40625 MHz are supplied from the timing generator 30, respectively.

4 supplied to the input filter 13:
Line numbers LN ₀ and LN ₁ are extracted from the 2: 2 signal. In the input filter 13, the band is compressed from the 4: 2: 2 signal to the 3: 1: 1 signal. That is, FIG.
As shown in FIG. 8B, 8 in the 4: 2: 2 signal
If the luminance signal Y for the sample is a 3: 1: 1 signal, it is 6
Band compression is applied to the samples. Correspondingly, the color difference signals Pr and Pb for two samples are respectively 1
Band compression is applied to the samples.

In this band-compressed signal, the luminance signal Y and the color difference signals Pr and Pb are serially divided into two channels of signals Ch0 and Ch1 and rearranged.
The rate is 6.40625 MHz. That is, this rearrangement is performed in units of six samples of luminance signals Y ₀ , Y ₁ , Y ₂ ... As shown in FIGS. 8B and 8C described above, and even-numbered samples Y ₀ , Y ₂ , Y ₄
.. And odd-numbered samples Y ₁ , Y ₃ , Y ₅ . Similarly, the color difference signal P
r and Pb are replaced with even samples Pr ₀ , Pr _2.
And Pb ₀ , Pb ₂ ... And odd-numbered samples Pr ₁ ,
Pr ₃ distributed to and ... and Pb _1, Pb _3. Then, the luminance signal Y and the color difference signals Pr / Pb are serially arranged for even samples and for odd samples, respectively. Even-numbered samples are arranged in the signal Ch0, and odd-numbered samples are arranged in the signal Ch1. By this rearrangement, sub-sampling is performed as described in the above-described related art.

Further, the input filter 13 outputs a signal to each of the signals Ch0 and Ch1 for each line.
Line numbers LN ₀ and LN ₁ are inserted. Further, in this input filter 13, signals Ch0 and C0
h1 is subjected to CRCC operation, and the resulting CRCC detection code is converted to signals Ch0 and Ch0.
1 is assigned to each. Input filter 13
The above processing in is performed using a predetermined area of the memory 14, for example.

FIG. 6B is divided into channels Ch0 and Ch1, and CRCC detection code CRCC and line numbers LN ₀ and LN ₁ are used for channels Ch0 and Ch1.
2 shows an example of the signal format of the signals Ch0 and Ch1 inserted respectively in FIG. As described above, this signal has a clock frequency of 46.4 MHz and 1
The horizontal cycle consists of 1375 clocks. Of these, the effective pixels are 1200 clocks. Here, the signal Ch0 will be described.

The start of one horizontal cycle is indicated by the rise of Hsync0, which is a horizontal synchronization signal corresponding to signal Ch0, and line numbers LN ₀ and LN are provided for two clocks.
N ₁ is inserted. Subsequently, the band-compressed luminance signal Y and color difference signals Pr / Pb are serially inserted. 1
A CRCC detection code for one clock is inserted after the luminance signal Y and the color difference signals Pr / Pb for the lines.
Then, at the 1375th clock from the first Hsync of one horizontal cycle, the next Hsync is supplied for one clock.

In the above description, the line numbers LN ₀ , LN ₁
Has been described as being inserted at the beginning of the effective video area, but this is not limited to this example. For example, line number L
N ₀ and LN ₁ may be inserted at the end of the effective video area.

The horizontal synchronization signal Hsync is provided for each of the signals Ch0 and Ch1.
These are referred to as Hsync0 and Hsync1, respectively. This corresponds to the processing after the input filter 13 being performed on the signals Ch0 and Ch1 by, for example, separate ASICs.

Although omitted in FIG. 3,
In the input filter 13, the signals Ch0 and Ch1
, A frame-based synchronization signal F
sync0 and Fsync1 are also output at the same time. However,
Since the change points of the frame can be easily known from the line numbers LN assigned to the signals Ch0 and Ch1, respectively, these Fsync0 and Fsync1 can be omitted.

From the input filter 13, the signal Ch0
And Hsync0, and signals Ch1 and Hsync1 are output, respectively. These signals are respectively BR
It is supplied to R (Bit Rate Reduction) encoders 18 and 19. The BRR encoders 18 and 19 are connected to memories 20 and 21, respectively, and encode the supplied signals by, for example, DCT (Discrete Cosine Transform) and quantize the signals so that the signals are compressed at a predetermined compression rate. Perform compression encoding. In this example, the image compression ratio is 1
/4.4.

The BRR encoder 18 extracts line numbers LN ₀ and LN ₁ from the supplied signal Ch0. The signal Ch0 is transmitted to the encoder 1 during compression encoding.
At 8, shuffling is performed in units of DCT blocks composed of, for example, 8 × 8 pixels. Each of the shuffled DCT blocks is written to a predetermined address in the memory 20. Since the writing control to the memory 20 is performed by the address control based on the line number LN, the position of the effective video area can be adjusted even if the line is discontinuous during the vertical blanking period, for example.

The signals Ch0 and Ch1 which have been subjected to the compression encoding processing by the BRR encoders 18 and 19, respectively.
Are supplied to an ECC (Error Corrected Coding) encoder 22 together with the corresponding horizontal synchronization signal Hsync. At the same time, the audio signal processing circuit 16
The digital audio signal which has been subjected to a predetermined process and output is also supplied to the ECC encoder 22.

The ECC encoder 22 uses the connected memory 23 to perform an error correction encoding process on the supplied signal using, for example, a product code. That is, as described in the above-described related art, the outer code parity and the inner code parity are generated for the data written in the memory 23, that is, the signal Ch0, and error correction coding of the product code is performed. The size of the data in which the product code of the inner code and the outer code is completed is called an error correction block.

The memory 23 is divided into, for example, two areas, and the processing of the inner code and the outer code is performed in each area. Also, the processing of the inner code and the outer code can be performed by devising a data access method without dividing the area. Memory 23,
It may be configured with two memories that respectively perform the processing of the inner code and the outer code.

FIGS. 9 and 10 schematically show an example of the configuration of the error correction block. As already shown in FIGS. 1 and 3, in the digital video tape recorder shown in this example, signals are recorded on the magnetic tape 4 by helical tracks. ECC encoder 2
The error correction encoding process in No. 2 is performed for each helical track.

In the example of the video data shown in FIG. 9, one track in the 12 frames is one error correction block shown in FIG. 9B as shown in FIG. 9A. ECC
When all of the 226 sync blocks shown in FIG. 9B arrive at the encoder 22, 217 shown in FIG.
A data array of bytes × 226 bytes is formed. With respect to this data, the data of each column is encoded by, for example, a (250, 226) Reed-Solomon code in the direction of arrow b to generate a 24-byte outer code parity. Further, with respect to the video data and the outer code parity, the data of each row is, for example, (229,
219) Encoded by Reed-Solomon code,
An inner code parity of the byte is generated. At this time, sync data and ID each having a size of 2 bytes are arranged at the head of each data row, and the inner code is calculated including this.

FIG. 10 shows an example of the configuration of an error correction block in audio data. As shown in FIG. 10A, audio data forms one error correction block shown in FIG. 10B with six tracks out of twelve tracks for one frame. For example, for audio data composed of a data array of 217 bytes x 12 bytes,
In the direction of arrow b, encoding is performed by, for example, a (24,12) Reed-Solomon code, and a 12-byte outer code parity is generated. Further, with respect to the video data and the outer code parity, for example, (22)
9, 219) encoded by a Reed-Solomon code,
A 12-byte inner code parity is generated. At that time, sync data and ID are arranged at the head of each data row, and the inner code is calculated including the sync data and ID.

FIG. 11 schematically shows the structure of one sync block in these error correction blocks, taking video data as an example. The first two bytes are sync data. The next two bytes are an ID, which describes the number (sync block number) of this one sync block in one track. This ID is generated based on ID0 and ID1 arranged at the head of the sync block. This ID is followed by 217 bytes of video data (or outer code parity) and inner code parity. The recording data on the magnetic tape 4 is a sequence of the sync blocks.

The signal error-correction-encoded by the ECC encoder 22 is replaced with a recording rate frequency on the magnetic tape 4 in units of error correction blocks, and converted into signals of four channels A, B, C, and D. Channel A / C and channel B / D
It is output as a system signal.

That is, in the signal Ch 0 supplied from the BRR encoder 18, for example, an error correction block composed of the first 226 sync blocks is set as the channel A,
The error correction block consisting of the following 226 sync blocks is channel C, and the ECC encoder 22 outputs
These channels A and C are output alternately. Similarly, the signal Ch1 supplied from the BRR encoder 19
, Error correction blocks respectively corresponding to channels B and D are generated, and ECC encoder 2
2, these channels B and D are output alternately.

The two channels A / C and B / D output from the ECC encoder 22
The system signals are supplied to the recording drive circuit 24, respectively. Then, the data is modulated and amplified so as to be recordable on the magnetic tape 4 and output. The output signal is supplied to the magnetic head 2A or 2C for the channel A / C and supplied to the magnetic head 2B or 2D for the channel 2B or 2D, and is recorded on the magnetic tape 4.

In FIG. 3, in order to avoid complexity, the magnetic heads 2A, 2B, 2C, and 2D for recording are replaced by two magnetic heads 2A or 2C, 2B or 2D, and these four heads. Signal paths for each of the magnetic heads are omitted in two systems. Also,
The recording drive circuit 24 has a changeover switch corresponding to the rotation of the rotary drum 1, and can switch and output the channels A and C and the channels B and D with respect to the rotation of the rotary drum 1 by 180 °. it can.

Next, processing on the reproduction side will be described with reference to FIG. The signals recorded on the magnetic tape 4 are reproduced by the read magnetic heads 3A, 3B, 3C, and 3D. As described above, the magnetic heads 3A,
By 3B, 3C, and 3D, tracks A, B,
C and D are reproduced respectively. Reproduction signals (signals A / C) reproduced from the magnetic heads 3A and 3C are supplied to the equalizer 40. Similarly, reproduction signals (signals B / D) reproduced from the magnetic heads 3B and 3D are supplied to the equalizer 47. Hereinafter, the description will be focused on the signal A / C supplied to the equalizer 40.

In FIG. 4, in order to avoid complication, the magnetic heads 3A, 3B, 3C and 3D are
A or 3C, 3Bor3D, and 4
Signal paths for each of the two magnetic heads are omitted in two systems. Each of the equalizers 40 and 47 has a changeover switch corresponding to the rotation of the rotary drum 1 by 180 °. Thus, in the equalizer 40, the reproduction signals from the magnetic heads 3A and 3C are alternately processed. Similarly, in the equalizer 47, reproduction signals from the magnetic heads 3B and 3D are alternately processed.

In the configuration of FIG. 4, the timing generator 30 shown in FIG. 3 is commonly used.

The equalizer 40 outputs a signal A / C and a reproduced clock generated by the rotation of the rotary head 1. These signals are sent to the ECC decoder 41
Supplied to The ECC decoder 41 is supplied with a clock of 46.40625 MHz from the timing generator 30, and is connected to the memory 42. The ECC decoder 41 uses the memory 42 to perform error correction decoding of the supplied channel signal A / C.

That is, the signal A / C reproduced for each track and supplied in units of error correction blocks is subjected to error correction decoding by an inner code and an outer code. The error-corrected decoded signal A / C is put on a clock of 46.40625 MHz and output in sync block units.
It is supplied to the BRR decoder 43 in the next stage.

If a signal contains an error exceeding the error correction capability of the error correction code, an error flag is set for each pixel having an error, indicating that error correction could not be performed. FIG. 12 schematically illustrates how an error flag is transmitted for a video signal. The output from the ECC decoder 41 is a 3: 1: 1 signal as shown in FIG. 12A. On the other hand, the error flag is one of the DCT blocks consisting of 8 × 8 pixels.
It is attached every eight pixels corresponding to the line. Further, the luminance signal Y and the color difference signals Pb and Pr are combined.

Therefore, as shown in FIG. 12B, the error flag is transmitted every 40 clock cycles of the video signal. The error flag is 8-bit data with a 1-bit error flag attached to each of the 8 pixels. This error flag is transmitted with a data width of 16 bits, together with the quantized data value of the pixel data and the 8-bit flag “0RF” (the description is omitted because it has no direct relation to the present invention).

The error flag has a data width of 16 bits together with the flag “0RF” and is transmitted at the same clock. Subsequently, the quantized data value is transmitted for 7 clocks. Transmission is performed at the cycle of 8 clocks. First three
An error flag corresponding to the luminance signal Y is transmitted for one cycle, and an error flag corresponding to the color difference signals Pb and Pr is transmitted for the next two cycles.

The ECC decoder 41 generates a frame synchronization signal Fsync0 and a synchronization signal SYNC. These synchronization signals Fsync0
And the synchronization signal SYNC are output from the BRR decoder 4 respectively.
3 is supplied.

The BRR decoder 43 is supplied with a clock of 46.40625 MHz from the timing generator 30. The BRR decoder 43 can know the head of the frame based on, for example, ID0 and ID1 added to the head of the sync block. BRR decoder 4
In step 3, the supplied signal A / C is subjected to inverse DCT conversion and deshuffling using, for example, the memory 44 to decode a compression code.

The decoded signal A / C is 46.406
Based on the 25 MHz clock, the luminance signal Y and the color difference signals Pr / Pb as shown in FIG. 6B are serially arranged signals. Further, line numbers LN ₀ and LN ₁ are given to each line. The data of each DCT block is written at a predetermined position in the memory 44 by the decoded ID according to the line number, and is added in reading from the memory 44 in accordance with the reading order. That is, the signal A /
The output corresponding to C is a signal equivalent to the signal Ch0 in the configuration on the recording side described above. Hereinafter, this signal corresponding to signal A / C is referred to as signal Ch0 for convenience. The signal Ch0 is supplied to a concealing circuit 45 that performs a modification process on image data constituting a video signal.

In the BRR decoder 43, a synchronization signal Hsync0 is also generated. This Hsync0 is also supplied to the concealing circuit 45.

Signal B / D output from equalizer 47
, The same processing as described above is performed. That is,
The signal B / D supplied from the equalizer 47 to the ECC decoder 48 is subjected to error correction decoding using the memory 49. Along with the decoded signal B / D, the synchronization signal F
The sync and SYNC are output from the ECC decoder 48 and supplied to the BRR decoder 50. In the BRR decoder 50, decoding of the compression code of the supplied signal B / D is performed using the memory 51. Decoded signal B / D
Is based on a clock of 46.40625 MHz, the luminance signal Y and the color difference signals Pr / Pb are serially arranged, and line numbers LN ₀ and LN ₁ are added to make the signal equivalent to the above-mentioned signal Ch1. . Hereinafter, a signal corresponding to the signal B / D is referred to as a signal Ch1 for convenience. This signal Ch1 is supplied to the concealing circuit 45. Also, the synchronization signal Hsyn generated by the decoder 50
c1 is also supplied to the concealing circuit 45.

The ECC decoders 41 and 48, B
ASICs of the same standard can be used for the RR decoders 43 and 50, respectively.

The concealing circuit 45 includes, for example, one AS
An error that exceeds the error correction capability of the ECC decoder 41 or 48 in the reproduced signal,
For example, if there is a long error due to a scratch on the magnetic tape 4, the decoder 41 or 48 corrects the signal that could not be corrected.

Here, the concealing circuit 45 according to the subject of the present invention will be described in more detail. FIG.
Shows an example of a configuration of a main part of the concealing circuit 45 according to the embodiment. In addition, as shown in FIG.
The concealing circuit 45 is supplied with two inputs. In the concealing circuit 45, error correction is performed using the two systems of image data.

The image data shown in FIG. 12A among the signals output from the BRR decoder 43 is supplied to the terminal 100. An error flag is extracted from the signal including the error flag described above with reference to FIG.
1 is supplied.

The image data is supplied from the terminal 100 to the concealing processing unit 102 and the field detection unit 10
3 is supplied. In the field detection unit 103, the line number L assigned to the supplied image data (video signal)
The field to which the image data belongs is detected based on N ₀ and LN ₁ . For example, in this example where one frame is composed of 1125 lines, the line numbers LN ₀ and LN ₁ are the first
It is to be first field if shows a line to the 563 line, the line number LN _0, LN ₁ is to be the second field if shows a # 564 line to the 1125 line.

A selection signal based on the detection result is supplied to the selector 107. Further, based on the detection result, a write enable signal is supplied to the corresponding one of the field memories A105 and B106. The field memory A105 is a memory for writing the image data of the first field, and the field memory B106 is a memory for writing the image data of the second field.

The image data is sent from the terminal 100 to the field memory A 105 and the field memory B 106
Supplied to The supplied image data is written to the side of the field memory A 105 or the field memory B 106 that is permitted by the write permission signal supplied from the field detection unit 103. Based on the detection result, the field detection unit 103 permits writing in the field memory A105 if the image data supplied from the terminal belongs to the first field, and permits writing in the field memory B106 if the image data belongs to the second field. Output a write enable signal.

Outputs from the field memory A 105 and the field memory B 106 are supplied to the selector 10 respectively.
7 terminals 107A and 107B. The selector 107 selects the terminals 107A and 107B based on the selection signal output from the field detector 103. The output of the selector 107 is the concealing processing unit 102
Supplied to In the field detection unit 103, the terminal 10
If the image data supplied from 0 belongs to the first field, it outputs a selection signal for selecting the terminal 107A, and if it belongs to the second field, it outputs a selection signal for selecting the terminal 107B.

The same processing is performed on the error flag supplied from the terminal 101. That is, the terminal 10
The error flag supplied from the concealing processing unit 1
02 and an error flag memory A108
In addition, the data is written to the side of the error flag memory B109 to which writing is permitted by the write permission signal based on the detection result of the field detection unit 103. The error flag memory A108 and the error flag memory B1
The error flag read out from the selector 09
Are supplied to the terminals 110A and 110B, respectively.
The selector 110 selects the terminals 110A and 110B based on the selection signal output from the field detection unit 103. The output of the selector 110 is supplied to the concealment processing unit 102.

In the concealing processing section 102, the terminal 100
, (2), and (3) using the video signal directly supplied from, the image data output from the selector 107, and the error flag output from the selector 110. Based on the above, a modification process is performed.

The same field as the field supplied from the terminal 100 is selected by the selector 107 based on the detection result of the field detection unit 103. Image data one frame before the input image data, which is read from the selected one of the field memory A105 and the field memory B106, is supplied to the concealment processing unit 102. The concealing processing unit 102 performs motion detection based on the mathematical expression (1) using the image data one frame before and the input image data.

As a result of the motion detection, when it is determined that the image data is still, a pixel having an error is placed in the pixel data at the corresponding position in the image data of the immediately preceding frame based on the above equation (2). The error correction is performed by changing. On the other hand, if it is determined that there is a motion as a result of the motion detection, the modification is performed using the pixel data of a group different from the group having the error based on the above equation (3).
The concealed processing unit 102 outputs a modified video signal, which is output to an output terminal 104.

In this example, there is a possibility that the pixel data used for the correction has an error. Therefore, the error flag memory A108 and the error flag memory B109
The concealment processing unit 102 determines whether or not the pixel data used for the correction is an error, using the error flag written in the. If it is determined that an error has occurred, a modification process is performed as follows, for example. First, at the time of motion detection, pixels determined to be in error are not used for detection. If it is determined that there is a motion as a result of the motion detection, the pixel data having an error is excluded from the above equation (3), and the divisor is changed. If it is determined to be stationary, the interpolation in the time direction is changed to the interpolation in the spatial direction.

The memory 46 connected to the concealing circuit 45 in FIG. 4 can correspond to the field memory A105, the field memory B106, the error flag memory A108, and the error flag memory B109 in FIG. .

The video signal thus modified by the concealing circuit 45 is supplied to the post filter 53. In this example, since two systems are actually processed,
The signals Ch0 and Ch1 are post-filter 53, respectively.
Supplied to Also, the synchronization signals Hsy supplied separately for the channel A / C and the channel B / D, respectively.
nc0 and nc1 are integrated into a synchronization signal Hsync and supplied to the post filter 53.

The post filter 53 includes, for example, one AS
It is composed of IC. With this post filter 53, BRR
In the decoders 43 and 50 or the BRR encoders 18 and 19 on the recording side, irregular noise generated at the time of image compression / decompression is reduced. This processing is performed according to the supplied 46.
This is performed using the connected memory 54 based on a 40625 MHz clock. The signals Ch0 and Ch1 output from the post filter 53 and the synchronization signal Hs
ync is supplied to the output filter 55.

The output filter 55 is composed of, for example, one ASIC, and outputs a clock of 46.40625 MHz and a clock of 74.25 MHz from the timing generator 30.
z clock is supplied together. The output filter 55 converts the supplied signals Ch0 and Ch1 into 4: 2: 2 signals using the memory 56 based on the supplied clocks.

That is, the signals Ch0 and Ch1 supplied by the clock of 46.40625 MHz are 74.25.
Resampled at MHz. The re-sampled signal is temporarily written to the memory 56, for example. Then, interpolation is performed so that the ratio of the sampling frequency of the luminance signal Y, the color difference signal Pr, and the color difference signal Pb becomes 4: 2: 2. The 4: 2: 2 signal thus obtained is supplied to the video processor 57. The interface between the output filter 55 and the video processor 57 uses the above-described signal format shown in FIG. 6A.

In the video processor 57, predetermined processing such as adjustment of gain and offset is performed on the supplied 4: 2: 2 signal using the memory 58.
The processed 4: 2: 2 signal is led to output 59.

The audio signal is supplied to the audio processor 52 after error correction decoding by the ECC decoders 41 and 48. The audio signal subjected to the predetermined processing by the audio processor 52 is led out to a digital audio output terminal 63.

The 4: 2: 2 signal output from the video processor 57 can be output as a serial digital A / V signal. The 4: 2: 2 signal is supplied from the video processor 57 to the coprocessor 60. At the same time, a digital audio signal is supplied from the audio processor 52 to the coprocessor 60.
In the coprocessor 60, a digital audio signal is inserted into a 4: 2: 2 signal based on a clock of 74.25 MHz, and predetermined auxiliary data specified in a format is added. The output of the coprocessor 60 is supplied to a P / S converter 61.

The P / S converter 61 converts the 4: 2: 2 signal supplied as a parallel digital signal to 1.485 Gb.
The signal is converted into a serial digital A / V signal having a rate of ps. The 4: 2: 2 signal serially converted by the P / S converter 61 in accordance with the format shown in FIG. 5 is led to a serial digital A / V output terminal 62.

Next, a modification of the embodiment of the present invention will be described. In this modification, the concealing circuit 102
The image data is modified using the data modified in step (1). FIG. 14 shows an example of a configuration of a main part of a concealing circuit 45 according to this modification. In FIG. 14, portions corresponding to those in FIG. 13 used in the above-described embodiment are denoted by the same reference numerals, and detailed description is omitted.

As described above, in this modification, the terminal 100
The input image data supplied from the
It is not written directly to the field memory 105 or the field memory B106. These field memories A10
5 or the field memory B 106 is written with image data that has been modified by the concealing processing unit 102. Therefore, in the concealing processing unit 102, the input image data newly supplied from the terminal 100 is modified using the signal already modified in the concealing processing unit 102.

The image data modified by the concealing processing unit 102 is directly output to the output terminal 104, and thus becomes the image data sent one frame before. Since this can be visually judged to be error-free image data, the use of this data in the modification processing eliminates the need for an error flag. Therefore, in this modification, only the error flag corresponding to the input image data to be modified is used in the modification processing in the concealing processing unit 102. Therefore, in the concealing circuit 45, it is not necessary to store the error flags corresponding to each field.

The operation of the concealing circuit 45 will now be described.
This will be described with reference to the time chart of FIG. In the figure, symbols “A”, “B”, and “C” represent frames, and numerals “1” and “2” represent first and second fields, respectively. The modified data is indicated by adding “′”.

When slow playback at 0.5 × speed is performed, the terminal 1
00, image data in which the same field is repeated twice each is input as shown in FIG. 15A. This image data is first supplied to the concealing processing unit 102.

On the other hand, the image data modified by the concealing processing unit 102 is stored in the field memory A 105 based on the write permission signal output from the field detecting unit 103.
Alternatively, the data is written to the field memory B106. That is, the field memory A105 and the field memory B106 are memories for the first and second fields, respectively. For example, when image data of the first field is input to the terminal 100, the concealing processing unit The output of 102 is written.

Similarly, the output of the field memory A 105 (FIG. 15B) and the output of the field memory B 106 (FIG. 15C) are supplied to the selector 107 by the field detector 1.
03 is selected on the basis of the selection signal. Selector 10
7 is supplied to the concealing processing unit 102.

The selector 107 is connected to the field detector 10
Based on the detection result of 3, the selection corresponding to the field of the image data supplied to the terminal 100 is made. FIG. 15D
Indicates data thus selected and output from the selector 107. The selector 107 selects the terminals 107A and 107B corresponding to the input image data of FIG. 15A. In response to this selection, the field memory A10
15 and the image data read out from the field memory B106, as shown in FIG.
7 is output.

Therefore, for example, when image data belonging to the first field is supplied to the terminal 100,
The terminal 107A is selected by the selector 107, and the image data of the first field read from the field memory A105 is supplied to the concealment processing unit 102.

The concealing processing section 102 has a terminal 100
The image data (FIG. 15A) supplied to the selector 10 and the selector 10
The image data selected in FIG. 7 (FIG. 15D) is supplied. In the concealing processing unit 102, the input image data shown in FIG. 15A is modified based on the data thus supplied. This modification is performed by the same method as that described in the above-described embodiment based on Expressions (1), (2), and (3). That is, the correction is performed by motion detection using the data of the previous frame and interpolation in the spatial direction or the time direction based on the result of the motion detection.

FIG. 15E shows an output obtained by the modification in the concealing processing section 102. This output is output to an output terminal 104 and is output to the field detection unit 10.
3, the data is written to the corresponding one of the field memories A105 and B106.

Since the selector 107 selects the image data belonging to the field that matches the input image data, the concealment processing unit 102 can always perform the modification using the image data of one frame before.

In the concealing circuit 45 according to the above-described embodiment and modification, in the case of reproduction at 1 × speed or less, the image data of one frame before is always stored in the field memory A 105 and the field memory B 106. Exists. Therefore, it is possible to always normally perform the modification processing based on Expression (1), Expression (2), and Expression (3).

On the other hand, at the time of high-speed reproduction where the reproduction speed is higher than that at the time of recording, there are fields that cannot be reproduced. Therefore, it is impossible to capture image data of all fields. For this reason, the emphasis is placed only on stillness, taking into account that it is difficult to visually recognize the deterioration of the image quality with respect to the high-speed operation. In this case, the modification processing is the same as the processing in the case of 1 × speed or less, so that it is not necessary to change the operation of the memory control in the concealing circuit 45. Therefore, the modification processing method in the concealing circuit 45 according to the present invention is effective at any reproduction speed.

Although the recording medium on which the digital video signal is recorded is the magnetic tape 4 in the above description, the present invention is not limited to this example. Other recording media can be used, and for example, a disc-shaped recording medium such as an MO (Magnetic Optical) disc and a DVD (Digital Versatile Disc) can be applied.

[0114]

As described above, according to the present invention, the image data of the first and second fields are respectively written into the dedicated field memories, and the selector stores the image data from the field memory corresponding to the field of the input image data. Data is read. Therefore, always 1
The retouching process can be performed using the image data before the frame, and there is an effect that the retouching ability does not deteriorate at the time of variable speed reproduction.

Further, according to the present invention, in variable speed reproduction, the image data to be modified can always be compared with the image data of one frame before, so that there is an effect that accurate motion detection can be performed. .

Further, according to the modification of the embodiment of the present invention, the input image data is modified using the image data which has been modified, so that the memory for the error flag is reduced. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a schematic diagram illustrating an example of a recording method for a magnetic tape.

FIG. 2 is a schematic diagram illustrating an example of a recording method for a magnetic tape.

FIG. 3 is a block diagram showing an example of a configuration on a recording side of the digital video tape recorder.

FIG. 4 is a block diagram illustrating an example of a configuration on a reproduction side of the digital video tape recorder.

FIG. 5 is a block diagram illustrating an example of a configuration on a reproduction side of the digital video tape recorder.

FIG. 6 is a conceptual diagram showing a signal format used in an interface between each ASIC.

FIG. 7 is a schematic diagram illustrating an example of bit allocation in line numbers LN ₀ and LN ₁ .

FIG. 8 is a conceptual diagram showing a video signal handled in the embodiment.

FIG. 9 is a conceptual diagram illustrating an example of a configuration of an error correction block.

FIG. 10 is a conceptual diagram illustrating an example of a configuration of an error correction block.

FIG. 11 is a conceptual diagram showing the configuration of one sync block in an error correction block, taking video data as an example.

FIG. 12 is a schematic diagram illustrating transmission of a video signal and an error flag.

FIG. 13 is a block diagram illustrating an example of a configuration of a main part of the concealing circuit according to the embodiment;

FIG. 14 is a block diagram illustrating an example of a configuration of a main part of a concealment circuit according to a modification.

FIG. 15 is a time chart for explaining an operation of a concealment circuit according to a modification.

FIG. 16 is a diagram for explaining sub-sampling.

FIG. 17 is a schematic diagram schematically showing a modification using subsampling.

FIG. 18 is a block diagram illustrating an example of a configuration of a concealment circuit according to the related art.

FIG. 19 is a time chart for explaining modification of image data obtained by slow reproduction.

[Explanation of symbols]

41 ECC decoder, 43 BRR decoder, 45 concealment circuit, 102 concealment processing unit, 103 frame detection unit, 105
Field memory A, 106 ... Field memory B, 107, 110 ... Selector

Claims (5)

[Claims] 1. A digital video signal processing apparatus for correcting a digital video signal having an error exceeding an error correction capability by an error correction code, comprising: a first memory for storing a first field of an input video signal; A second memory for storing a second field of the input video signal; a detecting means for detecting the first and second fields of the input video signal; Selecting means for selecting, from the second memory, a memory corresponding to a field of the input video signal; and selecting the input video signal, and selecting the memory from the first memory and the second memory. Using the video signal read from the memory on the selected side, the error flag corresponding to the input video signal is used. Digital video signal processing apparatus characterized by having a concealed processing means for modification of the pixels indicated to be error based on. 2. A digital video signal processing apparatus for correcting a digital video signal having an error exceeding an error correction capability by an error correction code, comprising: a first memory for storing a first field of the video signal; A second memory for storing a second field of the video signal; a detecting means for detecting the first and second fields of the input video signal; a first memory and the second memory based on a detection result by the detecting means; Selecting means for selecting a memory on the side corresponding to the field of the input video signal from among the memories, and selecting the input video signal, and selecting the memory from among the first memory and the second memory. Using the video signal read from the memory on the other side, an error is generated based on the error flag corresponding to the input video signal. Concealment processing means for modifying a pixel indicated to be a video signal, wherein the video signal stored in the first memory and the second memory is subjected to the concealment processing by the concealment processing means. A digital video signal processing device characterized by being a video signal. 3. The digital video signal processing device according to claim 1, wherein the concealment processing means detects a motion of the input video signal, and as a result of the motion detection, it is determined that there is a motion. In such a case, the pixel is modified by performing interpolation using pixel data in the same field. If the pixel is stationary, the data is replaced with pixel data at the same position one frame before. A digital video signal processing device, characterized in that the pixel is modified by the above method. 4. A digital video signal reproducing apparatus for reproducing a digital video signal stored in a storage medium, wherein an error of the video signal is determined based on an error correction code added to the video signal reproduced from the recording medium. Error correcting means for performing correction; decompression encoding applied to the video signal error-corrected by the error correcting means; compression decoding means; and the compression encoding decompressed by the compression decoding means. Concealing means for modifying the video signal when the video signal has an error exceeding the error correction capability of the error correction code, wherein the concealing means comprises an input video input to the concealing means. A first memory for storing a first field of the signal, and a second memory for storing the second field of the input video signal A second memory, a detecting means for detecting first and second fields of the input video signal, and, based on a detection result by the detecting means, of the first memory and the second memory, Selecting means for selecting a memory on the side that matches the field of the video signal; reading the input video signal from the memory selected by the selecting means from the first memory and the second memory; And a concealing means for correcting a pixel indicating an error based on the error flag corresponding to the input video signal using the video signal. Video signal playback device. 5. A digital video signal reproducing apparatus for reproducing a digital video signal stored in a storage medium, wherein an error of the video signal is determined based on an error correction code added to the video signal reproduced from the recording medium. Error correcting means for performing correction; decompression encoding applied to the video signal error-corrected by the error correcting means; compression decoding means; and the compression encoding decompressed by the compression decoding means. Concealing means for modifying the digital video signal when the digital video signal has an error exceeding the error correction capability of the error correction code, the concealing means comprising: A first memory for storing; a second memory for storing a second field of the video signal; Detecting means for detecting the first and second fields of the input video signal input to the concealing means; and detecting the input video signal from the first memory and the second memory based on the detection result by the detecting means. Selecting means for selecting a memory on the side that matches the field of the signal; reading the input video signal; and reading from the memory on the side selected by the selecting means among the first memory and the second memory Concealment processing means for modifying a pixel indicating an error based on an error flag corresponding to the input video signal using a video signal, and concealing processing means for modifying the first memory and the second memory. The stored video signal is a digital signal processed as the modified video signal by the concealing processing means. A digital video signal reproducing device using the device.