JPH05144190A - Recorder for digital image signal - Google Patents

Abstract

PURPOSE:To simplify the timing control by setting synch block length of each of video data, audio data and a sub-code to an integer ratio. CONSTITUTION:One synch block length of video data, audio data and a sub-code it taken as 90, 45 and 30 bytes, respectively, and set to an integer ratio of 6:3:2. In a synch block of each data, 2 bytes of a block synchronizing signal and 4 bytes of an ID signal of the same length are contained. Also, an error correction code is a product code using matrix-like array data. That is, encoding of an inner code is executed with regard to data contained in each row, parities of 8 and 6 are generated to Figures A, B, respectively, and encoding of an outer code is executed with regard to data contained in each column, and parities of 3 and 4 bytes are generated to the Figures A, B, respectively. As for a Figure C, error correction encoding is executed by only the inner code, a parity of 8 bytes is generated, and 4 bytes each are inserted into two digits.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital image signal recording apparatus for recording digital data such as digital video signals, digital audio signals and control subcodes on a magnetic tape, and more particularly to the structure of these data. ..

[0002]

2. Description of the Related Art Recently, a digital VT for digitizing a color video signal and recording it on a recording medium such as a magnetic tape.
As R, a component type digital VTR of the D1 format and a composite type digital VTR of the D2 format for broadcasting stations have been put to practical use.

The former D1 format digital VT
R represents the luminance signal and the first and second color difference signals 13.
The signal is A / D converted at a sampling frequency of 5 MHz and 6.75 MHz and then subjected to predetermined signal processing and recorded on the tape. The ratio of the sampling frequencies of these component components is 4: 2: 2. It is also called the 2: 2: 2 method.

The latter D2 format digital VT
R is configured to sample a composite color video signal with a signal having a frequency four times the frequency fsc of the color subcarrier signal, perform A / D conversion, perform predetermined signal processing, and then record on a magnetic tape. There is.

Since both of these digital VTRs are designed on the assumption that they will be used for broadcasting stations, the image quality is given the highest priority, and one sample is A / D in 8 bits, for example.
The converted digital color video signal is recorded without being substantially compressed. In the D1 format digital VTR, a segment system using 10 tracks per field in the NTSC system and 12 tracks in the PAL system is adopted as a track pattern. The segment method is adopted
It is based on the fact that it is difficult to record a large amount of recording data on one track, and by shortening the track length, the influence of defective track linearity can be reduced even when the track pitch is narrow.

Further, in the digital VTR, in addition to the digital image signal, it is necessary to record a digital audio signal, a pilot signal for tracking, etc. on the track. In the D1 format digital VTR described above, audio data is recorded in the center of the track, and a time code and a control signal for tracking are recorded in the longitudinal direction of the tape. In D2 format,
Audio data is recorded at both ends of the track, and a time code and a control signal for tracking are recorded in the longitudinal direction of the tape as in the D1 format.

Since an error occurs during recording / reproduction, digital image signals, digital audio signals,
The subcode is encoded with an error correction code. As the error correction code, there is known a product code in which a row (horizontal) direction and a column (vertical) direction of a matrix-shaped data array are coded by separate error correction codes. The product code has high error correction capability because each data symbol belongs to two error correction code sequences.

[0008]

In these conventional digital VTRs, in order to record / reproduce a tracking signal or a time code, a fixed head must be arranged in the mechanism of the VTR. There is a possibility that the tape becomes complicated and the reliability of the tape path is impaired. Therefore, it is desirable to omit the fixed head by recording a tracking signal and additional data for control in the track.

Since the data recorded in these one tracks have different amounts of information, the size of one unit of the product code is different when encoded by the product code. Product code 1
Since the block sync signal is added to the row data and the parity to form the sync block, the length of the sync block also differs between these data. Therefore, there is a problem that timing control during recording and reproduction becomes complicated.

Therefore, an object of the present invention is to provide a digital image signal recording apparatus which can achieve simplification of timing control during recording and reproduction. Another object of the present invention is to provide a digital image signal recording apparatus capable of simplifying an encoder and a decoder when encoding each of these data by a product code.

[0011]

The invention according to claim 1 is
In a digital image signal recording apparatus, an input digital image signal is compression-encoded and the encoded digital image signal is recorded on a magnetic tape by a magnetic head (13A, 13B) mounted on a rotating drum (46). A circuit for error-correcting and encoding an encoded digital image signal, digital audio signal, and additional data for control by a product code, and output data of the error-correction encoding circuit, for each line of the product code. , And a circuit for generating a data sequence having a sync block configuration by adding a block sync signal, and each sync block length of a digital image signal, a digital audio signal, and additional data is represented by an integer ratio. A digital image signal recording apparatus characterized by being set A.

According to a second aspect of the present invention, there are provided a circuit for error-correcting and encoding the encoded digital image signal, digital audio signal, and control additional data by a product code, and output data of the error-correction encoding circuit. And a recording processing circuit including a circuit that generates a data sequence having a sync block configuration by adding a block synchronization signal to each row of the product code,
The data after the recording processing of the digital image signal, digital audio signal and additional data is recorded in separate sections of the magnetic tape track, respectively, and is an integer multiple of the sync block length of one of the digital image signal, digital audio signal and additional data. The recording apparatus for digital image signals is characterized in that the section length is defined by. The invention according to claim 3 is a digital image signal,
A digital image signal recording apparatus characterized in that a section length and a non-data section length between sections are defined by an integral multiple of a sync block length of either the digital audio signal or the additional data.

According to a fourth aspect of the present invention, there is provided a circuit for error-correcting and encoding the encoded digital image signal, digital audio signal and additional data for control by a product code, and output data of the error-correction encoding circuit. And a recording processing circuit including a circuit that generates a data sequence having a sync block configuration by adding a block synchronization signal to each row of the product code,
The product code is set such that the number of parities generated by a plurality of rows of the additional data and the number of parities generated by one row of the digital image signal are set to be equal to each other. Is.

According to a fifth aspect of the present invention, there is provided a circuit for error-correcting and encoding the encoded digital image signal, digital audio signal and additional data for control by a product code, and output data of the error-correction encoding circuit. Therefore, a recording processing circuit including a circuit that generates a data sequence having a sync block configuration by adding a block synchronization signal and an ID signal to each row of data of a product code is provided. The digital image signal recording apparatus is characterized in that the length of the block synchronizing signal and the length of the ID signal are set to be equal between the sync blocks of the digital audio signal and the additional data. ..

[0015]

A plurality of pieces of data are encoded by the product code.
A sync block is formed by adding a block synchronization signal and an ID signal to the data of each row of the product code. The size of the product code differs depending on the data, and the length of the sync block also differs, but the ratio of the sync block lengths of these data is set to an integer ratio. Therefore,
Processing such as timing control can be simplified. Also, 1
Since the length of the data section and the non-data section in the track is an integral multiple of one sync block length, the circuit can be partially shared for timing control, recording processing, reproduction processing and the like.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below. This description will be given in the following order. a. Signal processing unit b. Channel encoder and channel decoder c. Head tape system d. Track format e. Data structure f. Audio signal interleaving and error correction g. Specification of ID data and post-recording area

A. Signal Processing Unit First, the signal processing unit of the digital VTR in this embodiment will be described. FIG. 1 shows the configuration of the recording side as a whole. Input terminals 1Y, 1U, and 1V, for example, have three primary color signals R from a color video camera,
A digital luminance signal Y formed from G and B and digital color difference signals U and V are supplied. In this case, the clock rate of each signal is the same as the frequency of each component signal of the D1 format described above. That is, the respective sampling frequencies are 13.5 MHz and 6.75 MHz, and the number of bits per sample is 8 bits. The data amount in the blanking period of this signal is removed and the data amount is compressed by the effective information extraction circuit 2 which extracts only the information in the effective area.

The luminance signal Y in the output of the effective information extraction circuit 2 is supplied to the frequency conversion circuit 3 and the sampling frequency is converted from 13.5 MHz to 3/4 thereof. As the frequency conversion circuit 3, for example, a thinning filter is used so that aliasing distortion does not occur. The output signal of the frequency conversion circuit 3 is supplied to the blocking circuit 5, and the order of luminance data is converted into the order of blocks.
The block forming circuit 5 is provided for the block encoding circuit 8 provided in the subsequent stage.

FIG. 3 shows the structure of a block as a unit of coding. As block encoding, DCT (Discrete Cosin)
e Transform), ADRC (encoding adapted to the dynamic range), etc. can be adopted, and one block has a size of (8 × 8) pixels as shown in FIG. In FIG. 3, a solid line indicates an odd field line, and a broken line indicates an even field line.

Of the outputs of the effective information extraction circuit 2,
The two color difference signals U and V are supplied to the sub-sampling and sub-line circuit 4, the sampling frequency is converted from 6.75 MHz to half thereof, and then two digital color difference signals are alternately selected for each line, and one channel is selected. Is combined with the data of. Therefore, the line-sequentialized digital color difference signal is obtained from the sub-sampling and sub-line circuit 4. FIG. 4 shows the pixel configuration of the signals sub-sampled and sub-lined by the circuit 4. In FIG. 4, ◯ indicates a sampling pixel of the first color difference signal U, Δ indicates a sampling pixel of the second color difference signal V, and x indicates the position of the pixel thinned by the sub-sample.

The line-sequential output signal of the sub-sampling and sub-line circuit 4 is supplied to the blocking circuit 6. Similar to the blocking circuit 5, the blocking circuit 6 converts color difference data in the scanning order of the television signal into data in the block order. Similar to the blocking circuit 5, the blocking circuit 6 converts color difference data into a block structure of (8 × 8) pixels. The output signals of the blocking circuits 5 and 6 are supplied to the synthesizing circuit 7.

In the synthesizing circuit 7, the luminance signal and chrominance signal converted in the order of blocks are converted into 1-channel data, and the output signal of the synthesizing circuit 7 is supplied to the block coding circuit 8 employing DCT, for example. .. The output signal of the block encoding circuit 8 is supplied to the framing circuit 9 and converted into frame structure data. This framing circuit 9
Then, the image system clock and the recording system clock are changed.

A PCM audio signal is supplied from the input terminal 1A and is supplied to the audio encoding circuit 15. This audio encoding circuit 15 uses the DPCM
The data amount of audio data is compressed by. The audio encoding circuit 15 interleaves in response to a mode signal from the input terminal 15a designating the user recording mode and the soft tape mode, as described later. The output data of the audio encoding circuit 15 is supplied to the parity generation circuit 16, and the parity of the product code which is an error correction code is generated. Audio data and parity are supplied to the mixing circuit 14.

As the recording area of the audio data, two areas of audio 1 and audio 2 are prepared as described later. The audio encoding circuit 15 and the parity generation circuit 16 generate data to be recorded in these two areas. Further, when performing post-recording of the PCM audio signal, one of the audio 1 and audio 2 areas is used. Post-recording is possible in the user recording mode described above, and post-recording is prohibited in the soft tape mode. The output data of the audio encoding circuit 15 may be supplied to the framing circuit 9 to record the audio data in the recording section of the block-encoded image data.

The output signal of the framing circuit 9 is supplied to the error correction code parity generation circuit 10 to generate the product code parity. The output signal of the parity generation circuit 10 is supplied to the mixing circuit 14. The output signals of the parity generation circuits 16 and 17 are supplied to the mixing circuit 14, respectively. The parity generation circuit 17 performs error correction coding processing on the subcode from the input terminal 1S to generate parity. For the subcode, only the inner code of the product code having the inner code and the outer code as the error correction code is used.

This subcode is supplied from a subcode generation circuit denoted by 111. Further, 112 is an ID signal generation circuit, 113 is a synchronization signal generation circuit, and 11
Reference numeral 4 is a parity generation circuit, and 115 is a timing generation circuit. The subcode can be generated, for example, by a user's key operation.

In the mixing circuit 14, the image data, the audio data, and the data in which the subcode is inserted are formed at predetermined positions on one track, which will be described later. The output signal of the mixing circuit 14 is supplied to the channel encoder 11, and channel coding is performed so as to reduce the low frequency part of the recording data. Channel encoder 11
Is supplied to the mixing circuit 18. Mixing circuit 18
Is supplied with a pilot signal for ATF (automatic track following control). This pilot signal is a low frequency signal that can be frequency separated from the recorded data. The output signal of the mixing circuit 18 passes through the recording amplifiers 12A and 12B and the rotary transformer (not shown) to the magnetic heads 13A and 13B.
And recorded on a magnetic tape.

Next, the structure on the reproducing side will be described with reference to FIG. In FIG. 2, reproduction data from the magnetic heads 13A and 13B are supplied to the channel decoder 22 and the ATF circuit 34 via a rotary transformer (not shown) and reproduction amplifiers 21A and 21B, respectively. The channel decoder 22 demodulates the channel coding, and the output signal of the channel decoder 22 is supplied to the TBC circuit (time axis correction circuit) 23. In this TBC circuit 23, the time-axis fluctuation component of the reproduction signal is removed. The ATF circuit 34 generates a tracking error signal from the level of the beat component of the reproduced pilot signal, and the tracking error signal is supplied to, for example, the phase servo circuit of the capstan servo. The operation of such an ATF is basically the same as that adopted in the 8 mm VTR.

The reproduced data from the TBC circuit 23 is ECC
It is supplied to the circuits 24, 37 and 39, and the error correction using the product code and the error correction for the error that cannot be corrected are performed. The ECC circuit 24 performs error correction and error correction on the image data, and the ECC circuit 37
Performs error correction and error correction of the audio data recorded in the audio section (audio 1 and 2), and the ECC circuit 39 performs error correction of the subcode. The output signal of the ECC circuit 37 is supplied to the audio decoding circuit 38. The reproduced subcode is taken out from the output terminal 33S of the ECC circuit 39. Although not shown, this subcode is supplied to a system controller for controlling the operation of the entire VTR. ECC circuit 24
Is supplied to the frame decomposition circuit 25.

The frame decomposing circuit 25 separates the respective components of the block coded data of the image data, and also changes the clock of the recording system to the clock of the image system. The respective data separated by the frame decomposing circuit 25 are supplied to the block decoding circuit 26, and the restored data corresponding to the original data is decoded for each block. Also, decoded data corresponding to the data recorded in the audio 1 and 2 sections can be obtained.

The audio decoding circuit 38 decodes the compression coding of the audio signal. The decoded audio data is supplied to the synthesis circuit 36. The synthesizing circuit 36 synthesizes the decoded data of the audios 1 and 2 in response to the mode designation signal from the input terminal 35.
This mode designation signal is a mode ID separated by the frame decomposition circuit 25 or the audio decoding circuit 38.
Can be formed from signals. In the soft tape mode, a reproduced audio signal of two channels is obtained by synthesizing reproduced audio signals from the audio 1 and audio 2 sections. In the user recording mode, 2-channel audio signals are reproduced from each of these sections.

The decoded data of the image data from the block decoding circuit 26 is supplied to the distribution circuit 27. The distribution circuit 27 separates the decoded data into a luminance signal and a color difference signal. The luminance signal and the color difference signal are supplied to the block decomposition circuits 28 and 29, respectively. The block decomposing circuits 28 and 29 convert the decoded data in the order of blocks into the order of raster scanning, contrary to the blocking circuits 5 and 6 on the transmitting side.

The decoded luminance signal from the block decomposition circuit 28 is supplied to the interpolation filter 30. In the interpolation filter 30, the sampling rate of the luminance signal is 3 fs to 4 fs.
(4fs = 13.5 MHz). The digital luminance signal Y from the interpolation filter 30 is taken out to the output terminal 33Y.

On the other hand, the digital color difference signal from the block decomposition circuit 29 is supplied to the distribution circuit 31, and the line-sequential digital color difference signals U and V are separated into the digital color difference signals U and V, respectively. The digital color difference signals U and V from the distribution circuit 31 are supplied to the interpolation circuit 32 and are interpolated. The interpolation circuit 32 interpolates the data of the thinned lines and pixels using the restored pixel data, and the sampling rate from the interpolation circuit 32 is 4
The digital color difference signals U and V of fs are obtained and taken out to the output terminals 33U and 33V, respectively.

B. Channel Encoder and Channel Decoder Next, the channel encoder 11 and the channel decoder 22 shown in FIG. 1 will be described. The details of these circuits are disclosed in Japanese Patent Application No. 1-143491 filed by the applicant of the present application, and a schematic configuration thereof will be described with reference to FIGS. 5 and 6.

In FIG. 5, reference numeral 41 denotes an adaptive scramble circuit to which the output of the parity generation circuit 10 of FIG. 1 is supplied, and a plurality of M-sequence scramble circuits are prepared. And an M series that can obtain an output with a small DC component. Reference numeral 42 denotes a precoder for the partial response class 4 detection method, which is used to perform arithmetic processing of 1 / 1-D ² (D is a unit delay circuit). This precoder output is passed through recording amplifiers 12A and 12B to the magnetic head 13
Recording and reproduction are performed by A and 13B, and reproduction output is amplified by reproduction amplifiers 21A and 21B.

FIG. 6 showing the structure of the channel decoder 22.
In the figure, reference numeral 43 denotes an arithmetic processing circuit on the reproducing side of the partial response class 4, and 1 + D arithmetic is performed on the outputs of the reproducing amplifiers 21A and 21B. Reference numeral 44 denotes a so-called Viterbi decoding circuit, which decodes data that is resistant to noise by performing an operation on the output of the operation processing circuit 43 by using the data correlativity and certainty. The output of the Viterbi decoding circuit 44 is supplied to the descramble circuit 45, the data rearranged by the scrambling process on the recording side is returned to the original series, and the original data is restored. By the Viterbi decoding circuit 44 used in this embodiment,
Compared to the case of decoding bit by bit, 3 in converted C / N conversion
An improvement in dB is obtained.

C. Tape Head System The magnetic heads 13A and 13B described above are attached to the rotary drum 46 at a facing interval of 180 °, as shown in FIG. 7A. Alternatively, as shown in FIG. 7B, the magnetic heads 13A and 13B are attached to the drum 46 in an integrated structure. 180 around the drum 46
Magnetic tape (not shown) is wound diagonally at a winding angle slightly larger or slightly smaller than °. Figure 7
In the head arrangement shown in A, the magnetic heads 13A and 13B substantially alternately contact the magnetic tape, and in the head arrangement shown in FIG. 7B, the magnetic heads 13A and 13B simultaneously scan the magnetic tape.

The extension directions (called azimuth angles) of the gaps of the magnetic heads 13A and 13B are made different. For example, as shown in FIG. 8, the magnetic head 13A
And 13B, the azimuth angle of ± 20 ° (-α, β) is set. Due to this difference in azimuth angle, a recording pattern as shown in FIG. 9 is formed on the magnetic tape. As can be seen from FIG. 9, the adjacent tracks TA and TB formed on the magnetic tape are formed by the magnetic heads 13A and 13B having different azimuth angles, respectively. Therefore, during reproduction, the amount of crosstalk between adjacent tracks can be reduced due to azimuth loss.

D. Track Format The track pattern in the above-described embodiment will be described. FIG. 10 shows an array of data recorded on one track. In the figure, the left end of the track is the head entry side, and the right end thereof is the head separation side. Further, no data is recorded in the margin and the IBG (inter block gap), which are the shaded areas. In the preamble section (preamble or postamble) added to both ends of the data recording section, for example, a pulse signal having a frequency equal to the bit frequency of the data is recorded, and a PLL for bit clock extraction provided on the reproduction side is provided. It is easy to lock.

Margins are provided at both ends of one track, and pilot signals ATF1 and ATF2 for ATF are recorded adjacent to these margins. An audio signal recording section (audio 1), a video signal recording section, an audio signal recording section (audio 2), a subcode recording section, a pilot signal AT in the head scanning direction from the recording section of the pilot signal ATF1.
The recording section of F2 is provided in order. The effective area of one track has a length of 16041 bytes. At the end of the track, the contact between the head and tape is unstable, so
The pilot signals ATF1 and ATF2 are recorded. Further, at the time of high-speed reproduction in which the speed of the magnetic tape is higher than that at the time of recording, the end on the head separation side is more stable in contact than the end on the head entry side. Therefore,
The recording section of the sub-code is on the side close to the end on the head separation side.

The recording data consists of a number of sync blocks. In the sync block, the sync block sync signal is located at the head of the sync block, followed by the ID signal indicating the block identification and the block position in the screen, and the parity of the data or error correction code is located after that. Is. The length of the sync block is different among the video data, the audio data, and the subcode, reflecting the difference in the amount of information in one track. In this example, AT
Each recording section and non-recording section of the effective area in one track other than the section of the F pilot signal (ATF1 and ATF2) are defined based on the length of the audio sync block. Audio 1 and 2 as shown
Section is selected as (14 × audio sync block), video section is selected as (288 × audio sync block), and subcode section is selected as (4 × audio sync block). Further, the length of the amble section and the IBG are defined as shown in the figure.

As described above, since the recording section and the non-recording section of each data are defined on the basis of the length of the audio sync block, for the timing control for defining each section during recording and reproduction. The configuration of can be simplified.

E. Data Structure FIG. 11A shows a data structure of recorded video data. One sync block length is 90 bytes, and the block sync signal (2 bytes) is located at the beginning of the sync block.
ID data (4 bytes), data (76 bytes), and parity (8 bytes) are located. The error correction code of the video data is a product code that uses data in a (76 × 45) matrix array. That is, with respect to the 76-byte data included in each row, the inner code is encoded, the 8-byte parity (referred to as C1 parity) is generated, and the 45-byte data included in each column is
The outer code is encoded to generate a 3-byte parity (referred to as C2 parity). As the inner code and the outer code, specifically, Reed-Solomon code can be used. The amount of data shown in FIG. 11A is 1/3 of the amount of data in one track, and the same product code structure as that shown in FIG. 11A is recorded three times in a video section in one track.

FIG. 11B shows the data structure of audio data. One sync block length is 45 bytes, a block synchronization signal (2 bytes) is located at the beginning thereof, and thereafter, ID data (4 bytes), data (33 bytes), and parity (6 bytes) are sequentially located. Like video data, audio data is also subjected to error correction coding using a product code. That is, (33 × 1
0) 3 included in each row of the matrix array data
Inner code encoding is performed on 3 bytes of data,
6 bytes of C1 parity is generated, 1 included in each column
Outer code encoding is performed on 0-byte data,
4-byte C2 parity is generated.

The product code of FIG. 11B is applied to data recorded in the audio section (audio 1 or audio 2) per channel of audio data. In the user recording mode, one sample has 8 bits, and in the soft tape mode, one sample has 16 bits. As described below, in soft tape mode,
In each section of audio 1 and audio 2,
One channel of L or R is recorded. The 1-channel data included in this recording section (audio 1 and audio 2) constitutes the product code of FIG. 11B. Audio 1 or Audio 2 in user recording mode
Data of 2 channels of L and R are recorded in the section. In this mode, the 2-channel data is shown in FIG.
Construct the product code of B. Then, in the user recording mode, the data of one channel is recorded in the first half portion of one audio section, and the data of the other channel is recorded in the latter half portion thereof.

FIG. 11C shows the data structure of the subcode recorded in the subcode section of one track. One sync block length is 30 bytes, and the block synchronization signal (2 bytes) is located at the beginning of the sync block, followed by ID data (4 bytes), data (20 bytes), and parity (4 bytes). 2 adjacent to subcode
The error correction coding is performed only on the inner code for the 40-byte data included in the row. That is, (20
For the 40-byte data included in every two rows of the matrix-shaped data in (6), the inner code is encoded, and 8-byte C1 parity is generated. These 8 bytes are 4 bytes in 2 rows. It is inserted as C1 parity.

The inner code for the sub-code produces a parity of 8 bytes and is therefore equal to the number of parity of the inner code for the video data. Therefore, the encoder for generating the parity of the inner code or the hardware for decoding the inner code can be shared. The reason why the data of one line is set to 20 bytes instead of 40 bytes is to shorten the sync block length. Even during high-speed playback,
The subcode is data necessary for detecting the tape position and the like. The sync block is the smallest unit that is treated as valid data in the reproduced data.
The shorter the sync block length, the more effective subcodes can be obtained.

As described above, the sync block length of each of the video data, the audio data and the subcode is set to an integer ratio of (90: 45: 30 = 6: 3: 2). Therefore, even if one track includes sync blocks having different lengths, timing control during data processing can be simplified. Further, the lengths of the block synchronization signal (2 bytes) and the ID signal (4 bytes) are common between these sync blocks,
Further, as will be described later, since the data structure of the ID signal is common, it is possible to share the circuit structure for generating or processing these.

F. Audio signal interleaving and error correction 525 line / 60 field system (eg NT
In the (SC method), one frame of recording data is divided and recorded in ten (N = 5) tracks T0 to T9 as shown in FIG. As described above, in this example, sections (audio 1 and 2) in which audio data can be independently recorded are provided in one track. As an example, a PCM audio signal having a length of 1 frame period (sampling frequency of 48 kHz, 16-bit linear quantization, 2 channels) can be recorded in the audio 1 and audio 2 sections.

Interleave processing is performed for 2N tracks for each PCM audio signal in one frame period. FIG. 12 represents the L (left) channel PCM audio signal in one frame period in an analog manner. The PCM audio signal sequence of this one frame period is (N =
It is divided into 5) sections. A sequence including an even-numbered sample in the PCM audio signal sequence included in the first section is represented as L0, and a sequence including the odd-numbered sample is L1.
Express. Similarly, regarding the PCM audio signal sequences included in the second, third, fourth, and fifth sections, respectively, sequences L2, L4, L6, which include even-numbered samples,
L8 and sequences L3, L5, L including odd-numbered samples
7, L9 is formed. Also from the R (right) channel PCM audio signal in one frame period, as in the case of the L channel, PCM audio signal sequences R0 to R5 in five sections
R9 is formed.

These PCM audio signal sequences are interleaved, error-correction coded as described above, and recorded in the audio 1 and audio 2 sections. PCM
As a recording mode of the audio signal, a soft tape mode used when a professional company such as a movie company produces a soft tape, and a user recording mode in which the user records by himself are prepared. In soft tape mode, P
One sample of CM audio signal is 16 bits,
In the user recording mode, one sample is 8 bits. Therefore, the data amount of the PCM audio signal in the user recording mode is half that in the soft tape mode. Not only the number of bits but also the sampling frequency may be different in the two modes, and as a result, the data amount may have the same relationship.

FIG. 14A shows a soft tape mode PCM.
7 shows an interleave process of an audio signal. The first group of the first half of the tracks T0 to T9 (tracks T0 to T
4) in the audio 2 section, (L1, L3, L5, L
7, L9) is recorded, and in the section of the audio 1,
(R0, R2, R4, R6, R8) is recorded. (R1, R3, R5, R7, R9) is recorded in the audio 2 section of tracks T5 to T9, which is the second group in the latter half, and (L0, L2, L9) is recorded in the audio 1 section.
4, L6, L8) are recorded.

FIG. 14B shows PCM signal interleaving in the user recording mode. In the user recording mode, since the data amount is half that in the soft tape mode as described above, the PCM audio signal is recorded in each section of audio 1 and audio 2 in the same format as the soft tape mode. it can. Audio 1
For example, the audio section 1 of the track T0
(L1, R0) is recorded on the track, and (L3, R2) (L5, R4) (L7, R6) are recorded on the tracks T1 to T9.
(L9, R8) (R1, L0) (R3, R2) (R5,
L4) (R7, L6) (R9, R8) are recorded respectively. In this case, the section of audio 1 is divided into the first half and the second half, and the first half of the data (L
, L3, ..., R9), and the lower half data (R0, R2, ..., L8) is recorded in the latter half.

Another example of interleaving in the user recording mode is shown in FIG. The example of FIG. 15 is similar to that of FIG. 14B.
L2 and L3, R2 and R3, L6 and L7, R
The recording tracks of 6 and R7 are exchanged. The interleave of FIG. 15 can be similarly applied to the soft tape mode. Also in the interleave of FIG. 15, one and the other of a pair of data sequences obtained by dividing a PCM audio signal of one frame into N are separated into a track included in the first group and a track included in the second group. Will be recorded.

In a system of 625 lines / 50 fields (for example, PAL system), one frame of recording data is (2N = 12) tracks T0 to T0 as shown in FIG.
It is divided into T11 and recorded. Therefore, the PCM audio signal of one frame period is divided into (N = 6) sections over the 12 tracks, and the PC of each section is divided.
Interleave processing is performed in units of M audio signals.

FIG. 16 shows the PCM audio signal of the L (left) channel in one frame period in an analog manner. This PCM audio signal sequence of one frame period is divided into six sections. Sequences L0 and L in which the PCM audio signal sequence included in each section includes even-numbered samples
, L10 and sequences L1, L3, ..., L11 including odd-numbered samples. From the R (right) channel PCM audio signal in one frame period, a sequence of R0 to R11 is formed as in the case of the L channel.

Then, as shown in FIG. 18A, in the soft tape mode, two audio recording sections in a track are used so that the even-numbered series and the odd-numbered series of each channel extend over the tracks T0 to T11. Are interleaved. Similar to FIG. 14A, this interleaving makes the even / odd interleaving and the audio recording section different between the tracks T0 to T5 and the tracks T6 to T11. Further, in the user recording mode, as shown in FIG. 18B, similar interleaving is performed by using the first half part and the latter half part obtained by dividing the audio 1 and 2 sections.

If an error occurs in the reproduced data due to scratches on the tape, dust on the tape, fingerprints, etc.,
When this error exceeds the correctable level, error correction is performed on the error data to reduce the effect of the error. The interleave processing described above is excellent in this error correction ability.

First, the error correction capability of the soft tape mode will be described with reference to FIG. As shown in FIG. 19A, it is assumed that an error (represented by a shaded area) occurs in both the width and the length of the tape, and the audio data can be reproduced only from the audio 2 section. In this case, as is apparent from FIG. 14A, odd-numbered sequences (L1, L3, L5, L7, L9) of the L channel and R
Odd-numbered series of channels (R1, R3, R5, R
7, R9) is obtained as error-free data. These odd numbered samples can be used to fix the even numbered error samples. As a modification method, for example, a method of using an average value of samples before and after the error sample instead of the error sample can be adopted.

Next, as shown by the hatched area in FIG. 19B,
Audio 1 and audio 2 of tracks T0 to T4
If both are errors, tracks T5 to T9
From (R1, R3, R5, R7, R9) (L0, L2,
L4, L6, L8) can be obtained as error-free data. Therefore, for the R channel, (R
0, R2, R4, R6, R8) series can be interpolated with an average value, and for the L channel, (L1, L3, L5, L
7, L9) series can be interpolated with an average value.

Even in the user recording mode, high retouching ability is exhibited as in the soft tape mode. In the first record,
When the same data is recorded in the audios 1 and 2, it is possible to strongly perform error correction and error correction by selecting non-error data from both sections. However, in this example, since the post-recording is allowed, there is no guarantee that both data are the same. In such a case, error correction is performed for each of audio 1 and audio 2.

As shown by the hatched area in FIG. 20A, when the tape running system is damaged in the longitudinal direction of the tape, the reproduced data in the first half of the audio 1 near the tape edge becomes an error. That is, the PC in the lower half of FIG. 14B
M audio signals (R0, R2, ..., L6, L
8) is error data, and the upper half (L1,
L3, ..., R7, R9) are correct data.
In this case, the error data can be corrected by the mean value interpolation using correct data.

Next, as shown in FIG. 20B, in the user recording mode, the audio PCs of tracks T0 to T4 are recorded.
When the M signal becomes error data, the error data can be corrected by the correct audio PCM signal from the audio 1 or 2 of the remaining tracks T5 to T9.

When data is recorded by two magnetic heads as in this embodiment, one magnetic head may clog. When one of the magnetic heads clogs, as shown in FIG. 21, tracks T0, T2, T
Correct reproduction data cannot be obtained from 4, T6 and T8. At the time of this head clog, in both the soft tape mode and the user recording mode, the odd-numbered series of the L channel and the even-numbered series of the R channel become error data. These error data can be interpolated as correct reproduction data from the tracks T1, T3, T5, T7, T9.

G. Configuration of ID Data and Definition of Post-Recording Area An example of the ID signal inserted for each sync block will be described with reference to FIG. This ID signal is a video,
It is a common format between audio and subcode. ID signal is 1 byte ID signal ID0, ID
It consists of 1, ID2, and ID3.

The ID signal ID0 is a 1-bit frame I
D (FRID), 2-bit data ID, 2-bit broadcasting system ID, 2-bit post-record ID, and 1-bit mode ID. The frame ID is inverted every frame. The data ID identifies the type of data of the sync block (video, audio 1, audio 2, or subcode). Broadcast format ID is NT (5
25/60 system) and PAL (625/50 system) 1 bit for distinguishing, and HD (high resolution)
And 1 bit for identifying SD (standard resolution). The post-record ID identifies a record and a record that is not. Non-post-recording means both recording on an unused tape and recording in which the entire track is rewritten by overwriting. During non-after-recording, pilot signals for tracking control at both ends of the track are always rewritten. Mode I
D identifies the soft tape mode and the user recording mode. Post-recording can be applied to any of video, audio, and subcode.

ID1 consists of 6-bit track number data and 2-bit spare area. The track number data indicates the track number given to 2N tracks. Considering the case of recording an image signal having an extremely large amount of information such as an HD signal, the track number data is
A relatively large number of bits (6 bits) is assigned. A spare area is provided to record data for other IDs in the future.

ID2 is an 8-bit sync block number. A sync block number is added to each sync block of each data in one track. ID
3 is a parity for error detection and correction of the above-mentioned ID0, ID1, and ID2.

In the case of post-recording, the recording area needs to be defined with high accuracy. If the recording area deviates from the correct one, other recorded data will be erased. To avoid this problem, it is not preferable to lengthen the non-recording section such as IBG because the recording density is lowered. FIG. 23 shows an example of a configuration for generating a control pulse for defining an after-recording area using the above-mentioned after-recording ID.

As a method of defining the after-recording area, here, the end of the previous recording section is detected, and the position of a predetermined number of sync blocks is set as the start position of the after-recording area from the detection, and the position of the after-recording area is set according to the type of the after-recording data. It defines the end position of the post-recording area. For example, when post-recording video data, first, the end of the section of audio 1, more accurately, the end position of the subsequent postamble is detected. Next, the number of sync blocks is counted from the reproduced block synchronization signal to define the position of the start end of the preamble in the video section. Then, the number of sync blocks is counted to define the end position of the postamble in the video section. The video section and the amble section defined in this way are the post-recording area.

As described above, when the block synchronizing signal of the previous section recorded is counted to define the post-recording area, if the previous section is post-recorded, its position is generally inaccurate. Is. Therefore, the post-record ID prevents the block sync signal in the post-recorded data from being used. If all the data in the track located before the post-recording area is post-recorded, the detection pulse of the recording section ATF1 of the pilot signal at the beginning of the track is used. Since the pilot signal has a predetermined frequency, it is possible to detect the pilot signal even if it has no sync block structure. Audio 1
Similarly, in the post-recording, the detection pulse of the pilot signal is used.

The reproduced data ID and sync number are supplied to the decoder 51 in FIG. A data ID and a sync number are supplied to the decoder 51,
The decoder 51 generates a preset pulse in the last sync block of the recording section located before the post-recording area. Since the last sync block number differs depending on the type of data, the data ID is supplied to the decoder 51.

This preset pulse is supplied to the counter 52. The counter 52 determines the start position of the post-recording area. The output of the logic circuit 53 is supplied to the counter 52 as an enable. The after-recording ID, the pilot signal detection pulse Pf, and the block synchronization pulse Psy are supplied to the logic circuit 53. When the post-recording ID is at a low level, that is, in a state indicating non-post-recording, a block sync pulse is supplied from the logic circuit 53 to the counter 52. This logic circuit 53 defines the start position of the post-recording area based on the block sync pulse of the post-recorded data.

The count value of the counter 52 is the decoder 54.
Is supplied to. A signal indicating the type of post-record data is supplied to the decoder 54, and the decoder 54 forms data indicating the start position of the post-record area corresponding to the data to be post-recorded. The output signal of the decoder 54 is supplied to the after-recording area generation circuit 55. Post-recording area generation circuit 5
A signal indicating the after-recording data type is supplied to 5.
The post-recording area generation circuit 55 detects the end position of the post-recording area according to the type of post-recording data from the start position of the post-recording area formed by the decoder 54. The after-recording area pulse Px generated by the after-recording area generating circuit 55.
Rises from the post-recording start position and falls at the end position according to the type of post-recording data.

For example, when post-recording is performed on the audio 2 section, if the preceding video section is not the post-recording section, the counter 52 is preset at the end position of the postamble of the video section and, for example, two block sync pulses. Occurs, a signal of the start position of the post-recording area is generated at the output of the decoder 54. Further, the post-recording area generation circuit 55 can detect the end position by looking at the output of the decoder 54 and the data of the type of post-recording data. Here, if the video section is post-recorded by the post-recording ID, the end position of the section is detected for the audio 1 before it. If the audio 1 is also post-recorded, the detection pulse Pf of ATF1 is used.

Although not described in FIG. 1, the after-recording area pulse Px is supplied as a control signal to the recording amplifiers 12A and 12B, and the recording amplifiers 12A and 12B are activated during the high level period of the pulse Px. It If necessary, the post-recording area pulse Px is supplied to the reproduction amplifier 21A,
21B, and the reproduction amplifier 2 during the high level period.
1A and 21B may be inactive.

[0078]

According to the present invention, since the sync block lengths of video data, audio data, and subcode are set to integer ratios, timing control and the like are simplified, and the configuration of the processing circuit is simplified. it can. According to the present invention, the length of each recording section and non-data section of one track is an integral multiple of the length of one sync block, so that the timing control related to these sections can be simplified.
Further, according to the present invention, since the number of parities generated by a plurality of rows of the product code of the subcode is equal to that generated by one row of the product code of the video data, hardware for parity generation and error correction is provided. Can be shared.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration on a recording side of a signal processing unit in an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration on a reproduction side of a signal processing unit.

FIG. 3 is a schematic diagram showing an example of a block for block coding.

FIG. 4 is a schematic diagram used to explain subsampling and sublines.

FIG. 5 is a block diagram showing an outline of an example of a channel encoder.

FIG. 6 is a block diagram showing an outline of an example of a channel decoder.

FIG. 7 is a schematic diagram used to describe a head arrangement.

FIG. 8 is a schematic diagram used to describe the azimuth of the head.

FIG. 9 is a schematic diagram used to describe a recording pattern.

FIG. 10 is a schematic diagram used to explain a data array according to an embodiment of the present invention.

FIG. 11 is an area showing a structure of a product code of video data, audio data, and a subcode.

FIG. 12 is a schematic diagram showing division of one frame of audio data in the 525/60 system.

FIG. 13 is a schematic diagram showing a track pattern of segment recording of data of one frame in the 525/60 system.

FIG. 14 is a schematic diagram of an example of audio data interleaving in a 525/60 system.

FIG. 15 is a schematic diagram of another example of interleaving audio data in a 525/60 system.

FIG. 16 is a schematic diagram showing division of one frame of audio data in the 625/50 system.

FIG. 17 is a schematic diagram showing a track pattern of segment recording of 1-frame data in the 625/50 system.

FIG. 18 is a schematic diagram of an example of audio data interleaving in a 625/50 system.

FIG. 19 is a schematic diagram used for explaining an error correction of audio data recorded in a soft tape mode.

FIG. 20 is a schematic diagram used for explaining an error correction of audio data recorded in a user recording mode.

FIG. 21 is a schematic diagram used for explaining an error correction of audio data when one magnetic head is clogged.

FIG. 22 is a schematic diagram showing a configuration of an ID signal.

FIG. 23 is a block diagram of an example of a configuration for generating a control signal that defines an after-recording area.

[Explanation of symbols]

 1Y, 1U, 1V Component signal input terminal 1A PCM audio signal input terminal 1S Subcode input terminal 5,6 Blocking circuit 8 Block coding circuit 11 Channel encoder 13A, 13B Magnetic head 15 Audio coding circuit 22 Channel decoder 38 Audio Decoding Circuit

Claims (5)

[Claims] 1. A digital image signal recording apparatus, wherein an input digital image signal is compression-encoded, and the encoded digital image signal is recorded on a magnetic tape by a magnetic head mounted on a rotary drum. Means for performing error correction coding of the digitized digital image signal, digital audio signal, and control additional data by a product code, and output data of the error correction coding means, wherein the data of one row of the product code And a means for generating a data sequence having a sync block configuration by adding a block synchronization signal to each of the digital image signal, the digital audio signal, and the additional data. A digit characterized by being set, as represented by an integer ratio Recording apparatus for an image signal. 2. An apparatus for recording a digital image signal, wherein an input digital image signal is compression-encoded and the encoded digital image signal is recorded on a magnetic tape by a magnetic head mounted on a rotary drum. Means for performing error correction coding of the digitized digital image signal, digital audio signal, and control additional data by a product code, and output data of the error correction coding means, wherein the data of one row of the product code A recording processing means including means for generating a data sequence having a sync block configuration by adding a block synchronization signal to each of them, and recording processing of the digital image signal, the digital audio signal and the additional data. Subsequent data is recorded in separate sections of the magnetic tape track. It is,
A recording apparatus for a digital image signal, wherein the section length is defined by an integral multiple of the sync block length of any one of the digital image signal, the digital audio signal and the additional data. 3. An apparatus for recording a digital image signal, wherein an input digital image signal is compression-encoded, and the encoded digital image signal is recorded on a magnetic tape by a magnetic head mounted on a rotary drum. Means for performing error correction coding of the digitized digital image signal, digital audio signal, and control additional data by a product code, and output data of the error correction coding means, wherein the data of one row of the product code A recording processing means including means for generating a data sequence having a sync block configuration by adding a block synchronization signal to each of them, and recording processing of the digital image signal, the digital audio signal and the additional data. Subsequent data is recorded in separate sections of the magnetic tape track. It is,
The section length and the non-data section length between the sections are defined by an integral multiple of the sync block length of any one of the digital image signal, the digital audio signal, and the additional data. Recording device for digital image signals. 4. An apparatus for recording a digital image signal, wherein an input digital image signal is compression-encoded and the encoded digital image signal is recorded on a magnetic tape by a magnetic head mounted on a rotary drum. Means for performing error correction coding of the digitized digital image signal, digital audio signal, and control additional data by a product code, and output data of the error correction coding means, wherein the data of one row of the product code A recording processing means including means for generating a data sequence having a sync block configuration by adding a block synchronization signal for each of the above, and the product code is generated by a plurality of rows of the additional data. Make the number of parity and the number of parity generated by one row of the digital image signal equal. Recording apparatus in a digital image signal, characterized in that set. 5. An apparatus for recording a digital image signal, wherein an input digital image signal is compression-encoded, and the encoded digital image signal is recorded on a magnetic tape by a magnetic head mounted on a rotating drum. Means for performing error correction coding of the digitized digital image signal, digital audio signal, and control additional data by a product code, and output data of the error correction coding means, wherein the data of one row of the product code And a recording processing means including means for generating a data sequence having a sync block configuration by adding a block synchronization signal and an ID signal to each of the digital image signal, the digital audio signal, and the additional data. Between each of the sync blocks, the block sync signal As the length of the length and the ID signal are equal, the recording apparatus of the digital image signal, characterized in that set.