JP2715418B2 - Error correction coding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to coding adapted to a dynamic range,
The present invention relates to an error correction coding device applied when transmitting data obtained by high-efficiency coding such as discrete cosine transform. [Prior Art] The present applicant seeks a dynamic range defined by a maximum value and a minimum value of a plurality of pixels included in a two-dimensional block, as described in JP-A-61-144989. A high-efficiency coding apparatus that performs coding adapted to the dynamic range has been proposed. Also, JP-A-62-92620
As described in Japanese Patent Application Laid-Open Publication No. H10-264, there has been proposed a high-efficiency coding apparatus that performs coding suitable for a dynamic range with respect to a three-dimensional block formed from pixels in a region included in each of a plurality of frames. Further, as described in JP-A-62-128621, a variable length coding method in which the number of bits changes according to a dynamic range in which the maximum distortion generated when performing quantization is constant is proposed. Have been. High-efficiency code (AD
RC) is suitable for application to a digital VTR because it can significantly reduce the amount of data to be transmitted. In ADRC, data obtained by encoding includes two data (fixed length data for each block) of the dynamic range DR, maximum value MAX, and minimum value MIN, and a code signal (variable length data) corresponding to each pixel of the block. ). In addition, in the case of encoding that combines ADRC and frame dropping compression as described in Japanese Patent Application Laid-Open No. 62-107526, a motion determination code MOVE indicating the presence or absence of motion is transmitted. Of these transmitted codes, fixed-length data for each block is an ADRC parameter, so if fixed-length data became error data, even if other data was correct, fixed-length data became error data. Block cannot be decrypted. In this sense, fixed-length data is data having a higher importance than variable-length data corresponding to each pixel. In a digital VTR, both a random error and a burst error occur during recording / reproduction. Therefore, even in a conventional digital VTR, an error correction code such as a product code including an inner code and an outer code is usually used. That is, for random errors, the interleave length is corrected to 0 or a short inner code. For burst errors, it is detected that the inner code cannot be corrected, and a pointer of this inner code is used to set a long interleave length. Was corrected with an outer code having. ADRC
Applying to the data obtained in the above has a problem in that the above difference in importance in the ADRC data is not taken into account. [Problems to be Solved by the Invention] One method of solving this problem is to perform encoding of data having high importance (fixed length data) with a dedicated third error correction code. Conceivable. This third
The following is conceivable as a method of encoding the error correction code. As with the inner code, encoding is performed to deal with random errors. As with the outer code, encoding is performed to cope with the burst error. A code completely different from the inner code and the outer code is performed. The same encoding as the inner code and outer code is performed. The method of (1) has a problem that the scale of hardware for encoding is large and the degree of redundancy is high. The method of (1) has a problem that redundancy is increased. It is necessary to consider a process for an error that could not be corrected to determine which method is preferable.
That is, when a long burst error occurs, fixed-length data with high importance can be corrected, and a code signal corresponding to each pixel has an error state. In this case, for example, average value data formed from fixed-length data is used as data of each pixel. On the other hand, interpolation processing is usually performed on data of pixels for which error correction has failed. When the interpolation processing can be performed to some extent, as described above, a better image can be formed as compared with the image quality of an image (consisting of average value data) obtained only from data having high importance. Therefore, as the third error correction code for data having high importance, it is preferable to perform encoding for dealing with random errors as in the method described in (1). Although the above description is of the case of ADRC, the DC component in the case of discrete cosine transform is also of high importance, so the same applies to the case where the third error correction code is encoded for this DC component. Holds. Therefore, an object of the present invention is to provide a high-efficiency encoding
It is an object of the present invention to provide an error correction encoding device capable of obtaining a high-quality restored image by performing dedicated encoding for correcting random errors on data having high importance. [Means for Solving the Problems] The present invention provides a method for generating a first digital signal by using a plurality of pixel data included in a two-dimensional or three-dimensional region of an input digital image signal, the pixel data being adjacent in the region. And a second block, perform high-efficiency coding in units of the first and second blocks, and code signals of a number corresponding to each pixel data in each block, and Coding means for generating parameter data and for separating the positions of the code signal and parameter data of the first block and the code signal and parameter data of the second block on the transmission sequence from each other so as not to be affected by a burst error And a data unit for transmitting the code signal and the parameter data generated by the encoding means is arranged in the first direction, and is directly arranged in the first direction. Error correction coding means for performing error correction coding processing in a first direction and a second direction in a data array having a plurality of data units arranged in a second direction. The encoding means encodes only the parameter data with a first error correction code in a first direction, and encodes the parameter data, the code signal, and the parity generated by encoding the first error correction code. To encode the second error correction code in the first direction,
And a third error correction code is encoded in the direction of. [Operation] In the example of the ADRC, fixed-length data such as a dynamic range DR, a minimum value MIN, a maximum value MAX, and a motion determination code MOVE for each block are data of high importance. For these highly important data, an error correction code for correcting a dedicated random error is encoded. Therefore, the fixed-length data is more likely to be error-corrected than the code signal for each pixel, and it is possible to prevent information of the entire block from becoming an error. When a long burst error occurs and both fixed-length data and variable-length data become error data, the error of the data of each pixel is made inconspicuous by the interpolation processing. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. This description is made in the following order. a. Configuration of recording / reproducing circuit b. Blocking process c. Configuration of transmission data d. Error correction code e. Modification a. Configuration of recording / reproducing circuit Referring to FIG. The recording / reproducing circuit will be described. In FIG. 1, a recording video signal is supplied to an input terminal indicated by 1. 2 indicates an A / D converter, and A
The video signal converted into a digital signal by the / D converter 2 is supplied to the blocking circuit 3. The effective area of the video signal is subdivided into blocks of (4 lines × 4 pixels × 2 frames = 32 pixels). As described later, this blocking is performed to make the interpolation process easy (4 lines × 8 pixels ×
This is a process for forming two blocks from an area of (2 frames = 64 pixels). At the same time, in the blocking circuit 3,
Shuffling is performed so that recording positions of adjacent blocks are separated as much as possible. The digital video signal converted in the block order by the blocking circuit 3 is supplied to the ADRC encoder 4. As described in detail in JP-A-60-247840 and Japanese Patent Application No. 61-153330, the ADRC encoder 4 discriminates whether a block is a motion block or a stationary block. Is subjected to frame drop compression in which the average value of one or two of the two regions constituting the block is quantized and transmitted. A motion determination code MOVE is transmitted to the receiving side to indicate whether the frame drop processing has been performed. In the ADRC encoder 4, the maximum value is
MAX and the minimum value MIN are detected, and the dynamic range DR is detected by (MAX-MIN). The frequency distribution of the dynamic range DR for two frame periods is obtained, and the threshold values T0, T1, T2, T3 of the variable length quantization are determined. Threshold T0
Blocks smaller than the threshold value T1 are not transmitted, and blocks smaller than the threshold value T1 are quantized by one bit. Blocks smaller than the threshold value T2 are quantized by two bits, and the threshold value T3 Blocks smaller than T3 are quantized by 3 bits, and blocks equal to or larger than the threshold value T3 are quantized by 4 bits. The reason why the frequency distribution is obtained and the threshold is determined is to perform buffering processing so that the transmission data rate does not exceed a predetermined value. Output data from the ADRC encoder 4 is supplied to the framing circuit 5. The output data of ADRC encoder 4 is 2
Are fixed length data including a motion determination code MOVE for each frame, a dynamic range DR for each block, and a minimum value MIN for each block, and variable length data including a code signal corresponding to each pixel. The framing circuit 5 arranges these data in a predetermined order to form data having a frame configuration. That is, as described in the specification of Japanese Patent Application No. 61-240890, even in the case of the variable-length ADRC, a data sequence in which fixed-length data is positioned at a predetermined period is formed. As described above, since the fixed-length data is located at a predetermined period, the reproduction of the fixed-length data becomes easy when the data is obtained in pieces during high-speed reproduction. Further, as described in the specification of Japanese Patent Application No. 61-240889, the most significant bits of the code signal may be collectively handled as fixed-length data. The output signal of the framing circuit 5 is supplied to a formatter 6 in the sync block, and the output data of the formatter 28 is supplied to a parity generation circuit 7 for generating a parity PT1 for fixed-length data with high importance. The output data of the parity generation circuit 7 is supplied to the formatter 8 in the segment, and the output data of the formatter 8 is supplied to the parity generation circuit 9 for generating the outer code parity PT2.
Output data of the parity generation circuit 9 is supplied to a parity generation circuit 11 for generating an inner code parity PT0 via a formatter 10 in the segment. These parity generating circuits 7, 9, 11 generate the parity of the Reed-Solomon code as described later. The output data of the parity generation circuit 11 is
According to 12, the data is subjected to randomization processing by an M sequence or the like. The DC component of the recording data is reduced by the randomization process. The output data of the randomizer 12 is added to the adder
The sync signal (SYNC) from the terminal 14 and the ID signal are added to the signal 13. The output data of the adding circuit 13 is converted into serial data via a parallel-to-serial conversion circuit 15 and supplied to a recording terminal R of a switch circuit 17 via a recording amplifier 16. The recording data from the switch circuit 17 is supplied to a pair of circuit heads 18a and 18b and recorded on the magnetic tape 19 as oblique tracks. Data alternately reproduced by the rotary heads 18a and 18b from the magnetic tape 19 is supplied to the PLL circuit 23 via the reproduction side terminal P of the switch circuit 17, the reproduction amplifier 21, and the equalizer circuit 22.
Supplied to The PLL circuit 23 forms a bit clock synchronized with the reproduction data. The synchronization signal and the ID signal are separated by the synchronization signal and ID signal separation circuit 24 connected to the PLL circuit 23. The synchronization signal and the output data of the ID signal separation circuit 24 are supplied to a derandomization circuit 25, and derandomization processing is performed by the same sequence such as the M sequence used in the randomization on the recording side. Reference numeral 26 denotes a reproduction memory composed of, for example, four frame memories. Play memory
According to 26, correction of time axis fluctuation (TBC) and data collection processing during variable speed reproduction are performed. The output data of the reproduction memory 26 is supplied to the error correction circuit 27. The error correction circuit 27 corrects the error of the inner code. Output data of the error correction circuit 27 is supplied to the formatter 28 in the segment, and output data of the formatter 28 is supplied to the error correction circuit 29. The error correction circuit 29 corrects the error of the outer code. The output data of the error correction circuit 29 is the formatter in the segment.
The data is supplied to an errata correction circuit 31 via 30 and error correction is performed on fixed-length data having high importance. Furthermore,
The output data of the error correction circuit 31 is converted into a formatter
It is supplied to an outer code error correction circuit 33 via 32. The output data of the error correction circuit 33 is supplied to the deframing circuit 35 via the formatter 34. The deframing circuit 35 separates the dynamic range DR, the minimum value MIN, the motion determination code MOVE, and the code signal,
The decoder 36 decodes the ADRC. The output data of the ADRC decoder 36 is supplied to a block decomposition circuit 37, where the data in the block order is converted into the data in the scanning order. Output data of the block decomposition circuit 37 is supplied to a smoothing and interpolation circuit 38. The smoothing process is a process in which, when the still blocks are continuous, the data at the boundary between the blocks is replaced by the average value data of the data of the preceding and following blocks. The interpolation process is
This is a process of replacing data of a pixel for which error correction cannot be performed with interpolation data using surrounding correct data. The processing data of the smoothing and interpolation circuit 38 is supplied to the D / A converter 39, and the digital bit signal is converted into an analog video signal,
At the output terminal 40, a reproduced analog video signal is obtained. b. Blocking Process FIG. 2 shows the blocking process performed in the blocking circuit 3. As shown in FIG.
Belong to each of the frames and occupy the same spatial position (4
In two regions of (line × 8 pixels), two blocks are formed by white dots and black dots located in a dice fifth-eye lattice. FIG. 2B shows one block of (4 lines × 4 pixels × 2 frames) formed by black dots. Although not shown, another block of the same size is similarly formed by the white dot. The blocking circuit 3 is configured to have two 2-frame memories, for example, one 2-frame memory and the other 2 frame memory.
Data writing and reading are alternately performed with the frame memory. For example, during a two-frame period in which data is sequentially written to one of the two-frame memories,
Data is read from the frame memory. At the time of reading, as shown in FIG. 2A, data is read in a quincunx lattice, and the read data constitutes a block. The two blocks formed in this way are recorded at positions separated at the time of recording, and it is prevented that both of the two blocks become error data due to a burst error. In the reproduced data, even if one of the data blocks composed of, for example, white dots becomes error data,
As shown in FIG. C, since the correct data of the black dot of the other block is located in the periphery, the data of the center white dot is interpolated by, for example, the average value of the surrounding data, thereby obtaining the error data. Can be performed in the frame. This interpolation processing is performed in the smoothing and interpolation circuit 38. In the case where two blocks are formed so as to form a fifth eye lattice, a fifth eye lattice may be formed in a field as shown in FIG. 2D. In this case, intra-field interpolation is performed. Further, transmission of one of the two blocks formed by the above-described blocking may be omitted. In the case of a digital VTR, two modes, an SP mode with good image quality and an LP mode capable of recording for a long time, are often provided. For example SP
In the case of the mode, the rate of the recording data is set to 30 Mbps, and in the case of the LP mode, the rate is set to 15 Mbps. Therefore, by recording two blocks together in the SP mode, and by recording only one block in the LP mode,
The data rate is halved. In the case of the LP mode, recording is performed in the same manner as the recording method for performing sub-sampling as described in Japanese Patent Application No. 61-182492. c. Structure of Transmission Data FIG. 3A shows one sync block of a byte serial data structure before serialization by the parallel-to-serial conversion circuit 15. This sync block has a length of 156 bytes including the following data. Block synchronization signal: 2-byte ID signal (frame ID, segment ID): 2-byte BADS and bit plane: 20 bytes (data of four ADRC blocks) × 4: 27 × 4 = Parity PT0: 4 of 108-byte inner code Parity PT1 and bit plane dedicated to data with high byte importance: 20 bytes BADS of 20 bytes includes BADS1 to BADS4 of 1 byte and bits of (4 × 4 = 16 bytes) as shown in FIG. 3B. And a plane (code signal of each pixel). As shown in FIG. 3B, the data of the four ADRC blocks includes a motion determination code MOVE (1 byte), a dynamic range D
R, 4 blocks of minimum value MIN (hence 8 bytes)
It consists of a bit plane (18 bytes). As shown in FIG. 3C, the 20-byte parity PT1 and the bit plane consist of a 4-byte parity PT1 and a 16-byte bit plane. Furthermore, the 4-byte BADS1 to BADS4 are
As shown in FIG. D, a 1-bit 2-frame ID (DBFR) and
5-bit code Yth indicating a set of a 15-bit head ADRC block number (BLKn) and a threshold value for a luminance signal
, A 5-bit code Cth indicating a set of threshold values for the color difference signal, a 4-bit ADRC block address, and 2-bit spare bits. d. Error Correction Code The configuration of the error correction code will be described with reference to FIG. The error correction code in this embodiment is basically a product code. Four sync blocks shown in FIG. 3A are arranged in the horizontal direction and 46 sync blocks are arranged in the vertical direction. The parity generation circuit 7 on the recording side generates a parity PT1 for data having high importance. 4 bytes of BADS1 to BADS4 and ADRC fixed length data (MOVE, DR, MIN: 9 × 4
= 36 bytes), a 4-byte parity of the Reed-Solomon code is generated for a total of 40 bytes. Parity PT1
Is an error correction code for random error correction because it is generated for data included in the sync block and is not interleaved. Next, the parity of the outer code is
PT2 is generated. The parity PT2 of the outer code is a parity of a 4-byte Reed-Solomon code generated from 46 bytes of data (excluding the synchronization signal and the ID signal) arranged in the vertical direction in FIG. Then, the parity generation circuit 11 generates the parity PT0 of the inner code. As shown in Fig. 3, 20 bytes of B
ADS, 4 ADRC blocks (4 × 27 = 108) and parity PT
1 (20 bytes), total of 148 bytes to 4 bytes of parity
PT0 is generated. The data sequence is recorded in order from the data sequence located in the first row of FIG. On the reproduction side, the error correction circuit 27 first corrects the error of the inner code (parity PT0). The error correction of the inner code corrects only 1-byte error correction, and sets a pointer indicating an error in error data of 2 bytes or more. Next, the error correction circuit 29 corrects the error of the outer code. The error correction of the outer code is an erasure correction using a pointer, and a 3-byte error is corrected. Then, the error correction circuit 31 corrects the error of the data of high importance. In this error correction, an error of 4 bytes indicated by the pointer of the inner code is erasure-corrected. In order to increase the error correction capability, the erasure correction of the outer code is performed again by the error correction circuit 33. This erasure correction corrects an error of up to three bytes. e. Modifications The present invention is also applicable to high-efficiency codes other than ADRC, for example, discrete cosine transform. In this case, the DC component becomes data of high importance, and the DC component is encoded with a dedicated random error correction code. Further, in the present invention, an error correction code other than the Reed-Solomon code can be used. In the above description, when two blocks are formed from an area twice as large as one block, the data is divided into a quincunx lattice. However, the present invention is not limited to this, and two blocks may be formed by alternately selecting pixels in the sample direction or alternately selecting pixels in the line direction. [Effects of the Invention] In the present invention, when transmitting image data encoded with a high-efficiency code such as ADRC through a transmission path in which a random error and a burst error coexist as in a digital VTR, the encoded data Among them, data having a high degree of importance is encoded with a dedicated error correction code. This error correction code can correct a random error. Therefore, according to the present invention, the redundancy is not so high,
It is possible to improve the error correction capability of highly important data, and to improve the restored image quality.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of a recording / reproducing circuit according to one embodiment of the present invention, FIG. 2 is a schematic diagram used for explaining block formation, and FIG. FIG. 4 is a schematic diagram showing a data structure of a sync block, and FIG. 4 is a schematic diagram used for describing an error correction code in one embodiment of the present invention. Description of main symbols in the drawings 3: Blocking circuit, 4: ADRC encoder, 7, 9, 11: Parity generation circuit, 18a, 18b: Rotating head, 27, 29, 31, 33: Error correction circuit, 36: ADRC Decoder, 37: block decomposition circuit.

Claims (1)

(57) [Claims] A plurality of pixel data included in a two-dimensional or three-dimensional area of the input digital image signal, and a first and a second pixel data are respectively determined by pixel data adjacent in the area.
Are formed, and high-efficiency coding is performed for each block of the first and second blocks. A number of code signals corresponding to each pixel data in each of the blocks and a parameter for each block are formed. And a code that separates the positions of the code signal and parameter data of the first block and the code signal and parameter data of the second block in the transmission sequence from each other so as not to be affected by a burst error. And a data unit for transmitting the code signal and the parameter data generated by the encoding means.
In a data array in which a plurality of the data units are arranged in a second direction orthogonal to the first direction, error correction coding is performed in the first direction and the second direction. Error correction encoding means for performing the following processing, wherein the error correction encoding means encodes only the parameter data with a first error correction code in the first direction, and The data, the code signal, and the parity generated by the code of the first error correction code are encoded with a second error correction code in the first direction, and a third error correction code is encoded in the second direction. An error correction coding device for coding an error correction code.