JP3817881B2 - Digital video signal processing apparatus and method, and digital video signal reproducing apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital video signal processing apparatus and method for improving data loss due to overwriting during high-speed reproduction when processing digital video data shuffled with a plurality of shuffling patterns, and The present invention relates to a digital video playback apparatus.
[0002]
[Prior art]
Digital video recorders (hereinafter abbreviated as DVR) that record / reproduce video signals in a digital manner are becoming widespread. In such a DVR, a digital video signal is subjected to a shuffling process so that errors are not concentrated on the screen together with a compression encoding process using, for example, DCT (Discrete Cosine Transform). Then, an error correction code using a product code is further added to this data and recorded on the magnetic tape. A digital video signal is recorded on the magnetic tape by forming a helical track by a rotating head. At this time, a so-called double azimuth method is used in which adjacent tracks are formed by heads having different azimuth angles.
[0003]
At the time of reproduction, deshuffling is performed on the reproduction data from the magnetic tape, and the shuffled data is restored. Then, after the error correction code is decoded for error correction, the compressed code is decoded. Further, concealment processing is performed on the data that could not be corrected by a predetermined method. This concealing process is performed, for example, by interpolating between the fields for images with a lot of movement within the field and for images with little movement such as a still image.
[0004]
Data compression coding using DCT is performed in units of DCT blocks obtained by dividing one frame screen into, for example, 8 × 8 pixels. Prior to compression encoding, data is shuffled. By shuffling the DCT block within one screen, the amount of information is averaged, the compression efficiency is increased, and errors are prevented from being concentrated on the screen.
[0005]
Conventionally, the shuffling pattern in one screen is fixed. Therefore, there is a one-to-one correspondence between the recording position on the magnetic tape and the pixel. In the case of recording / reproducing with respect to a magnetic tape, there is a possibility that an uncorrectable error may occur due to an error correction code due to, for example, a scratch in the longitudinal direction of the tape on the magnetic tape or a clog of the magnetic head. In this case, a large number of pixels that cannot be reproduced absolutely occur.
[0006]
In order to avoid this problem, a method called SFP toggle has been proposed in which shuffling patterns (hereinafter abbreviated as SFP) are switched in units of picture (one frame unit or one field unit). According to this, even if a certain pixel cannot be reproduced due to the clog of the magnetic head, the next image is reproduced by another head that is not clogged, and the recorded image can be reproduced. In particular, when the SFP toggle method is not used, it is easy to notice that the still image portion has been concealed. However, according to this method, all pixels are reproduced.
[0007]
[Problems to be solved by the invention]
Now, let us consider a case where high-speed playback is performed on a tape on which a video signal has been recorded in this manner, which is played back at a tape speed faster than that at the time of recording. 24 and 25 show examples of the relationship between the magnetic head and the track during high-speed playback. In this example, one frame consists of 12 tracks on which azimuth is recorded, and one segment is composed of two adjacent tracks. Therefore, one frame consists of six segments and is reproduced by six scans of the magnetic head. The reproduced data is stored in the memory in units of frames when error correction is performed.
[0008]
In FIG. 24A and FIG. 25A, the track is shown by only one azimuth. In addition, tracks with different frames are individually painted and correspond to different SFPs in the SFP toggle. It can be seen that two types of SFPs are used alternately. Further, the arrow represents the scan of the magnetic head, and image data for one frame is reproduced by six scans A to F. FIGS. 24B and 25B show examples of the waveform of the reproduction RF signal and the reproduction signal by the magnetic head, respectively.
[0009]
FIG. 24 shows an example of quadruple speed playback in which playback is performed at a speed four times that during recording. In this example, as shown in FIG. 24A, scans 0, 1, and 2 and scans 3, 4, and 5 pass through the same location with respect to the segment. Therefore, when the magnetic tape is running at an accurate multiple speed, the reproduction data of scans 3, 4, and 5 overwrite the reproduction data of scans 0, 1, and 2 on the memory. The playback data of 1 and 2 is lost.
[0010]
Further, in the example shown in FIG. 25 where reverse reproduction is performed at a speed three times that at the time of recording, as shown in FIG. 25B, the same location is passed every two scans. That is, in this example, the scans 0 and 1 are overwritten on the scans 2 and 3, and the scans 2 and 3 are further overwritten on the scans 4 and 5. Accordingly, only the last scans 4 and 5 remain as reproduction data.
[0011]
As described above, in the reproduction data, since the memory address and the pixel to be stored do not have a one-to-one correspondence, the pixel of the image is overwritten with a different pixel before the image stored in the memory is reproduced. There was a problem that occurred.
[0012]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a digital video signal processing apparatus and method, and a digital video reproduction apparatus that do not cause overwriting of data in a frame during high-speed reproduction.
[0013]
[Means for Solving the Problems]
In order to solve the above-described problems, the present invention is such that pixel data is shuffled by a plurality of shuffling patterns, and the plurality of shuffling patterns are changed for each image unit and recorded on a magnetic tape. In a digital video signal processing apparatus that handles a digital video signal, unifying means for unifying a plurality of shuffling patterns applied to the digital video signal so as to change for each image unit into one shuffling pattern; A digital video signal processing apparatus comprising: a memory for storing the digital video signal output from the unifying unit; and a memory control unit for reading out the digital video signal stored in the memory in an original order. It is.
[0014]
In addition, in order to solve the above-described problems, the present invention is such that pixel data is shuffled by a plurality of shuffling patterns, and the plurality of shuffling patterns are changed for each image unit and recorded on a magnetic tape. In a digital video signal processing method for handling a digital video signal, a plurality of shuffling patterns applied to the digital video signal so as to change for each picture unit are unified into one shuffling pattern. A memory for storing the digital video signal output from the unifying step, and a memory control step for reading the digital video signal stored in the memory in the original order. A digital video signal processing method.
[0015]
In addition, in order to solve the above-described problems, the present invention is such that pixel data is shuffled by a plurality of shuffling patterns, and the plurality of shuffling patterns are changed for each image unit and recorded on a magnetic tape. In a digital video signal reproducing apparatus using a digital video signal processing apparatus that handles a digital video signal, pixel data is shuffled from a magnetic tape by a plurality of shuffling patterns, and the plurality of shuffling patterns are displayed for each image unit. Reproducing means for reproducing a digital video signal recorded in such a manner as to be changed, error correcting means for correcting an error of the digital video signal reproduced by the reproducing means, and digital video signal error-corrected by the error correcting means Multiple shuffling patterns of one shuffling pattern Standardization means, a memory for storing the digital video signal output from the standardization means, and the digital video signal stored in the memory are read out in the original order and output as a reproduction signal. And a digital video signal reproducing apparatus using the digital video signal processing apparatus.
[0016]
As described above, according to the present invention, a digital video signal having a plurality of shuffling patterns applied so as to change for each image unit is stored in a memory by unifying the shuffling patterns, and the digital video signal is stored from the memory. When reading, since reading is performed in the original reading order, overwriting with different pixels on the memory is not performed.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. First, in order to facilitate understanding, a digital VTR to which the present invention can be applied will be described. The digital VTR records a high resolution video signal on a magnetic tape and reproduces the high resolution video signal from the magnetic tape. FIG. 1 shows an example of the configuration of a recording / reproducing system for such a digital VTR. FIG. 1 shows a four-head system having four recording heads and four reproducing heads.
[0018]
In FIG. 1, a high resolution digital video signal is input to an input terminal 1. This digital video signal is supplied to the input filter 2. In the input filter 2, a filtering process for compressing the (4: 2: 2) signal into a (3: 1: 1) signal is performed. Further, the clock frequency is changed from 74.25 MHz to 46.4625 MHz.
[0019]
Further, the input filter 2 converts the (3: 1: 1) signal into 2-channel data. The data for each channel has a data rate of 46.4625 MHz. The two-channel data is subjected to compression coding by BRR (Bit Rate Reduction) encoders 3 and 4 and error correction coding processing by error correction encoders (ECC encoders) 5 and 6.
[0020]
In this example, the BRR encoders 3 and 4 are configured to adaptively switch between intra-field compression and intra-frame compression, and further, for example, shuffling is performed in units of DCT blocks each including 8 × 8 pixels. When there is a lot of motion between fields, a DCT block is composed of data in the field. On the other hand, when there is little motion between fields, a DCT block is composed of data within a frame. Switching between intra-field compression coding and intra-frame compression coding is performed, for example, with one frame as a minimum unit.
[0021]
The ECC encoders 5 and 6 perform product code encoding and generate recording data in which sync blocks are continuous. First, the outer code is encoded, and then an ID part including the order of the sync blocks and various flags is added to each sync block recorded on the tape. Then, the inner code is encoded. The encoding range of the inner code includes this ID portion. One sync block is configured including the parity of the inner code and the sync signal indicating the head portion of the sync block. One sync block is the minimum unit of data to be recorded / reproduced.
[0022]
The outputs of the ECC encoders 5 and 6 are supplied to the recording equalizer 7. Two-channel recording data from the recording equalizer 7 is supplied to the recording head driver 9R via the rotary transformer 8. The recording head driver 9R includes a switching circuit that switches supply of recording signals to the recording amplifier and the head. Recording heads 10, 11, 12, 13 are connected to the recording head driver 9R, and recording data is recorded on the magnetic tape 14 by the recording heads 10-13.
[0023]
Next, the configuration on the playback side will be described. The signals recorded on the magnetic tape 14 are reproduced by the reproducing heads 15-18. A reproduction signal is supplied to the reproduction head driver 9P, and a reproduction signal of two channels is obtained from the reproduction head driver 9P. This reproduction signal is supplied to the reproduction equalizer 20 via the rotary transformer 8. Reproduction equalization is performed by the reproduction equalizer 20 to complete reproduction serial data. At the same time, the reproduction equalizer 20 generates a clock synchronized with the reproduction signal and supplies it to the ECC decoders 21 and 22 together with the data.
[0024]
An output signal (reproduction serial data) of each channel of the reproduction equalizer 20 is supplied to the ECC decoders 21 and 22. The ECC decoders 21 and 22 detect the synchronization of the input data, change from the recording rate to the system clock, and correct various errors occurring on the tape. That is, the ECC decoders 21 and 22 correct the inner code of the error correction code configured in advance. The inner code is completed in one sync block. If the error size is within the correction capability of the inner code, correction is performed, and if it is more than that, an error flag is set at the error position. Next, the process proceeds to correction of the outer code, and erasure correction is performed with reference to the error flag. Most errors can be corrected by this, but in the case of a long error in the longitudinal direction of the tape, there are rare cases where the error cannot be corrected. At that time, detection within the detection capability range of the outer code is performed, and an error flag is set at the position of the error word.
[0025]
From the ECC decoders 21 and 22, the data is output on a 46.4625 MHz clock, data is output in units of sync blocks, and a word error flag is output. The outputs of the ECC decoders 21 and 22 are supplied to the BRR decoders 23 and 24, respectively. The BRR decoders 23 and 24 perform decoding of variable length coding, inverse DCT conversion, and deshuffling, and decoding of compressed codes. Further, in correspondence with the intra-field coding / intra-frame coding performed by the BRR encoders 23 and 24, the BRR decoders 23 and 24 perform intra-field decoding / intra-frame decoding.
[0026]
The output signals of the BRR decoders 23 and 24 are supplied to the concealing circuit 25 together with the concealing error flag. The conceal circuit 25 conceals an error that exceeds the error correction capability of the ECC decoders 21 and 22 in the reproduction signal. For example, this is done by interpolating a missing portion without error correction by a predetermined method. For example, in the BRR decoders 23 and 24, when decompressing, it is determined which order of the DCT coefficient has an error from the word error flag set at the error position. If there is an error in the DC coefficient or the low-order AC coefficient that is relatively high in importance, the decoding of the DCT block is given up, the concealing flag is passed to the concealing circuit 25 in the next stage, and interpolation of the DCT block portion is performed. Processing is performed.
[0027]
The output signal of the conceal circuit 25 is supplied to the output filter 26. In the output filter 46, the clock frequency is changed (from 46.40625 MHz to 74.25 MHz), and the (3: 1: 1) signal of two channels is converted into a (4: 2: 2) signal. A playback video signal is output from the output filter 26.
[0028]
The input audio data is subjected to predetermined processing by the audio processor 19 and supplied to the ECC decoders 5 and 6. Similar to video data, a product code is encoded for each channel of audio data recorded in one track. Further, at the time of reproduction, the audio data is taken out from the ECC decoders 21 and 22, subjected to predetermined processing by the audio processor 19, and output.
[0029]
The recording heads 10 to 13 described above are mounted on a rotating drum that rotates at 90 Hz, for example. The pair of recording heads 10 and 12 and the pair of recording heads 11 and 13 are provided at close positions. The azimuths of the recording heads 10 and 12 are different. Similarly, the azimuths of the recording heads 11 and 13 are different. Further, the pair of recording heads 10 and 11 facing each other at 180 ° is set to the same azimuth. Further, the reproducing drums 15, 16, 17 and 18 are provided on the rotating drum. The arrangement of the reproducing heads 15, 16, 17 and 18 and the azimuth relationship are the same as those of the recording heads 10, 11, 12 and 13 described above.
[0030]
The magnetic tape is wound around the rotating drum with a winding angle of 180 °, and the recorded data is sequentially recorded as oblique tracks on the magnetic tape. The recording head driver 9R is provided with a recording circuit and a switching circuit for switching a recording signal in synchronization with the rotation of the head. Similarly, the reproducing head driver 9P is provided with a reproducing amplifier and a switching circuit. A switching pulse SWP synchronized with the rotation of the head is supplied from the servo circuit 28 as indicated by a broken line. This switching pulse SWP is also supplied to the ECC encoders 5, 6 and ECC decoders 21 and 22.
[0031]
In correspondence with the recording heads 10 to 13 and the reproducing heads 15 to 18, as shown in FIG. 1, when the symbols A, B, C, and D are given, the recording heads A and B are recorded by the recording heads 10 and 12. Are simultaneously formed. Next, the recording heads 11 and 13 simultaneously form the tracks C and D corresponding to the recording heads C and D. In one embodiment of the present invention, recording data of one frame (1/30 second) of a video signal is recorded on 12 continuous tracks. A segment is composed of two adjacent tracks (A and B channels, and C and D channels) having different azimuths as a set. Therefore, one frame of the video signal consists of 6 segments. Each of these six segments is given a segment number from 0 to 5. Note that the audio data having four channels is recorded so as to be sandwiched between video data, for example, at the center of each track.
[0032]
FIG. 2 shows another example of a digital VTR to which the present invention can be applied. FIG. 2 shows an eight-head system in which a video camera and a digital VTR are integrated and each has eight recording heads and eight reproducing heads. A color image is picked up by a CCD indicated by 120 and converted into a two-channel video signal by A / D conversion and camera processor 121. The video signals of the respective channels are compression encoded by the BRR encoders 122 and 123 and supplied to the ECC encoders 30 and 31.
[0033]
Each channel is further divided into two channels by the ECC encoders 30 and 31, and recording data of four channels is formed. Recording data is supplied to the eight recording heads 35, 36, 37, 38, 39, 40, 41, and 42 via the recording equalizer 32, the rotary transformer 33, and the recording head driver 34 R. Recorded as a track.
[0034]
Reproduction heads 43, 44, 45, 46, 47, 48, 49, 50 similar to the recording head are provided, and an output signal of the reproduction head is converted into a four-channel reproduction signal by the reproduction head driver 34P. This reproduction signal is supplied to the reproduction equalizer 52 via the rotary transformer 33. The output of the reproduction equalizer 52 is supplied to the ECC decoders 53 and 54, and error correction processing is performed. At the outputs of the ECC decoders 53 and 54, two-channel reproduction data is generated, and these are decoded by the BRR decoders 55 and 56.
[0035]
The switching pulse SWP from the servo circuit 58 is supplied to the ECC encoders 30 and 31, the ECC decoders 53 and 54, the recording head driver 34R, and the reproducing head driver 34P, and timing control synchronized with the rotation of the head is performed.
[0036]
The reproduced data, which has been subjected to compression encoding by the BRR decoders 55 and 56, is supplied to the conceal circuit 59, and an error that cannot be corrected is interpolated. The output of the conceal circuit 59 is supplied to the output filter 127. The output filter 127 converts the (3: 1: 1) signal into a (4: 2: 2) signal and extracts it as an output video signal.
[0037]
The input audio data is subjected to predetermined processing by the audio processor 126 and supplied to the ECC encoders 30 and 31. Similar to video data, a product code is encoded for each channel of audio data recorded in one track. At the time of reproduction, audio data is taken out from the ECC decoders 53 and 54, subjected to predetermined processing by the audio processor 126, and output.
[0038]
In the configuration shown in FIG. 2, the number of recording heads and reproducing heads is twice as many as the configuration shown in FIG. 1 (that is, eight). This is to reduce the number of rotations of the drum to half that of the four-head system in FIG. That is, the four recording heads 35 to 38 in FIG. 2 are the same azimuth, and the recording heads 39 to 42 are also the same azimuth. The set of recording heads 35 to 38 and the set of recording heads 39 to 42 are reverse azimuths. A pair of recording heads 35 (A) and 36 (E), a pair of recording heads 37 (C) and 38 (G), a pair of recording heads 39 (B) and 40 (F), a recording head 41 (D) and 42 The pair (H) is mounted on the rotating drum so as to face each other by 180 °.
[0039]
The recording heads 35, 37, 39, and 41 trace the magnetic tape 14 almost simultaneously, and then the recording heads 36, 38, 40, and 42 trace the magnetic tape 14 almost simultaneously. Since the drum rotation speed is halved and the number of heads is doubled, the same track pattern as the 4-head system is formed on the tape. Thus, four tracks are recorded simultaneously. Accordingly, there are four recording signals passing through the rotary transformer 33, and the opposing head is selected by the switching pulse SWP supplied from the servo circuit 58. The reproducing heads 43 to 50 have the same relationship as the recording head.
[0040]
In the 8-head system of FIG. 2, the number of reproduction signals is four, which is twice the number of the configuration of FIG. 1, but the data rate is half, so if an input stage is added, the subsequent steps are exactly the same as in FIG. Can be processed by a circuit. Since the same circuit may be used for reverse azimuth, the ECC decoders 21 and 22 (FIG. 1) and the ECC decoders 53 and 54 can all be realized by the same IC. The present invention can be applied to both the 4-head system digital VTR (FIG. 1) and the 8-head system digital VTR (FIG. 2). In the following description, the present invention is applied to a 4-head digital VTR.
[0041]
The format of one track formed on the magnetic tape is shown in FIG. This track represents the data arrangement along the direction in which the head traces. One track is roughly divided into video sectors V1 and V2 and audio sectors A1 to A4. The product code is encoded in units of video data and audio data recorded in one track. OP1 and OP2 indicate the parity of the outer code generated when the video data is product-encoded. The parity of the outer code generated when product coding of audio data is recorded in the audio sector. Each track is divided into equal intervals of 233 bytes, and each one is called a sync block.
[0042]
An example of the length of each data recorded in one track is shown in FIG. In this example, 275 sync blocks + 124 bytes of data are recorded in one track. The video sector is 226 sync blocks. The time length of one track is about 5.6 ms. There is a non-recorded part in the gap between sectors. This gap is called an edit gap, and is provided so that the adjacent sector is not erased when recording is performed in sector units.
[0043]
FIG. 4A is an example of a configuration of an error correction code for video data. Error correction coding is performed for each amount of video data recorded in one track. That is, the video data for one track is arranged in (217 × 226). (250, 226) Reed-Solomon code (outer code) is performed on 226 words (one word is one byte here) aligned in the vertical direction of the array. A parity of 24 words outer code is added. By using an outer code, for example, normal error correction up to 10 words and erasure correction up to 24 words are performed.
[0044]
A 2-word ID is added to 217 words (video data or parity of outer code) aligned in the horizontal direction of the two-dimensional array. Then, (231, 219) Reed-Solomon code encoding (inner code encoding) is performed on (217 + 2 = 219) words aligned in the horizontal direction. As a result, the parity of the inner code of 12 words is generated. By using the inner code, for example, error correction up to 4 words is performed, and an erasure flag for error correction of the outer code is generated.
[0045]
Note that the audio data is encoded with a product code in the same manner as video data, although the amount of data in one track is different.
[0046]
The outer code is encoded, and the inner code is encoded with respect to the encoded output of the outer code including the ID. As shown in FIG. 4B, one sync block having a length of 233 bytes is configured by cutting out data in the encoding direction of the inner code and adding a block sync. That is, a 2-word block sync is added to (2 + 217 + 12 = 231) words in each row of the array of FIG. 4A. On the magnetic tape, data having successive sync blocks is recorded after being scrambled.
[0047]
In each sync block, a 2-byte ID (ID0 and ID1) is inserted after the sync pattern. FIG. 5 shows the configuration of these ID0 and ID1. ID0 indicates a sync block number (FIG. 5A). The sync blocks in one track can be distinguished by the sync block number. ID1 includes a flag Sector a / v for distinguishing audio sectors / video sectors, a track number Track b / a (track Tr0 / 1) for distinguishing adjacent tracks having different azimuths, and segment numbers 0 to 5 Seg information is inserted. Further, compression coding parameters (intra-frame coding / intra-field coding: Frm / Fld, high image quality / standard image quality: HQ / SQ, shuffling pattern SFP) are also inserted into ID1 (FIG. 5B).
[0048]
Further, the first one word (indicated by HD) in the 217-word data in each sync block is a data header. In this data header, a 1-bit sync error flag is inserted together with information indicating data quantization characteristics and the like.
[0049]
Next, a more detailed configuration of the ECC decoder 21 or 22 will be described with reference to FIG. The ECC decoder 53 (or 54) in the 8-head system has the same configuration as that of FIG. 6 except that the input system is doubled. In FIG. 6, reference numeral 60 denotes an IC circuit portion of the ECC decoder. The ECC decoder IC 60 basically has an inner code error correction function, an outer code error correction function, an audio signal processing function, an error count function, and an auxiliary data reading function.
[0050]
Serial data reproduced at a recording rate of 94 Mbps and a clock generated therefrom are input in parallel to the ECC decoder IC 60, input to the S / P converter 61, and converted from serial to parallel data. The width data and the clock divided by 1/8.
[0051]
At this stage, the high-speed 1-bit data is simply reduced to the 8-bit width of 11 Mbps rate, so the breaks in byte units and sync block units are appropriate. The function converts them into regular data strings. The byte break is defined by the bit assignment of the output terminal of the synchronization detection circuit 62, and the sync block break is defined by the strobe pulse STB added by the synchronization detection circuit 62. Next, the system is switched to the system clock 46 MHz by the rate converter 63.
[0052]
The ECC decoder IC 60 has two inputs, a main system and a sub system, in order to support an 8-head system. The above is a circuit for the input through the main system, but the same configuration is provided for the input of the sub system. In order to process the reproduction data of the sub system, an S / P converter 65, a synchronization detection circuit 66, and a rate converter 67 are provided as in the main system. Data packets output from these circuits are mixed into one system by the OR circuit of the mixer 68. A signal that originally came at a rate of 11 Mbps is converted to a rate of 46 Mbps. Therefore, there is a gap between the packets, so that it is possible to mix the sub system data and the main system data. However, if the mixing process is performed randomly, the data of both systems collide, so that the two rate converters 63 and 67 are busy each other with reference to busy and keep the output during the other party's output. Yes. At the same time, a 1-bit flag of sub / main is embedded in the packet so that the origin of the packet can be determined.
[0053]
The input switching pulse SWP is delayed by the timing generator 64 by the delay time of the internal circuit, and information indicating the tape running direction is similarly delayed and embedded in the packet by the rate converters 63 and 67. It is. The rate converters 63 and 67 have a counter that is initialized at the head switching timing and is counted by the strobe pulse STB. By this counter, whether or not the data is in a data non-recording section (hereinafter referred to as a gap). And the information is also included in the packet.
[0054]
The packet output from the mixer 68 is subjected to inner code correction by the inner code decoder 69. In the data from the inner code decoder 69, for example, error correction information indicating whether correction is impossible or not and how many bytes have been corrected are also embedded in the packet and input to the ID reproduction circuit 71. If the inner code decoder 69 cannot correct the inner code, the ID cannot be trusted. However, in the memory controller 74 to be described later, the ID and the order of the outer code correction are determined with reference to the ID, so the ID needs to be reproduced. The function of the ID reproduction circuit 71 reproduces the ID of an uncorrectable packet in anticipation from the IDs of uncorrectable packets before and after. The ID reproduction circuit 71 has RAMs capable of storing three packets in each of the main system and the sub system in order to refer to packets that come later. The RAM is used for conversion to a 16-bit width and start-stop with the video outer code decoder 76.
[0055]
The error correction information obtained from the inner code decoder 69 is input to an error monitor (not shown). In the error monitor, error correction information and other information are encoded together, aggregated into main and sub signals, and output to the outside of the ECC decoder IC60. An error correction state can be observed by D / A converting this output.
[0056]
The data output from the ID reproduction circuit 71 is subjected to descrambling processing, shuffling pattern unification processing, which is the gist of the present invention, and the like by the descrambler 72. The main line data output from the descrambler 72 is stored in an SDRAM (Synchronous Dynamic Random Access Memory) 75 external to the IC via the memory controller 74.
[0057]
At this time, the memory controller 74 performs timing control of data coming from the descrambler 72 and address control for separately writing video data and audio data for each segment to the SDRAM 75.
[0058]
When the main system video data has accumulated one error correction code block (for one track), in order to perform the outer code correction processing by the video outer code decoder 76, the SDRAM 75 is subjected to read control, and the data is transmitted in the outer code direction. Read and send data to the video outer code decoder 76. The memory controller 74 performs writing for returning to the SDRAM 75 again from the data whose outer code processing is completed.
[0059]
The memory controller 74 selects the main / sub data for the data for which the decoding process of the outer code for one track has been completed, reads the data in the inner code direction, and transmits the data to the compression decoder via an ID renumbering circuit (not shown). The ID is changed for the interface and output from the terminal 77.
[0060]
On the other hand, when one field (one error correction coding unit of audio data) is accumulated in the SDRAM 75, the audio data is supplied to the audio processing circuit 78. The audio processing circuit 78 performs predetermined processing such as outer code correction, deshuffling, and error interpolation, and is then converted into serial data and output from a terminal 79.
[0061]
In addition to the above description, an interface 80 with a system control microcomputer (hereinafter referred to as a syscon) is provided so that various settings can be made and error information can be read by the syscon. Further, although not shown, a circuit for extracting video auxiliary data other than video data and a circuit for extracting audio auxiliary data other than audio data are provided, and the extracted auxiliary data is sent to the syscon via the interface 80. . Furthermore, an error counter 73 for counting the number of errors is also provided.
[0062]
Data exchange with the syscon uses a bus 81 having a predetermined bit width in the order of the interface 80, the timing generation circuit 64, the error counter 73, the memory controller 74, the outer code decoder 76, the audio processing circuit 78, and the interface 80. Data is streamed. In each part, necessary data is taken out from the bus 81. In each unit, data to be read by the interface 80 is sent to the bus 81.
[0063]
Next, how the data on the magnetic tape 14 changes until it is written in the SDRAM 75 will be described with reference to FIGS. FIG. 7 shows a recording pattern on the tape. Referring to FIG. 3, as described above, one track is divided into six sectors, and a serial number called ID0 is assigned (hexadecimal notation). A non-recorded portion called an edit gap is provided between the sectors. This edit gap is provided as a margin for preventing destruction of a sector not to be recorded when recording is performed in sector units. Actually, synchronization patterns SY0, SY1, and ID0, ID1 are recorded for synchronization detection with respect to this edit gap. When all sectors are recorded, the rest is filled with a sub Nyquist frequency signal.
[0064]
When this signal is reproduced and the synchronization detection circuit 62 ends the synchronization detection, a data string as shown in FIG. 8 is formed. This is exactly the same as the data string at the time of recording. From the top, the fixed patterns SY0, SY1 used for synchronization detection, ID0, ID1, 217 bytes used for specifying sync blocks, data bodies D0 to D216, for correcting inner codes. The configuration is 12-byte parity ip0 to ip11.
[0065]
This data string is supplied to the rate converter 63 to form a packet as shown in FIG. Since the rate increases, packets that have been continuously connected until then are considered discontinuous. At this time, SY0 and SY1 are removed, and data pid0 and id2 are incorporated instead.
[0066]
pid0 takes the value shown in FIG. FIG. 10A shows the configuration of pid0. This pid0 is an expected value of ID0 that is predicted by the time from the signal SWP indicating head switching. Therefore, it basically takes the same value as ID0. However, since it is unnecessary in the edit gap section, 'ffh' is substituted in this section. This also indicates that the section is an edit gap. In addition, the numerical value attached | subjected with "h" represents that it is a hexadecimal notation. In each figure, the notation “h” is omitted to avoid complication.
[0067]
FIG. 10B shows the configuration of id2. This id2 is the flag OpHead indicating the head switching described above, the flag SubHead used to determine the Sub / Main, the flag TapeDir indicating the tape running direction, and the flags Jump, SY0 and SY1 indicating the DT Jump are correct values. It includes information such as a flag FabSync indicating. The other bits are undecided at this stage and are assigned '0'.
[0068]
Returning to FIG. 9, in the rate converter 63, a null packet 92 is added at the timing of switching between tracks, that is, at timings 90 and 91 (see FIG. 7) based on the switching pulse SWP. Id2 is transmitted by the Null packet 92. As shown in FIG. 9, the Nul packet 92 is a short packet consisting of 2 bytes, and can be specified by the head pid0 being “00h”.
[0069]
Next, the inner code is corrected by the inner code decoder 69 to obtain the data string shown in FIG. ip0 to ip11 are removed because they become unnecessary after the inner code correction process is completed, and are filled with “0” instead. In addition, the result of the inner code correction is c1ef, which is incorporated into the packet. FIG. 10C shows the configuration of c1ef. As described above, c1ef includes the actual correction number TtlERR by the inner code correction consisting of 3 bits, the flag Error indicating the uncorrectability, and the flag FabSync copied from id2.
[0070]
In the subsequent ID reproduction circuit 71, the width of the data string is set to 16 bits in order to match the bit width of the SDRAM 75. At the same time, in order to secure time for the memory controller 74 to calculate the address of the SDRAM 75, a process of extending the periods of ID0 and ID1 is also added. This is done with reference to the signal busy output from the memory controller 74. FIG. 12 shows a packet output from the ID reproduction circuit 71. As shown in FIG. 12, pid0 and id2 arranged at the head of the packet are transferred to the rear end side of the packet and can be written in the SDRAM 75.
[0071]
Here, a flag called ReqC2 is added to id2. This is a flag for determining whether or not the outer code correction can be omitted. The ID reproduction circuit 71 detects the continuity of ID0. The ID reproduction circuit 71 has a circuit for obtaining ID0 of an error from ID0 of a previous packet. This circuit output can be considered as an expected value of ID0. If ID0 that has been normally inner code corrected is different from the expected value, it is assumed that there is a packet loss or duplication. In this way, the continuity of ID0 is detected, and the detection result is put on ReqC2.
[0072]
The data D0 to D216 are scrambled by the ECC encoder 5 by, for example, an M sequence in order to flatten the recording frequency distribution during recording. These data are returned to their original values via the descrambler 72. FIG. 13 shows a packet output from the descrambler 72. In the descrambler 72, a CRCC (Cyclic Redundancy Check Code) for checking the SDRAM 75 is embedded at the rear end side. This packet is stored in the SDRAM 75 via the memory controller 74.
[0073]
Next, the descrambler 72 will be described. FIG. 14 schematically shows an example of the configuration of the descrambler 72. The descrambler 72 is supplied with setting information and the like output from the syscon via an error counter 73. The setting information from the syscon is represented as “from EC” in FIG. Similarly, information sent to the syscon via the error counter 73 and the interface 80 is represented as “to EC”.
[0074]
A strobe signal STB is supplied to the descrambler 72 together with the packet. The packet is output via the descrambling circuit 100, the SFP unification circuit 101, and the CRCC circuit 102. On the other hand, pid0 and signal STB extracted from the packet are supplied to the controller 103. In addition, setting information from the system controller is supplied to the controller 103. The controller 103 controls the descrambler 72 as a whole. Based on the signal STB supplied by the controller 103 and the setting information from the system controller, timing signals and various status signals required in the descrambler 72 are provided. Is generated. The timing signal is supplied to the descrambling circuit 100, the SFP unification circuit 101, the CRCC calculation circuit 102, and the error count circuit 104. Various status signals are supplied to the SFP unification circuit 101 and the error count circuit 104.
[0075]
In the descrambler circuit 100, the packet is scrambled by the M series with ID0 as an initial value. For example, the scramble is released by taking the exclusive OR of the M series starting from ID0 and data using an ExOR circuit.
[0076]
The output of the descrambling circuit 100 is supplied to the SFP unification circuit 101 and also supplied to the error count circuit 104. The error count circuit 104 extracts various error information from the supplied packets, summarizes them, and supplies them to the error counter 73. On the other hand, the SFP unification circuit 101 unifies the SFP for the supplied packet. The processing in this SFP unification circuit 101 will be described later. The output of the SFP unification circuit 101 is output from the descrambling circuit 72 via the CRCC calculation circuit 102.
[0077]
The error information extracted by the error count circuit 104 is supplied to the OOPS determination circuit 105 that determines whether or not the outer code correction is necessary. The OOPS determination circuit 105 is supplied with syscon setting information OOPS according to conditions corresponding to the reproduction quality as information set by the syscon. Based on the syscon setting information OOPS and the A error information supplied from the error count circuit 104, a flag ReqC2 is generated. This flag ReqC2 is supplied to the CRCC calculation circuit 102 and reflected in the flag ReqC2 of id2.
[0078]
Here, a data recording format for the magnetic tape will be described in detail. FIG. 15 shows the track pattern on the tape for two frames. Each track has the recording pattern shown in FIG. In FIG. 15, one track is represented by one band, and the aspect ratio is enlarged in the horizontal direction. Two adjacent tracks having different azimuths form one set and are called a segment (Seg). In this figure, Seg1, Seg2, Seg3,... Are recorded in this order from the left, and one frame is composed of 12 tracks (6 segments) for convenience.
[0079]
Each track is divided into sectors of OP1 (Video Outer Parity 1), V1 (Video Data 1), A1 (Audio Data 1), A2, A3, A4, V2, and OP2, and the non-recorded portion is narrowed in each gap. It is. The gap formed by the non-recorded portion is called “Edit Gap” and is provided so as not to erase the adjacent sector when recording is performed in sector units.
[0080]
Each track is divided at equal intervals every 233 bytes. Each of the divided parts is referred to as a sync block. The meaning of the sync block is represented by LSB of ID1 and 8 bits of ID0. The LSB of ID1 indicates whether the sync block is for audio data or video data. ID0 corresponds to a serial number in the sector and has a value written on the scale at the left end of FIG.
[0081]
In FIG. 15, one AUX (Auxiliary) sync block is distributed at the end of the sector V1 in the even segment and at the head of the sector V1 in the odd segment. In this AUX sync block, a compression parameter called a 24-byte waiting factor is recorded immediately after ID1. In this AUX sync block, XID1 whose upper 3 bits are the same as ID1 is recorded, and an AUX portion including a time code and a user code is recorded in 182 bytes.
[0082]
As described above, the position of the AUX sync block in the track changes depending on the segment number. Therefore, there are two types of data body ranges in the V1 sector. This is 0Dh to 7Ah for the even numbered segment and 0Eh to 7Bh for the odd numbered segment. As can be seen from FIG. 15, the range of the data body is determined only by the segment number regardless of the shuffling pattern SFP and the track number. On the other hand, in the V2 sector, the data body is uniformly arranged in the range of F80h to F2h.
[0083]
In each segment, the track is distributed to tracks Tr0 and Tr1 according to the azimuth angle. That is, a track having the same azimuth angle is, for example, a track Tr0, and a track having another azimuth angle is a track Tr1.
[0084]
Next, a process until the digital video signal supplied from the input terminal 1 is recorded on the magnetic tape 14 will be schematically described.
[0085]
As shown in FIG. 16A, the 4: 2: 2 digital video signal input to the input terminal 1 has a pixel configuration in which the luminance signal Y is 1920 × 1080 pixels and the color difference signals Pb and Pr are 960 × 1080 pixels, respectively. . This is band-compressed to 3: 1: 1 by the input filter 2 so that the luminance signal Y is 1440 × 1080 pixels and the color difference signals Pb and Pr are 480 × 1080 pixels, respectively, as shown in FIG. 16B.
[0086]
The band-compressed digital video signal is further distributed to two systems at the output of the input filter 2. This signal is shown in FIG. 17A. The luminance signal Y is distributed to luminance signals Y0 and Y1 each consisting of 720 × 1080 pixels. Similarly, the color difference signal Pb is divided into color difference signals Pb0 and Pb1 each consisting of 480 × 1080 pixels. Similarly, the color difference signal Pr is divided into color difference signals Pr0 and Pr1 each consisting of 480 × 1080 pixels. Signals Y0, Pb0, and Pr0 correspond to one piece azimuth, and signals Y1, Pr1, and Pr1 correspond to the other piece azimuth.
[0087]
This distribution is called a subsample. This is a method for separating the data into two systems for each sample, separating them into two highly correlated images, and interpolating the other when one of them is crushed due to an error during reproduction. The data is distributed, for example, by distributing odd-numbered pixels and even-numbered pixels to different systems.
[0088]
The two systems of signals thus obtained are supplied to the BRR encoders 3 and 4, respectively. In the BRR encoders 3 and 4, the supplied data is first divided into blocks of 8 × 8 samples, and this is used as a unit for compression encoding. This unit block is referred to as a DCT block. FIG. 17B shows a state where the subsampled data is divided into DCT blocks. For example, in the luminance signal Y0, 720 × 1080 pixels are divided every 8 × 8 pixels to form a 90 × 135 DCT block.
[0089]
Further, in the BRR encoders 3 and 4, since errors do not concentrate on the screen, a shuffling process for scattering the DCT blocks is performed. The shuffling process is performed in units of shuffling blocks (SHB) composed of 2 × 3 DCT blocks.
[0090]
FIG. 18 shows an example of the distribution of a certain sync block on the screen. Each sync block includes a luminance signal Y of 9 DCT blocks and color difference signals Pb and Pr for 3 DCT blocks. As shown in FIG. 18, one sync block is distributed for each DCT block in each subsample. That is, in each of the sub-samples, the luminance signal Y is distributed at nine locations and the color difference signals Pb and Pr are distributed at three locations.
[0091]
In FIG. 18, each point indicating that data for one sync block is distributed and arranged belongs to one shuffling block. The shuffling block is composed of 2 × 3 DCT blocks, and the data of the other five sync blocks belong to each shuffling block as well. One shuffling block is composed of data of sync blocks (DCT blocks included therein) having different ID0 values on tracks having different segment numbers.
[0092]
FIG. 19 shows an example of the correspondence between the value of ID0 and the segment number in the shuffling block. In this example, for example, the shuffling block at position A is a sync block whose segment number 0 and ID0 value are indicated by F12h, a sync block whose segment number 1 and ID0 value are indicated by FCBh, segment number 2 and ID0 value is FDAh 6 of the sync block indicated by, segment number 3, sync block indicated by ID0 value F22h, sync block indicated by segment number 4 ID0 value F30h, and sync block indicated by segment number 5 ID0 value FE9h It consists of data of DCT blocks included in one sync block.
[0093]
The purpose of shuffling is to distribute errors that occur intensively on the screen as described above. Therefore, in this way, DCT blocks included in the same shuffling block are arranged at different positions in each segment, and ID0 also takes various values.
[0094]
The shuffling block has six arrangements. FIG. 20 shows the arrangement inside the shuffling block. In FIG. 20, s1 to s6 indicate segment numbers, respectively. FIG. 20A shows the shuffling block at the position indicated by A in FIG. 18 in the shuffling pattern SFP0. FIG. 20B shows the shuffling block at the position indicated by B in FIG. FIG. 20C shows a shuffling block at a position corresponding to the position A of the shuffling pattern SFP0 in the shuffling pattern SFP1.
[0095]
In FIG. 20, as illustrated in FIG. 20D, a small square indicates a DCT block, and six DCT blocks are gathered to form a shuffling block. In FIG. 20A, FIG. 20B, and FIG. 20C, the range surrounded by the solid line indicates the shuffling block. A range surrounded by a thick line corresponds to the shuffling block indicated by A and B in FIG.
[0096]
The shuffling block of shuffling pattern SFP0 shown by A in FIG. 18 is recorded at the positions of Seg0 and ID0 12h on the tape. On the other hand, the shuffling block of shuffling pattern SFP1 indicated by B in FIG. 18 is also recorded on the tape at the positions of Seg0 and ID0 12h. That is, even if the position on the tape is the same Seg0, ID0 12h, the shuffling patterns SFP0 and SFP1 are completely different blocks. In the shuffling pattern SFP1, the same block as A in FIG. 18 is Seg3 and ID0 8Ah shown in FIG. 20C.
[0097]
In the SFP toggle described above, the DCT blocks corresponding to the same position distributed by the sub-sample are recorded and reproduced at two positions with different azimuth angles and at different positions on the tape. Has been. For this reason, the two DCT blocks obtained by sub-samples have a very small correlation with each other, and even if one of the DCT blocks cannot be error-corrected, there is a high possibility that the other block can perform error correction. Therefore, even if an uncorrectable error occurs due to, for example, a scratch in the longitudinal direction of the tape, it can be interpolated.
[0098]
Shuffling is sorting in units of DCT blocks, and two patterns are selected only by the SFP flag indicating the distinction between shuffling patterns SFP0 and SFP1. Therefore, for example, as shown in FIG. 20, on the tape, the image recorded in the shuffling pattern SFP1, Seg3, ID0 8Ah of the track Tr0 and the shuffling pattern SFP0, Seg0, ID0 12h of the track Tr0 are recorded. The recorded image completely matches up to the pixel. Therefore, even if the latter sync block IDs 0 and 1 are replaced with the former, no inconvenience is caused as an image. In the present invention, this is utilized to unify the shuffling pattern SFP.
[0099]
In FIG. 15 described above, in order to show a state where one shuffling block is arranged on the tape, each track is marked. For example, in the track Tr0, the left half, that is, the first frame is the shuffling pattern SFP0, and the right half, that is, the next frame is the shuffling pattern SFP1. The above-described sync block is filled. The corresponding block is filled with the same color.
[0100]
For example, a sync block of ID0 12h is arranged in the sector V1 at the left end (Seg0, track Tr0) of the first frame. The corresponding sync block is arranged in Seg0 and sector V1 of the next frame, but the track is set to be opposite azimuth to the track Tr1 and the block arranged in the first frame. As can be seen from FIG. 15, this relationship is similarly maintained in the other sync blocks.
[0101]
In order to realize the SFP conversion, the following processes are required: (1) SFP flag conversion, (2) segment conversion, and (3) sync block position conversion. The conversion of the SFP flag (1) is a process of setting SFP0 only when the shuffling pattern SFP is 1. For example, in the example of FIGS. 20A and 20C described above, the SFP flag is converted from SFP1 to SFP0, and Seg3 is converted to Seg0. Also, ID0 is converted from 8Ah to 12H. Of course, similar conversion is necessary for other sync blocks.
[0102]
The conversion of the segment number Seg (2) will be described. Regarding the segment number Seg, as can be seen from FIGS. 20A and 20C, the shuffling pattern SFP1 to SFP0 is converted from Seg3 to Seg0, Seg2 to Seg1, Seg4 to Seg3, Seg5 to Seg2, and Seg1 to Seg4. And Seg0 to Seg5, respectively.
[0103]
The sync block position conversion in (3) will be described. ID0 is arranged so as to maintain an equal interval. In the sector V2, 8Ah is converted to 12h, 8Bh is converted to 13h, and so on. Thus, when ID0 is monotonously increased, the end of sector V2 is reached. Subsequently, from the beginning of the sector V1, 0Eh is converted into 85h, 0Fh is converted into 86h, and so on.
[0104]
Furthermore, in this embodiment, sector V2 is longer than sector V1. Therefore, the head of sector V2 needs to be converted to the end of sector V2, such as 80h to EEh,..., 84h to EEh.
[0105]
In addition, since the position of the AUX sync block changes according to the segment number Seg, there are two types of conversion between the sector V1 and the sector V2. The reason that only two conversions are required is that the position of the AUX sync block is defined only by the even / odd segment number Seg, and the conversion of the segment number Seg is always inverted between even and odd. .
[0106]
Such shuffling pattern SFP conversion is performed by the SFP unification circuit 101 configured in the descrambler 72 shown in FIG. In the format, the initial value of scramble is ID0, and descrambling is performed using ID0. Therefore, if this shuffling pattern SFP conversion process is performed at a stage prior to the descrambling process, ID0 is converted, and the descrambling process cannot be performed correctly, causing a problem. Of course, it is meaningless unless it is a stage before SDRAM75. Therefore, in this embodiment, the SFP unification circuit 101 is placed immediately after the descrambling circuit 100.
[0107]
FIG. 21 is a flowchart of the segment number Seg (track number) conversion process in the SFP unification circuit 101. The determination in this flowchart can be determined based on ID1 arranged after ID0 at the head of the sync block. Based on this determination, the segment number Seg is converted and ID1 is converted.
[0108]
First, in the first step S10, it is determined whether or not the flag SFP indicating the shuffling pattern SFP is 0 and whether the data is audio data. If it is 0 and the sync block is the shuffling pattern SFP0 or audio data, no processing is performed. On the other hand, if it is determined in step S10 that the flag SFP is 1, the above-described conversion processing of the segment number Seg is performed based on the processing from step S11 to step S23.
[0109]
FIG. 22 shows a flowchart of the conversion process of ID0 (position on the track). In this flowchart, a determination is made based on ID0 and ID1, and ID0 is converted. This processing is very complicated as described above, and conversion is selected by various inequality comparisons for various condition judgments. For this reason, this conversion cannot be processed in one cycle. Therefore, in this embodiment, the process is configured in two cycles, and the addend add is selected based on the even and odd values of ID0 and segment number Seg in the first cycle, and the addend add is added to ID0 in the second cycle. Is added.
[0110]
First, in the first step S30, it is determined whether or not the flag SFP indicating the shuffling pattern SFP is 0 and whether the data is audio data. If it is 0 and the sync block is the shuffling pattern SFP0 or audio data, the process proceeds to step S31 and the addend add is set to 00h. That is, nothing is added to ID0.
[0111]
On the other hand, if it is determined in step S30 that the sync block is the shuffling pattern SFP1 and not audio data, the process proceeds to step S32. In step S32, it is determined whether the segment number Seg is an even number or an odd number. If it is determined that the number is even, the process proceeds to step S33, and a determination is made based on the value of ID0. If it is determined in step S33 that the value of ID0 is 0 Dh or more and 7 Ah or less, the process proceeds to step S34, and 73h is selected as the addend add. If it is determined in step S33 that the value of ID0 is not in the above range, the process proceeds to step S37.
[0112]
On the other hand, if it is determined in step S32 that the segment number seg is an odd number, the process proceeds to step S35, and it is determined whether the value of ID0 is in the range of 0Eh or more and 7Bh or less. If there is, 72h is selected as the addend add in step S36. On the other hand, if it is determined in step S35 that ID0 is not within the above range, the process proceeds to step S37.
[0113]
In step S37, it is determined whether or not the value of ID0 is in the range of 80h or more and 84h or less. If it is in this range, 6Eh is selected as the addend add in step S38. On the other hand, if it is determined in step S37 that ID0 is not within the above range, the process proceeds to step S39.
[0114]
In step S39, it is determined whether or not the value of ID0 is within a range of 85h or more and F2h or less. If it is within this range, the process proceeds to step S40. In step S40, whether the segment number Seg is even or odd is determined again. If it is even, 89h is selected as the addend add in step S41, and if it is odd, the addend add is 88h in step S42. Is selected. On the other hand, if it is determined in step S39 that the value of ID0 is not within the above range, 00h is selected as the addend add in step S43.
[0115]
The process up to the selection of the addend add in steps S31, S34, S36, S38, S41, S42, and S43 is the first cycle. In the first cycle, the flow up to here is processed at once. When the addend add is selected in the first cycle, the addend add is added to the current ID0 value in the second cycle shown in step S44. ID0 to which the addend add is added is the value of ID0 after conversion.
[0116]
Thus, the packets whose ID 0 and ID 1 are converted by the SFP unification circuit 101 are output from the descrambler 72 via the CRCC calculation circuit 102 and supplied to the memory controller 74. Then, the packet is written to the SDRAM 75 by the address control of the memory controller 74 based on the converted ID0 and ID1. Packets are read from the SDRAM 75 with regular timing and order. The read packet is output from the terminal 77 to the subsequent stage via the memory controller 74. Of course, packets overwritten during the period from writing to reading to the SDRAM 75 are lost and are not output.
[0117]
It should be noted that the sync block arrangement in the track is different from that at the time of recording by the processing in the SFP unifying circuit 101. Therefore, the outer code correction using the outer code parity added at the time of recording cannot be performed. Therefore, in the reproduction other than the high-speed reproduction, for example, the normal reproduction in which the reproduction is performed at the same speed as the recording, the above-described conversion process in the SFP unification circuit 101 is stopped.
[0118]
This is done by controlling a syscon circuit (not shown) built in the error counter 73. A control signal from the syscon circuit is supplied to the controller 103 of the descrambler 72, and the processing of the SFP unification circuit 101 is controlled by the controller 103. Also, the processing of the SFP unification circuit 101 can be forcibly turned on / off.
[0119]
FIG. 23 conceptually shows the result of the SFP unification process described above. In FIG. 23, an actual display on the screen is imitated. FIG. 23A and FIG. 23B show examples of display by shuffling patterns SFP0 and SFP1 for one sync block, respectively. That is, the points shown in FIGS. 23A and 23B are for the same sync block. Here, it is assumed that one sync block includes a 3DCT block. Also, the position is different from the actual one.
[0120]
Conventionally, the shuffling pattern SFP is ignored for the SDRAM 75, and the packet is written based only on the ID number. Therefore, a pixel that is overwritten and erased by other data sent later is generated. It was. An example of this is shown in FIG. 23C. In the example of FIG. 23C, the shuffling pattern SFP1 is reproduced immediately before transmission of the packet to the BRR decoder. The data of the shuffling pattern SFP1 is overwritten and erased by the data of the reproduced shuffling pattern SFP1.
[0121]
FIG. 23D is an example when the SFP unification process according to the present invention is performed. By converting the ID number based on the flag SFP, the pixel is overwritten, and data that is not utilized can be reduced. Therefore, as shown in FIG. 23D, many DCT blocks can be left.
[0122]
Of course, there are DCT blocks that are erased by this conversion process. However, since the block was captured before the block to be overwritten, and the main purpose of high-speed playback is usually to search for images, it would be more convenient for old images to disappear. I can say that.
[0123]
Also, depending on the tape speed, this process may not improve at all, but at least does not cause harm. Moreover, this is only the case of a very accurate even-numbered speed, and it is almost impossible from the viewpoint of realistic tape running characteristics. Therefore, by performing this process, it can be said that the update rate of the playback video during high-speed playback can be improved reliably.
[0124]
In the above description, the present invention is applied to the case where there are two types of shuffling patterns SFP, but this is not limited to this example. That is, the present invention can be applied to a case where there are more shuffling patterns, and in that case, it can be expected that the effect will be higher. For example, if the number of shuffling patterns is set to an odd number, the effect can be obtained even in the case of even multiple speeds. Similarly, as the number of shuffling patterns is increased, the image update rate is improved.
[0125]
In the above description, the shuffling pattern SFP is unified with the pattern SFP0, but may be unified with other patterns.
[0126]
In addition, the present invention is similarly applied to a non-compressed configuration or a configuration in which the compression rate is different from that of this embodiment, a configuration that does not employ DCT, or a configuration that does not employ a sub-sampling method. The same effect can be obtained.
[0127]
Furthermore, this is not limited to the case where the unit of compression is a frame, and even in a configuration in which compression encoding is performed in units of fields or in units of several frames, as long as the shuffling pattern is switched and recorded for each unit, this implementation is performed. The same effect as one form can be expected.
[0128]
Furthermore, the division method on the screen such as the DCT block, and the grouping and arrangement of the blocks are not limited to this example.
[0129]
The format settings such as data assignment within the sync block, the number and number of sync blocks on the track, and the number of segments in the frame are not limited to those described above. Similarly, the circuit configuration is not limited to the above-described configuration.
[0130]
Further, if it is possible to associate the outer code parity after the ID number conversion by some method and correct the outer code after the conversion, this processing can be performed even during normal reproduction. . In this case, processing in the BRR decoder and circuit can be reduced.
[0131]
Furthermore, in the above description, the segment number Seg conversion (ID1 conversion) and ID0 conversion have been described as being performed in different configurations, but this is not limited to this example, and these processes are combined into one configuration. It is also possible to do this. In the above-described configuration, ID0 conversion is performed over two cycles. However, if the circuit delay is small, it can be performed in one cycle. Needless to say, it is also possible to adopt a configuration in which processing is performed by taking more cycles.
[0132]
【The invention's effect】
As described above, according to the present invention, ID0 and ID1 are converted to unify a plurality of shuffling patterns and avoid overwriting with different data in the sync block in the SDRAM during high-speed playback. Therefore, there is an effect that the update rate of the image at the time of high-speed reproduction can be improved up to nearly twice by adding a small amount of configuration.
[0133]
Further, according to this embodiment, the processing is divided into the conversion of the position (ID0) on the track and the conversion of the track number (segment number Seg), and each is performed as an independent configuration. It is not necessary to have a configuration for converting ID0, and the circuit scale can be reduced.
[0134]
Furthermore, according to this embodiment, since the AUX sync block is excluded from the conversion target, there is an effect that different information can be recorded for each track.
[0135]
Furthermore, in this embodiment, since the conversion of the position (ID0) on the track is processed in two stages, the processing speed of the circuit can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an example of the configuration of a recording / reproducing system of a digital VTR using a four-head system applicable to the present invention.
FIG. 2 is a block diagram showing an example of a configuration of a recording / reproducing system of a digital VTR using an eight head system applicable to the present invention.
FIG. 3 is a schematic diagram showing a format of one track formed on a magnetic tape.
FIG. 4 is a schematic diagram for explaining an error correction code by a product code.
FIG. 5 is a schematic diagram illustrating an example of a configuration of ID0 and ID1.
FIG. 6 is a block diagram illustrating an example of an IC circuit of an ECC decoder.
FIG. 7 is a schematic diagram showing a recording pattern on a magnetic tape.
FIG. 8 is a schematic diagram for explaining a change in data inside the ECC decoder;
FIG. 9 is a schematic diagram for explaining a change in data in the ECC decoder;
FIG. 10 is a schematic diagram for explaining pid0, id2, and c1ef.
FIG. 11 is a schematic diagram for explaining a change in data in the ECC decoder;
FIG. 12 is a schematic diagram for explaining a change in data inside the ECC decoder;
FIG. 13 is a schematic diagram for explaining a change in data inside the ECC decoder;
FIG. 14 is a block diagram schematically illustrating an example of a configuration of a descrambler.
FIG. 15 is a schematic diagram showing a track pattern on a tape for two frames.
FIG. 16 is a schematic diagram for explaining processing until a digital video signal supplied from an input terminal is recorded on a magnetic tape;
FIG. 17 is a schematic diagram for explaining processing until a digital video signal supplied from an input terminal is recorded on a magnetic tape; It is a figure for demonstrating subsampling.
FIG. 18 is a schematic diagram for explaining processing until a digital video signal supplied from an input terminal is recorded on a magnetic tape; It is a figure for demonstrating a shuffling block.
FIG. 19 is a schematic diagram illustrating an example of a correspondence between a value of ID0 and a segment number in a shuffling block.
FIG. 20 is a schematic diagram illustrating an arrangement inside a shuffling block.
FIG. 21 is a flowchart of segment number Seg conversion processing;
FIG. 22 is a flowchart of ID0 conversion processing;
FIG. 23 is a diagram conceptually showing a result of the SFP unification process.
FIG. 24 is a schematic diagram illustrating an example of a relationship between a magnetic head and a track during high-speed reproduction.
FIG. 25 is a schematic diagram illustrating an example of a relationship between a magnetic head and a track during high-speed reproduction.
[Explanation of symbols]
14 ... Magnetic tape, 21, 22, 53, 54 ... ECC decoder, 60 ... ECC decoder IC, 63, 67 ... Rate converter, 69 ... Inner code decoder, 71 ... ID reproduction circuit, 72 ... descrambler, 73 ... error counter, 74 ... memory controller, 75 ... SDRAM, 76 ... video outer code decoder, 100 ... descrambling circuit, 101 ..SFP unified circuit, 103 ... Controller

Claims (8)

In a digital video signal processing apparatus for handling a digital video signal in which pixel data is shuffled with a plurality of shuffling patterns, and the plurality of shuffling patterns are changed for each image unit and recorded on a magnetic tape.
Unifying means for unifying a plurality of shuffling patterns applied to the digital video signal so as to change for each image unit into one shuffling pattern;
A memory for storing the digital video signal output from the unifying unit;
A digital video signal processing apparatus comprising: memory control means for reading the digital video signal stored in the memory in an original order. The digital video signal processing apparatus according to claim 1, wherein
The digital video signal processing apparatus characterized in that the unification processing by the unification means is performed only during variable speed reproduction in which reproduction is performed at a tape speed different from the tape speed at the time of recording. The digital video signal processing apparatus according to claim 1, wherein
The digital video signal processing apparatus characterized in that the unification unit performs the unification process by independently converting the position information on the track and the track number for each sync block. The digital video signal processing apparatus according to claim 3,
A digital video signal processing apparatus characterized in that the conversion processing of position information on the track is switched in accordance with the position of the auxiliary sync block. The digital video signal processing apparatus according to claim 3,
A digital video signal processing apparatus characterized in that the track number conversion process is not performed for the auxiliary sync block. The digital video signal processing apparatus according to claim 3,
The position information on the track is converted by a first process for selecting a value corresponding to the input sync block and a value corresponding to the input sync block selected in the first process. And a second process of adding to the value indicating the position information of the sync block. In a digital video signal processing method for handling a digital video signal in which pixel data is shuffled by a plurality of shuffling patterns, and the plurality of shuffling patterns are changed for each image unit and recorded on a magnetic tape,
A step of unifying a plurality of shuffling patterns applied to a digital video signal so as to change for each image unit into one shuffling pattern;
A memory for storing the digital video signal output from the unification step;
And a memory control step for reading out the digital video signal stored in the memory in an original order. A digital video signal processing apparatus that handles digital video signals recorded on magnetic tape in which pixel data is shuffled by a plurality of shuffling patterns and the plurality of shuffling patterns change for each image unit is used. In the digital video signal reproducing apparatus,
Reproducing means for reproducing a digital video signal recorded from a magnetic tape in which pixel data is shuffled with a plurality of shuffling patterns, and the plurality of shuffling patterns are changed for each image unit;
Error correction means for performing error correction of the digital video signal reproduced by the reproduction means;
Unifying means for unifying the plurality of shuffling patterns of the digital video signal error-corrected by the error correcting means into one shuffling pattern;
A memory for storing the digital video signal output from the unifying unit;
A digital video signal reproducing apparatus using a digital video signal processing apparatus, comprising: memory control means for reading out the digital video signals stored in the memory in the original order and outputting them as reproduced signals .

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