JPS5953640B2 - Storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device, and particularly to a high-speed storage device for a main storage device of an electronic computer or the like.

Conventionally, in high-speed, large-capacity storage devices such as the main memory of information processing devices such as computers, error correction codes such as Hamming codes have been added to improve the reliability of the information stored therein. It was used as For example, if the number m of Hamming codes is the number of information codes, then ≦2m−m
-1, and in this type of storage device with a small number of information codes, the ratio of the number of error correction codes increases, which has the disadvantage of impairing economic efficiency. An object of the present invention is to reduce the ratio of the number of error correction codes to the number of information codes and to reduce the ratio of the number of error correction codes to the number of information codes by adding error correction codes to the information bits of a plurality of addresses in a distributed manner to each address. A part of the error correction code added to the bit is used to determine whether there is an error in the read memory information. If there is no error, it is read out as is, and if there is an error, all of these multiple addresses are read out. The object of the present invention is to provide a storage device capable of reading and correcting the data.

The present invention includes data, a first check bit, and a second check bit as a set of information, and the first check bit of each set is is created, and a second check bit of each set is created by all of the data belonging to each set and the first check bit. Addressing means for specifying an address; and after reading the set of information using an addressing signal output from the addressing means, the second check bit is used for all bits of the set of information. Perform a parity check to detect whether there is a 1-bit error1
a bit error detection circuit, and if an error is detected by this detection, reads information of a plurality of sets of the group to which this set belongs from the storage means, and detects a 1-bit error using the first and second check bits of this group; This configuration is characterized by including an error correction circuit for correcting errors.

The principle of the present invention will be explained using Table 1 and FIG.

D at addresses O and 1 of the storage device, respectively.

, Dl, D2, D3 and D4, D5, D6, D7 each 4
It is assumed that bit information codes are stored. Especially D. −
When D3 and D4 to D7 are given as 1 and 2 in FIG. 1, respectively, the error correction code POPlP2P3P is obtained by calculating the parity of each row of the matrix from these information codes using the parity check matrix in Table 1.
4P5 is created. This is predetermined data, and can be created using the formula shown below. This is given to the storage device and has the sign e
indicates exclusive OR.

First, in Table 1 And for Table 2, In Table 3, It can be obtained using the following formulas.

That is, the code surrounded by O in Table 1 is the error correction code P.

- Made as P5. P to DO-D7. -P5 is added to generate 3 in Figure 1, 4 and 5 in Figure 1
are written to address O and address 1, respectively. Then 0
When the address is read out, the stored content as shown in 6 in Figure 1 is read out, and if the parity of the first row, that is, the row of C2, is determined using Table 1, it becomes O as shown in 8 in Figure 1. Information code D at 6 in FIG.

It is found that there is no error in ~D3, and an information code such as 7 in FIG. 1 is read out. On the other hand, as shown at 9 in FIG. 1, for example, D. When the stored information with an error is read from address O, the parity of row C2 in Table 1 becomes 1, as shown in 10 in FIG. 1, and the stored information shown in 9 in FIG. It turns out that there is an error inside. In such a case, DO-D7 and P are read out by reading out the stored information at address 1, indicated by 11 in FIG. -P5
Using Table 1, calculate the parity of each row to find the syndrome C22C5raCOraClyC3raC4) As shown in 12 in Figure 1, C2, CO, and Cl are 1, so from Table 1, D. It turns out that there is an error in 1 in Figure 1.
D like 3. Errors are corrected and corrected information is obtained. As is clear from the above explanation, the storage information D at address 0.

-D3, PO-P2 and storage information D4 to D7 at address 1,
By calculating the parities C2 and C5 for P3 to P5, respectively, it is determined whether there is a 1-bit error. If there is no error, the address in question is read out as is; if there is an error, both addresses are read out and By obtaining the syndromes C2, C5, CO, Cl, C3, and C4, the ratio of the error correction code to the information code can be reduced by performing 1-bit correction and reading. Table 2 shows D to an even address. -D7
Error correction code P in the case where D8 to Dl5 are stored at odd addresses.

- An example of a parity check matrix showing a method of generating error correction code P. ,P,,P2 and P3,P4,P
5 has information code D at even and odd addresses, respectively. -D
, and D8 to D, . Also, Table 3 shows D to an even address. ~D,5 to odd address D,6
Error correction code P in the case where D3l is stored. −
This is an example of a parity check matrix showing how to generate an error correction code P. -P3 and P4-P7 are each D
. - Dl5 is stored at an even address, and D, 6 to D3l are stored at an odd address. In addition, P and P5 in Table 2
are each D.

~D7, PO, P2 and D, ~Dl,, P3, P4 are created, and P and P in Table 2 are respectively D
O5Dl59PO″P2 and Dl6ゝD3lPP4″P
6, and is similar to the case explained in Table 2, in which case the error correction code surrounded by O is finally created. Compared to the Hamming code, if the parity check matrix of Table 2 or Table 3 is added and storage information is stored in two addresses, the number of error correction codes will be reduced by 1 bit in both cases.

Next, one embodiment of the present invention will be described with reference to FIG.

Referring to FIG. 2, one embodiment of the present invention takes k-bit write information 70 as input, a write register 50 holding write information of even addresses, write information 70 as input,
a write register 51 that holds write information of odd addresses;
Write information outputs 72 and 73 of write registers 50 and 51
as an input, an error correction code 74 written to an even address and an error correction code 75 written to an odd address.
A 1-bit error correction code generation circuit 52 that outputs a code 74 written to an even address and a write register 50
A multiplexer 53 that outputs the output 72 of the code 72 or the code 75 written to an odd address and the output 73 of the write register 51 as an error correction code 76 and write information 77, and inputs 76 and 77 to a specified address. Error correction code 78 and read information 79
A memory circuit 54 outputs the error correction code 78 and read information 79 read from even addresses, and a read information register 55 holds them, inputs 78 and 79 read from odd addresses. The error correction code and read information 80 read from the even address which is the output of the read information registers 56 and 55 that hold these, and the error correction code and read information 81 read from the odd address which is the output of the register 56. A signal 84 indicating whether there is a 1-bit error in this information 80 or 81.
An error checking circuit 57 which outputs the above information 80 and 81 and outputs the syndrome code 82, a syndrome generation circuit 58 which takes the syndrome 82 as input, decodes the error position, and outputs a signal 83 specifying the error position. The position decoding circuit 59 inputs the error position designation signal 83 and the read information from among the information 80 and 81, corrects the error in 80 or 81 by the error position designation signal 83, and stores it at the designated even address or odd address. Information 85
an error correction circuit 60 that outputs an address and read or write command input signal 71 as well as an output signal 8 of the error check circuit.
4 as an input, signals 86 and 87 that set the write registers 50 and 51, respectively, and a signal 88 that switches whether the outputs 76 and 77 of the multiplexer 53 are written to an even address or an odd address. A signal 89 causes writing or reading to be performed at the specified address of
Signal 90 to set 9 and odd addresses 78 and 7
Signal 91 to set 9, input 80 of error check circuit 57
or 81, a signal 93 that outputs the output 83 of the error position decoding circuit 59, and an output 85 of the error correction circuit 60, among the even address information and the odd address information. and a control circuit 61 that outputs a signal 94 specifying which one to give.

Next, its operation will be explained.

First, addresses 2m (even addresses) and 2m+ of the memory circuit 54
When writing arbitrary k-bit information to address 1 (odd address), specify address 2m by input signal 71 and issue a read command. The write information initially given as input 70 is The write information set in register 50 by signal 86 and then given as input 70 is set in register 51 by signal 87, and these outputs 72 and 73 are given to error correction code generation circuit 52 to generate even addresses and Error correction codes 74 and 75 are obtained which are respectively stored together with the write information stored at odd addresses, and the circuit 52 is configured as shown in Table 1, for example.
Error correction codes are generated using parity check matrices as shown in Tables 2 and 3.

Multiplexer S is then controlled by signal 88 to output signals 74 and 72 as output signals 76 and 77, respectively, i.e., to output the error correction code and write information stored in even addresses of storage circuit 54. After that, the signal 89 is transferred to the signal 7 at address 2m of the memory circuit 54.
6 and 77 are issued, and after the writing has taken place at that address, the signal 88 directs the outputs 76 and 77 of the multiplexer 53 to output 75 and 73, respectively, i.e., to store them at odd addresses in the storage circuit 54. The signal 89 is issued to output the error correction code and write information, and the signal 89 is issued to write the signals 76 and 77 to address 2n+1 of the memory circuit 54, thereby writing to that address. In this way, writing can be performed to any pair of even and odd addresses. On the other hand, at the time of reading, first, the designated address and read command are inputted to the one-legged circuit 61 by the input signal 71, and below, a case where the designated address is address 2n (even address) will be explained.

The output signal 89 of the Frjl leg circuit 61 is issued to read the 2n address of the memory circuit 54, and the error correction code 78 and read information 79 at the 2n address are output and set in the register 55 by the signal 90, and then The output 80 is input to the error checking circuit 57, and the signal 91 is issued to perform the parity check of 80, eg, the parity check of Table 1, C2 of Table 2, C of Table 3, and the signal 91 It is checked whether there is a 1-bit error in the error position, and if there is no error, the signal 84 notifies the output circuit 61 that there is no error, and the signal 93 is sent to the output 83 of the error position decoding circuit 59. At the same time, the output of the error correction circuit 60 generates a signal 94 so that the information 80 stored at the even address is outputted as read information 85, and reading is performed. . However, when the error checking circuit 57 discovers that there is a 1-bit error in the stored information 80, the signal 84 notifies the error circuit 61 that there is an error, and as a result, the signal 89 is turned on again. 2n+ of the memory circuit 54
A signal is issued to read address 1, an error correction code 78 and read information 79 are output, and a signal 91 causes register 5 to be read.
6, outputs 80 and 81 are applied to syndrome generation circuit 58 to generate syndrome code 82, and signal 93 is applied to error position decoding circuit 59.
Since the decoding signal 83 is outputted as an output, the error position is decoded and the signal 83 is given to the error correction circuit 60 along with the stored information 80 and 81.
One bit of the stored information at the even address is corrected by the signal 94, and the read information 85 is output as the output of the circuit 60, thereby performing error correction. When reading is performed to address 2n+1 (odd address), it is the same as when reading from even address, and if there is no error, the error check circuit 5
7, the information is read out as is. If a 1-bit error is found, the 1-bit error can be corrected by reading out the stored information at the paired even address 2n.

In one embodiment of FIG. 2, during writing,
We explained that addresses 2n and 2n+1 should be written in one operation, but when rewriting, it is necessary to write to addresses 2n+1 once.
Alternatively, it is obvious that after reading address 2n+1, this information can be used as write information, and the device can also be expanded to perform a writing operation by externally supplying information to be written to address 2n+1 or 2n.

Further, in the embodiment shown in FIG. 2, there are two addresses that share an error correction code, but it is clear that this can be easily extended to three or more addresses.

As explained above, in the present invention, when the number of information codes stored at the same address is k1 and the number of check codes is m, and if a 1-bit error can be corrected for j addresses, then , if a 1-bit error can be corrected for two addresses as in the case of the conventional case, then if m≧3 for the same number of code checks m, then the information stored at the same address The allowable range of the number of codes increases.

This means that the ratio of the number of error correction codes to the number of information codes is reduced, and a part of the error correction code added to the information bits of each address is used to determine whether there is an error in the read stored information. , if there is no error, the address can be read as is, and if there is an error, all of these addresses can be read and corrected. When using the present invention, it is extremely rare for there to be errors in read information, so an increase in the time required to read multiple addresses is not a problem.On the other hand, when writing, data is written to multiple addresses. However, in normal high-speed storage devices, the ratio of writes compared to reads is extremely low, so this does not pose a major problem, and it is very effective in read-only storage devices.

In addition, one error correction code used in the storage device is given to the information code of multiple addresses, and the error correction code of one address is used to detect whether there is an error in the information stored at the address. By configuring a storage device that can do this, the number of error correction codes relative to the number of information codes can be reduced, thereby making it possible to manufacture a storage device using error correction codes at low cost.

By the way, according to the present invention, the read operation is fast because there are almost no errors, but the write operation is slow because the error correction codes are distributed and it has to be performed for a plurality of addresses. However, in a typical computer, the ratio of reads is much higher than that of writes, and it is very effective for read-only storage devices.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining the principle of the present invention, and FIG. 2 is a diagram for explaining an embodiment of the present invention. 50, 51...Write register, 52...
・Error correction code generation circuit, 53...Multiplexer, 54...Main storage section, 55, 56...
. . . Read register, 57 . . . 1-bit error check circuit, 58 . . . Syndrome generation circuit.

Claims (1)

[Claims] 1. The data, the first check bit, and the second check bit are set as a set of information, and the first check bit of each set is created from a plurality of data among the plurality of sets of information forming a group, Specify a storage means for storing one or more groups in units of one set, in which the second check bits of each set are created by all the data belonging to each set and the first check bits, and the address of this storage means. After reading the set of information using an addressing means and an addressing signal output from the addressing means, a validity check is performed on all bits of the set of information using the second check bit. a 1-bit error detection means for detecting whether or not there is a 1-bit error; and error correction means for correcting a one-bit error using the first and second check bits.