JPH0973709A - Disk reproducing device, data reproducing method and signal processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a disk reproducing device and a signal processing circuit suppressing current consumption and heat generation due to it to an irreducible minimum even in the system requiring acceleration in operation such as a CR- ROM. SOLUTION: When an error symbol is not detected in an error correction circuit, a processing command and a clock are made so as not to be supplied from a program decoder 77 to relative circuits such as an ALU 75 and a decision circuit 74, so as not to execute calculation processing for obtaining the number of pieces of the error symbols, positions and error correcting patterns, etc., after that. Further, a gate circuit 11 supplying no processing command and no clock from the program decoder 77 to the relative circuits such as the ALU 75 and the decision circuit 74, so as not to execute excepting the processing required for correction processing of the number of pieces according to the number of pieces of the error symbols being the detection result of the error data is provided in the error correction circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disc reproducing apparatus such as a CD player and, more particularly, to error correction processing thereof.

[0002]

2. Description of the Related Art At present, in the field of audio equipment, an audio signal is converted to a P signal in order to perform high-density and high-fidelity recording and reproduction.
2. Description of the Related Art A digital recording / reproducing system that converts a signal into a digitized signal by a CM (Pulse Code Modulation) technique, records the signal on a recording medium such as a disk or a magnetic tape, and reproduces the signal is known. In particular, a CD in which a bit string corresponding to digitized data is formed on a disk having a diameter of 12 cm and which is optically read is used. In such a disk reproducing apparatus, an optical pickup element including a semiconductor laser and a photoelectric conversion element is moved linearly from the inner peripheral side to the outer peripheral side of the disk, and a CD is driven at a constant linear velocity (CLV: Constant Linear). Veloc
)), the data recorded on the CD is read. This CD stores digital data (main information data) obtained by converting an analog audio signal into PCM data in 16 bits. In digital data, 24 symbols each having 8 bits as one symbol are defined as one frame, and data is stored in a form in which this frame is repeated. In this disc, a cross interleaved Reed-Solomon (CIRC) code is used as an error correction code. The 24-symbol digital data is supplied to the C2-series parity generation circuit through the scramble unit, and the 4-symbol C2-series error correction parity data Q is supplied.
Is generated.

The digital data and the parity data Q are supplied to a C1 series parity generation circuit through an interleave circuit to generate C1 series error correction parity data P of 4 symbols. The 32-symbol data consisting of the 24-symbol digital data and the 4-symbol parity data P and Q is added with 8-bit (1 symbol) subcode data after passing through a 1-frame delay circuit. The subcode data and the 32 symbol data are E
FM (Eight to Fourteen Modulation) modulation is applied. A 3-bit margin bit is added between the modulated 14-bit symbols, and a 24-bit frame period signal is added at the beginning. Thus, 588-bit data is recorded on the disc as one frame. In this case, the bit clock is 4.3218M
Since it is Hz, 136 μsec per frame
It is recorded on the disc at (7.35 KHz). In the subcode data, one subcode frame is composed of 98 frames, and one subcode frame has 75 Hz (1
It is recorded on the disc in 3.3 msec.

The disc reproducing device EFM demodulates the digitized data read from the disc after separating the synchronizing signal from the data, and includes parity data P and Q 32.
The word component and the subcode data component of the symbol are separated. Then, in the signal processing circuit, the EFM demodulated data is written into the memory by the reproduction system frame clock by the PLL circuit and read from the memory by the system reference clock to absorb the time axis fluctuation due to the disk motor. And 32 per frame
C1 error correction processing is performed on the data component of the symbol based on the P parity symbol. Furthermore, 2
After deinterleaving the 4-symbol data and the 4-symbol Q-parity symbol, the CIRC code is decoded by performing the C2 sequence error correction process based on the Q-parity symbol. Then, based on the result of the error correction processing, the uncorrectable data is subjected to processing such as average value correction and output as audio data.

[0005] A CD is well known as a disk reproducing apparatus, and a CD-ROM is one of the representative examples. The CD-ROM is a device for reproducing audio signals mixed in a disc and ROM data such as image information and character codes. When an audio signal is reproduced, it is reproduced at a normal reproduction speed in order to output it as a sound, and this is set to 1 × speed. On the contrary, in order to read the data as quickly as possible, the ROM data is reproduced at a high speed, for example, 4 × speed. FIG. 19 shows the error correction processing of the error correction circuit in the conventional disc reproducing apparatus.
The description will be made with reference to FIGS. FIG. 19 is a block diagram of a conventional error correction circuit, FIG. 20 is a flowchart diagram showing an error correction algorithm based on the error correction circuit, and FIG. 21 is a block diagram of a program decoder used in the correction circuit of FIG. 22 and 23 are timing charts showing the processing algorithm of the error correction of FIG.

First, the error correction circuit and its operation will be described with reference to FIGS. The numbers attached to the respective operations represent steps (1) to (9) shown in FIG. The reproduced EFM signal (EFM) demodulated by the EFM demodulation circuit is written in the memory (RAM) 62 as digital data (symbol). The written data (symbol) is read by the syndrome calculation circuit 72 to determine the presence or absence of error data (1),
The syndrome is calculated (2). This result is stored in the syndrome register 73 and the determination circuit 74
The presence or absence of error data is determined at (3), and if there is an error, the error signal 78 is set. Subsequently, in order to obtain the number and position of error data, the syndrome register 73
The result of is input to the arithmetic logic unit (ALU) 75, the calculation based on the error equation is executed (4), the result is stored in the working register 76, and the number and position of the error data are determined by the determination circuit 74. It is judged (5). Further, the correction pattern of the error data is calculated by the ALU 75 from the result of the syndrome register 73, the result of the error equation in the working register 76, and the position of the error data (6), and the error data is corrected (7).

These series of operations are controlled by the processing instruction 79 of the program decoder 77. If the error signal 78 is set even in the corrected data (8), it is written in the memory (RAM) 62. (9) If the error signal 78 is not set, the memory (RAM) 62 is not written. FIG. 21 is a block diagram showing details of the program decoder 77. The program decoder 77 is
A ROM memory is provided, and a processing clock is input to an address and an error signal is input. Then, the ALU relating to the C1 correction processing and the C2 correction processing input to the ALU
Processing instructions C1-A through C1-D and C2-A through C2-
Determination circuit processing instructions C1-E to C related to C1 correction processing and C2 correction processing in which D is output and input to the determination circuit
1-G and C2-E to C2-G are output. Also,
The processing clock is output to each circuit of the correction circuit.

Processing instruction 7 of this program decoder 77
No. 9 has the algorithm shown in the timing charts of FIGS. 22 and 23, and this operation will be described below. 22 shows the case where there is an error symbol in both the C1 correction process and the C2 correction process, and FIG. 23 shows the C1 correction process and the C2 correction process.
This is the case in which there is no error symbol in both C2 correction processing. As is well known, EFM demodulated digital data is stored in a memory (RA) as data of 32 symbols in one frame.
In the correction circuit, one frame is set as one cycle of correction processing, and C1 correction and C2 correction are performed in one cycle. Here, in order to avoid complication of description, the concept of pointers and the like is omitted, and error correction calculation formulas and the like are well known. The 32-symbol data written in the memory (RAM) 62 is first read into the syndrome calculation circuit 72 as C1 correction processing, the syndrome calculation processing (hereinafter referred to as processing 1) is performed, and then the determination circuit 7 is determined from the result.
In step 4, a determination circuit processing instruction C1- (E) performs determination processing for the presence or absence of an error symbol (hereinafter referred to as processing 2). Next, the ALU 75 executes a calculation process for determining how many error symbols have occurred and the number thereof by the ALU processing instruction C1-A.

Then, based on this result, the decision circuit 74
In the decision circuit processing instruction C1-F, the selection process of the calculation method for obtaining in which symbol the error has occurred (that is, the position of the error symbol) is performed. Subsequently, the ALU processing instruction C1-B is output according to the calculation formula selected here, the calculation processing for obtaining the position of the error symbol is performed by the ALU 75, and similarly, the determination circuit processing instruction C1-G is performed by the determination circuit 74. A final determination process of the number of error symbols and their positions is performed. When the number and position of error symbols are known, the error correction pattern calculation process (hereinafter referred to as process 7) for correcting the error symbols is AL
It is executed by the ALU 75 by the U processing instructions C1-C.
If the error symbol is "present" in the result of the processing 2, the processing 7 is executed by the ALU processing instruction C1-D.
The error correction pattern resulting from the above is added to the error symbol, and the symbol correction and the writing process to the memory (RAM) 62 (hereinafter referred to as process 8) are performed. If the result of the process 2 is "none", the ALU process instruction C1-D is not output and the process 8 is not executed as shown in FIG.

This is the entire operation of C1 correction, but the following C
28 in 2 correction processing except C1 error detection code 4 symbols
The same processing is executed for the symbol and the error correction 1
The cycle ends. The C2 correction process is performed from the process (corresponding to the process 1 of the C2 correction process) to the process (16) as shown in the figure.
(Corresponding to the process 8 of the C1 correction process) is defined as one cycle.
This (16) is indicated by circled numbers in the drawings (hereinafter, circled numbers 10 to 21 in the drawings are indicated by (10) to (21) in the present specification). The operation of the error correction circuit in the prior art has been described above, but as can be seen from the above description, in order to simplify the circuit configuration in this example, for example, the result of the determination processing 2 is the error symbol “none”, that is, the configuration circuit. In other words, even in the "state where the flag with an error symbol is not set", the operations of the processes 3 to 7 are performed. Until now, this circuit has not been a problem, but in systems such as CD-ROM, which has recently emerged as a product for applying CD players, such as a CD-ROM, which requires a high operating speed, the extra processing requires immediate consumption of current. It leads to an increase and fever.

[0011]

As described above, in the conventional system, in order to simplify the circuit configuration, for example,
Even if it is determined that there is no error in step (3), the operation is up to step (7), and the final step (9) is based on the error determination result of step (8).
It was decided whether to execute or not. As described above, in the conventional disc reproducing apparatus such as a CD player, in order to simplify the circuit configuration of the error correction circuit, a process of executing a calculation process for obtaining an error symbol even when no error symbol is detected. Instructions and clocks are output from the program decoder to related circuits such as ALUs, which causes a problem of increasing current consumption and heat generation in a system such as a CD-ROM that requires a high operating speed. The present invention has been made in view of the above circumstances, and is a disk reproducing apparatus in which the current consumption and the heat generation accompanying it are suppressed to the minimum necessary even in a system such as a CD-ROM that requires a high operating speed. Provided are a signal processing circuit and a disk reproducing device.

[0012]

According to the present invention, when an error symbol is not detected in an error correction circuit, a calculation process for obtaining the number / position of error symbols and an error correction pattern after that is not executed. As described above, it is characterized in that a gate circuit that does not supply a processing instruction and a clock from the program decoder to the related circuits such as the ALU and the determination circuit is provided. Also, in the error correction circuit, depending on the number of error symbols that are the detection results of error data,
A feature is that a gate circuit that does not supply a processing command and a clock from the program decoder to the related circuits such as the ALU and the determination circuit is provided so as to perform only the processing necessary for the correction processing of the number. When no error symbol is detected in the error correction circuit, the related circuits such as the ALU and the determination circuit are set by the program decoder so as not to execute the subsequent calculation processing for obtaining the number and position of error symbols and the error correction pattern. By providing a gate circuit which does not supply a processing instruction and a clock to the above, related circuits such as ALU are stopped so as not to execute such calculation processing. For example, it is consumed in a system which operates at high speed such as a CD-ROM. The increase in current and heat generation can be suppressed to the necessary minimum. In addition, the error detection result corresponding to the number of error symbols is output from the correction circuit, and whether or not to perform the subsequent processing is controlled based on the signal. According to this, the related circuits such as the ALU are stopped except during the processing required depending on the number of erroneous symbols, and it is possible to suppress an increase in current consumption and heat generation of the system to a necessary minimum.

That is, according to the invention of claim 1, in the disc reproducing apparatus, information data is read from the disc,
The reproduction data is read from the memory means, and the correction data processing means includes means for generating reproduction data, memory means for storing the reproduction data, and correction processing means for performing error correction processing on the reproduction data. Syndrome calculation means to determine whether there is incorrect data,
A syndrome register for storing the calculation result by the syndrome calculating means, and a logic for writing the correction result to the memory means by calculating the number, position and correction pattern of the error data from the calculation result and correcting the error data. The presence / absence, the number, and the position of error data are determined from an arithmetic unit, a working register means for storing the correction result of the logical operation unit, the calculation result of the syndrome calculating means, and the correction result of the logical operation unit. And a gate means for controlling the output of the processing instruction and the clock output from the program decoder depending on the presence or absence of the error data. It is characterized by doing. According to a second aspect of the invention, in the disc reproducing apparatus,
Means for reading information data from the disc and generating reproduction data; memory means for storing the reproduction data;
Correction processing means for performing error correction processing of the reproduction data, wherein the correction processing means judges whether or not there is erroneous data in the reproduction data read from the memory means; and syndrome calculation means. A syndrome register for storing the calculation result by the means, and correcting the error data by calculating the number, position and correction pattern of the error data from the calculation result,
From the logical operation unit for writing the correction result in the memory means, the working register means for storing the correction result of the logical operation unit, the calculation result of the syndrome calculating means and the correction result of the logical operation unit. Determining means for determining the presence / absence, the number, and the position of error data, and a processing instruction and a clock required for these means are supplied, and the processing instruction and the clock output from the program decoder are output depending on the presence / absence of the error data. And a program decoder having gate means for on / off control.

According to a third aspect of the present invention, in the disc reproducing apparatus, means for reading information data from the disc to generate reproduced data, memory means for storing the reproduced data, and correction for performing error correction processing of the reproduced data. Processing means, the correction processing means, a syndrome calculating means for determining whether there is erroneous data in the reproduction data read from the memory means, and a syndrome register for storing the calculation result by the syndrome calculating means. , The number of the error data from the calculation result,
A logical operation unit for calculating a position and a correction pattern to correct the error data and writing the correction result in the memory means, a working register means for storing the correction result of the logical operation unit, and the syndrome. Judgment means for judging the presence, number, and position of error data from the calculation result of the calculation means and the correction result of the logical operation unit, and the processing instruction and clock necessary for these circuits are supplied to detect the error data. And a program decoder including a gate circuit for controlling on / off of output of a processing instruction and a clock output to a related circuit such as the logical operation unit according to the number of error symbols. According to a fourth aspect of the invention, in the disc reproducing apparatus, means for reading information data from the disc and generating reproduced data, memory means for storing the reproduced data, and correction processing means for performing error correction processing of the reproduced data. The correction processing means comprises a syndrome calculation means for judging whether or not there is erroneous data in the reproduction data read from the memory means, a syndrome register for storing a calculation result by the syndrome calculation means, and the calculation A number, a position, and a correction pattern of the error data are calculated from the result, the error data is corrected, and a logical operation unit for writing the correction result in the memory means and the correction result of the logical operation unit are stored. And a working register means for storing the result of the calculation of the syndrome calculating means. In addition, a judgment means for judging the presence, number, and position of error data from the correction result of the logical operation unit, a program decoder for supplying processing instructions and clocks necessary for these circuits, and an error as a result of detection of error data And a gate circuit for controlling on / off of output of a processing instruction and a clock output to a related circuit such as the logical operation unit according to the number of symbols.

[0015] The invention of claim 5 is the invention of claims 1 to 4.
In the reproduction data reproducing method according to any one of the disk reproducing devices, when the result of the syndrome calculating unit determines that there is no error data by the determination circuit, the correction process thereafter is stopped. To do. According to a sixth aspect of the present invention, in the signal processing circuit, a clock generation circuit that generates a reproduction clock synchronized with a data signal obtained by binarizing the information data read from the disk, and the reproduction signal by demodulating the data signal. And a correction processing circuit for performing error correction processing on the reproduction data, and the correction processing circuit determines whether or not there is erroneous data in the reproduction data read from the memory means. A syndrome calculation circuit, a syndrome register that stores a calculation result by the syndrome calculation circuit, a number of the error data, a position, and a correction pattern are calculated from the calculation result to correct the error data, and the correction result is described above. The logical operation unit written in the memory means and the correction result of the logical operation unit A working register, a determination circuit for determining the presence / absence, the number, and the position of error data from the calculation result of the syndrome calculation circuit and the correction result of the logical operation unit, and a processing instruction and a clock necessary for these circuits. And a gate circuit for controlling on / off of the output of the processing instruction and the clock output from the program decoder depending on the presence / absence of the error data.

According to a seventh aspect of the present invention, in the signal processing circuit, a clock generating circuit for generating a reproduction clock synchronized with a data signal obtained by binarizing the information data read from the disk, and demodulating the data signal. A data signal demodulation circuit for generating reproduction data, and a correction processing circuit for performing error correction processing on the reproduction data, wherein the correction processing circuit includes erroneous data in the reproduction data read from the memory means. A syndrome calculation circuit for judging whether or not it is, a syndrome register for storing the calculation result by this syndrome calculation circuit, a number of the error data, a position, and a correction pattern are calculated from the calculation result to correct the error data and the correction result A logical operation unit for writing the data into the memory means, and the correction of the logical operation unit. A working register for storing the result, a judgment circuit for judging the presence / absence, the number, and the position of error data from the calculation result of the syndrome calculation circuit and the correction result of the logical operation unit, and a processing instruction necessary for these circuits. And a program decoder having a gate circuit that supplies a clock and controls ON / OFF of the output of the processing instruction and the clock output from the program decoder depending on the presence or absence of the error data. To do.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. First, the overall system of the disc reproducing apparatus will be described with reference to FIGS. 1 and 2. FIG. 1 is an overall system diagram of the disc reproducing apparatus, FIG.
FIG. 3 is a detailed system diagram of the signal processing circuit of FIG. 1. A disc 1 such as a CD on which information is recorded is driven by a disc motor 2 and rotates at a constant linear velocity. Data recorded by the optical pickup element (PU) 3 is read from the rotating disk 1, and the read data is supplied to an EFM signal generation circuit (hereinafter referred to as an RF circuit) 4. The RF circuit 4 extracts the focus error signal and the tracking error signal from the output of the optical pickup element, supplies them to the servo control circuit 10 and binarizes the reproduction signal, and supplies them to the PLL circuit 5 as EFM signals. The PLL circuit 5 is an EF for reading the EFM signal.
A PLL clock (reproduction clock) synchronized with the M signal and a frame clock of the signal processing system are generated and supplied to the signal processing circuit 6 together with the EFM signal.

The servo control circuit 10 is a focus servo circuit that controls the focus of the optical system of the optical pickup element 3 so that the focus error signal becomes zero, and the servo control circuit 10 of the optical pickup element 3 so that the tracking error signal becomes zero. A tracking servo circuit that controls tracking of the optical system, a spindle servo circuit that controls a disk motor 2 such as a spindle motor that drives the disk 1 to rotate at a predetermined rotation speed, and a tracking servo actuator are located in the center of the movable range. Or a sled servo control circuit for moving the optical pickup element to a target track position of the disk 1 designated by the system controller 11. The signal processing circuit 6 performs read clock generation of the EFM signal, EFM demodulation, subcode demodulation, error correction processing, and the like, and outputs the output signal to a DAC (digital / digital).
Supply to the analog converter) 8. The output of the DAC 8 is supplied to the LPF (low-pass filter) 9. The output of this LPF 9 becomes the reproduced audio output signal. The system controller 11 supplies a speed switching signal and the like to the clock circuit. In addition, control signals for controlling the entire system, such as control of play, stop, search between tracks, ON / OFF control of muting, etc., are supplied to the signal processing circuit 6 and the servo control circuit 10.

Next, the signal processing circuit 6 will be described with reference to FIG. The PLL circuit 5 generates a PLL clock synchronized with the EFM signal for reading the EFM signal and a frame clock of the signal processing system, and supplies the frame clock to the EFM demodulation circuit 61. Further, the EFM signal is separated from the synchronizing signal by the EFM demodulation circuit 61 and then EFM demodulated, and 1 frame of subcode data, 32 symbols of data including parity data, a total of 33 symbols of data in a memory (RAM) ( Buffer memory) 62. The memory (RAM) 62 is used for interleaving in jitter absorption and error correction processing. Jitter on the time axis is absorbed by writing and reading the EFM demodulated signal in the buffer memory (RAM) 62. The output of the memory (RAM) 62 is supplied via a data bus to an error correction circuit 7 which performs C1 and C2 error correction. The error-corrected data is
It is written in the memory (RAM) 62 again. Subsequently, the error-corrected data is read from the memory (RAM) 62 and supplied to the output circuit 63. The output circuit 63 outputs the reproduction data (DATA), and if there is uncorrectable data thereafter, the average value complementation and the mute processing are performed.

Next, the structure and operation of the error correction circuit will be described with reference to FIGS. 3 is a detailed block diagram of the error correction circuit, FIG. 4 is a flow chart diagram showing an error correction algorithm based on the error correction circuit,
5 is a block diagram of a program decoder used in the correction circuit of FIG. 3, and FIGS. 6 and 7 are timing charts showing the processing algorithm of the error correction of FIG. The numbers attached to the respective operations represent steps (1) to (8) shown in FIG. The reproduced EFM signal demodulated by the EFM demodulation circuit 61 is written in the memory (RAM) 62 as digital reproduced data. The written data is read by the syndrome calculation circuit 72 to determine the presence or absence of an error symbol (1), and then the syndrome is calculated (2). The result is stored in the syndrome register 73, and the determination circuit 74 determines the presence or absence of an error symbol (3). If there is an error, the error signal 78 becomes "H", and if there is no error, the error signal 78 becomes "L" and is output from the program decoder 77 to the ALU 75, the determination circuit 74, the working register 76, and the syndrome register 73. It is connected to a gate circuit 70 for controlling ON / OFF of a processing instruction 79 and a processing clock 71 to be processed.

As shown in the system configuration of FIG. 3, when the error signal 78 is "H", the program decoder 77 to the ALU 75, the judging circuit 74 and the working register 7 are connected.
6. The processing instruction 79 and the processing clock 71 are output to the syndrome register 73.
As for the content of 9, first, the result of the syndrome register 73 is input to the ALU 75 in order to obtain the number and position of error symbols, and calculation based on the error equation is executed (4).
Further, the calculation result is stored in the working register 76, and the number and position of error symbols are determined by the determination circuit 7.
Make it judged by 4 (5). Further, the result of the syndrome register 73, the result of the error equation in the working register 76, and the position of the error symbol are displayed in the ALU7.
5, the correction pattern of the error symbol is calculated (6) and stored in the working register 76. continue,
This error symbol correction pattern is read to the ALU 75, added to the error symbol to correct error data (7), and the correction result is written to the memory (RAM) 62 (8).

When the error signal 78 is "L", the processing instruction 79 and the processing clock 71 to be output from the program decoder 77 to the ALU 75, the judging circuit 74, the working register 76, and the syndrome register 73.
Is fixed to "L" by the gate circuit 70, and A
The LU 75, the determination circuit 74, the working register 76, and the syndrome register 73 are completely stopped. Therefore, as described above, the number / position of error symbols / calculation of error symbol correction patterns (4), (5), and (6), error symbol correction (7), and write operation to the memory (RAM) 62 (8) ) Is not done. That is, in step (3) shown in FIG. 4, if there is no error, the processes of steps (4) to (8) are omitted. FIG.
FIG. 7 is a block diagram showing details of a program decoder 77 and a gate circuit 70 associated therewith. The program decoder 77 has a ROM memory, a processing clock is input to an address, and an error signal is input. Then, ALU processing instructions C1-A to C1-D and C2 relating to the C1 correction processing and the C2 correction processing input to the ALU.
-A to C2-D are output via the gate circuit 70,
Judgment circuit processing instructions C1-E to C1-G and C2 relating to C1 correction processing and C2 correction processing input to the judgment circuit
-E to C2-G are output via the gate circuit 70. Further, the processing clock is output to each circuit in the error correction circuit through the gate circuit.

Next, how the related circuits such as the ALU 75 operate in accordance with the contents of the processing instruction 79 output from the program decoder 77 will be described from the viewpoint of the algorithm. As described above, in the error correction circuit 7, one frame is set as one cycle of the correction process, and C1 correction and C2 correction are performed in one cycle. As the operation algorithm, as shown in FIG. 6, first, 32 symbol data is read from the RAM as a C1 correction process into the syndrome calculation circuit, and the syndrome calculation process (hereinafter referred to as process 1) is performed. C1- (E) performs a process of determining the presence / absence of an error symbol (hereinafter referred to as process 2). As a result of this process 2, if it is determined that there is an error symbol “present”, the calculation process (hereinafter referred to as process 3) for obtaining the number of error symbols and the number of error symbols generated next is the ALU processing instruction C.
1-A is executed by the ALU 75. Based on the result of this process 3, the process of selecting a calculation method (hereinafter referred to as process 4) for determining in which symbol an error has occurred (position of error symbol) in the determination circuit 74 is the determination circuit processing instruction C1-F. Done by Subsequently, the ALU processing instruction C1-B is output according to the calculation formula selected in the process 4, and the ALU 75 performs the calculation process for obtaining the position of the error symbol (hereinafter referred to as the process 5).

Similarly, the decision circuit 74 issues a decision circuit processing instruction C.
A final determination process (hereinafter referred to as process 6) for the number of error symbols and their positions is performed by 1-G. Next, when the number and position of the error symbols are known, a calculation process of an error correction pattern for correcting the error symbols (hereinafter,
Processing 7) is AL by ALU processing instruction C1-C
It is executed in U75. Subsequently, the error correction pattern resulting from the process 7 is added to the error symbol by the ALU process instruction C1-D to correct the symbol and store the memory (RAM).
A write process (hereinafter, referred to as process 8) is performed to complete the C1 correction operation. If the result of the process 2 is “absent” retroactively, as shown in FIG. 7, from the determination result of this error symbol “absent”, the subsequent processes 3 to 8 are not executed and the C1 correction operation is terminated. Become. This movement is
This is because the gate circuit 70 does not supply the processing instruction and the clock of the program decoder 77 to the related circuits such as the ALU 75 and the determination circuit 74, so that the circuits are stopped. Specifically, the gate circuit 70 causes the ALU
Processing instructions C1-A to C1-D and determination circuit processing instruction C1
-F to C1-G and the clocks to the syndrome circuit and the syndrome register indicated by the processing clock A, the clocks to the determination circuit and the ALU and the working register indicated by the processing clock B are prohibited from being output.

The above is the operation of the C1 correction processing. In the subsequent C2 correction processing, the same processing is executed for 28 symbols excluding the 4 symbols of the C1 error detection code, and one cycle of error correction is completed. As shown in the figure, the C2 correction processing has one cycle from processing (corresponding to processing 1 of C2 correction processing) to processing (16) (corresponding to processing 8 of C1 correction processing). FIG. 8 is a block diagram of a program decoder having a structure different from that shown in the above embodiments. The program decoder 77 shown in FIG. 5 is provided with the gate circuit 70 as a separate component, but the program decoder 80 shown in FIG. 5 has a built-in gate circuit composed of a plurality of AND circuits. Its function is the same as that of FIG. As shown in FIG. 1, the system constituting the disc reproducing apparatus includes a semiconductor substrate (chip) having a PLL circuit and a signal processing circuit, and constructs a system with other components. This system includes, for example, the chip and
A chip having an RF circuit and a servo control circuit, and a DAC
And a LPF, and a chip including a system controller such as a microcomputer.

In the conventional error correction algorithm, up to 2 error symbols can be corrected by C1 error correction and up to 4 error symbols can be corrected by C2 error correction. An algorithm limiting the number of error symbols will be described with reference to FIGS. 9 to 11. As described above, the EFM-demodulated digital data is written in the memory (RAM) as 32 symbol data in one frame. In the correction circuit, this one frame is set as one cycle of correction processing, and C1 error correction and C2 error correction are performed in one cycle. FIG. 9 is a flowchart of a C1 error correction algorithm (motion in one frame), FIG.
0 and FIG. 11 are flowcharts of the C2 error correction algorithm (motion in one frame). In the C1 error correction (FIG. 9), first, 32 symbol data is read from the RAM, and a syndrome calculation for determining the presence or absence of error data is performed. If there is no error symbol here, it is determined that there is no error symbol, but if an error symbol is detected, an error such as whether there is one error symbol, two error symbols, or three or more error symbols has occurred. The number of symbols is calculated. When the number of error symbols is 3 or more, it is determined that the C1 correction is “uncorrectable”, and a signal called a pointer is set in this frame. If there is one error symbol, position calculation is performed to find where the error has occurred, and if "one root (solution)" is found as a result, error correction for the symbol at that position is performed. The correction pattern is calculated. After this pattern is added to the error symbol, it is written again in the RAM, and the correction process ends. If "one root (solution)" is not found when calculating the position of the error symbol, it is determined to be "uncorrectable" and the pointer is set. Similarly, in the case of two error symbols, the position calculation of two error symbols, the correction pattern calculation, the correction,
A writing process is being performed.

In C2 error correction (FIGS. 10 and 11),
28 symbols of data are read from the RAM because the used 4 symbols of parity are unnecessary for C1 error correction. Similar to the C1 error correction, the syndrome calculation for determining the presence or absence of error data is performed, and if an error symbol is detected, is it possible to generate one error symbol?
The number of error symbols, such as whether there are two or three or more, is calculated. If there are three or more error symbols, the number of pointers (C1 pointers) set by the C1 error correction algorithm is checked. If there are four pointers, the position of the C1 pointer is regarded as the position of four error symbols, and the correction pattern of four error symbols is calculated and added to the error symbols. The added correction symbol is written in the RAM again, and the correction process ends. If there are 4 or more C1 pointers,
It judges that it cannot be corrected, complements only the symbol with the pointer, and ends. When there are three C1 pointers, the position of the pointer is regarded as the position of three error symbols,
For checking, "3 roots (solution)" is substituted into the calculation formula to perform verification. If the result of the check is "OK", a correction pattern of three error symbols is calculated, added to the error symbols for correction, and written again in the RAM. The result of verification is "N
If it is "G", this frame is judged as "uncorrectable", and all the symbols of this frame are complemented. When the number of C1 pointers is 2 or less, it is also judged as "uncorrectable" and this frame Now, if we go back and calculate the number of error symbols is 1, we calculate the position of the symbol, and as a result, "1 root (solution)"
When is obtained, it is checked whether it matches the position of the pointer set by the C1 correction algorithm.

Here, only when the position of the pointer, the position of the error symbol, and the position of the error symbol match, the correction pattern of one error symbol is calculated, added to the error symbol, and written again in the RAM. The correction process ends. If it does not match the pointer, it is judged as "uncorrectable" and the symbol at the position of this pointer is complemented. If "one root (solution)" is not obtained as a result of the error symbol position calculation, it is determined as "uncorrectable" and all the symbols of this frame are complemented. If there are two error symbols, calculate the position of the error symbol,
When "two roots (solution)" are obtained, it is checked whether the position of the C1 pointer and the position of the obtained error symbol match. As a result, if the positions match, it is further checked whether the number is 4 or less. This is because in the case of two error symbols, if the number of C1 pointers is five or more, there is a high possibility that the position of the error symbol and the pointer matching check process are erroneous. If the number of pointers is four or less, a correction pattern of two error symbols is calculated, added to the error symbols, and written in the RAM again. When the positions of the C1 pointers are 5 or more, or the positions of two error symbols do not match the C1 pointers, it is determined that “correction is not possible”, the symbol at the position of the pointer is complemented, and the process ends. If "two roots (solutions)" are not found in the position calculation of the error symbol, there is a possibility that three or more errors are made. Therefore, the above three or more error symbols are checked.

According to the above algorithm, it is possible to correct up to 2 error symbols in C1 error correction and up to 4 error symbols in C2 error correction. In order to implement this algorithm, conventionally, error correction as shown in FIG. 19 is performed. The circuit was ready. The related art and its problems will be described below with reference to FIGS. 19 and 12 to 14. FIG.
13 and FIG. 13 are overall timing charts of the conventional program decoder, and FIG. 14 is a block diagram showing the configuration of the conventional program decoder. In this program decoder, C1 error correction is performed for up to two error symbols, C2 error correction.
The error correction can correct up to four error symbols.

First, how the error correction algorithm is conventionally realized will be briefly described with reference to FIG. The reproduced EFM signal demodulated by the EFM demodulation circuit as described above is written in the RAM 62 as digital data. The written data is read to the syndrome calculation circuit 72, and the syndrome calculation is performed. This result is stored in the syndrome register 73, and the presence or absence of an error symbol is determined by the determination circuit 74. If there is an error symbol, the "error symbol present signal" 87 of the error detection signal is set. Then, the result of the syndrome register 73 is the logical operation unit (ALU).
It is input to 75 and a calculation for obtaining the number of error symbols is executed. As a result, the decision circuit 74 executes the selection of the calculation formula for obtaining the position of the error symbol corresponding to the number of error symbols. The calculation formula selected here is executed in the ALU 75, and as a result, the determination circuit 74 checks whether or not there is a “root (solution) to be obtained” and if so, what is the condition with the pointer. When the number and positions of error symbols are secured by this, the positions of error symbols are stored in the working register 76. At this time, if there are four error symbols, the "signal with four error symbols" 85 of the error detection signal is set. Further, from the result of the syndrome register 73 and the position of the error symbol in the working register 76, the correction pattern of the error data is ALU7.
5 and the error data is corrected based on this. These series of operations are controlled by the processing instruction 79 and the processing clock 71 of the program decoder 77. If the "error symbol present signal" 87 is set in the corrected data, it is written in the RAM 62 and set. If not, it is not written.

Processing instruction 7 of this program decoder 77
9 is shown in the entire timing chart of FIGS. 12 and 13, and this movement will be described below. EFM
The demodulated digital data is written in the RAM as data of 32 symbols in one frame, but the correction circuit uses this one frame as one cycle of the correction process, and C1 error correction and C2 error are included in one cycle. Corrections have been made. First, the 32-symbol data written in the RAM is read into the syndrome calculation circuit as C1 error correction processing, and after the syndrome calculation processing (hereinafter referred to as processing 1) is performed, the determination circuit detects the error symbol Presence / absence determination processing (hereinafter referred to as processing 2) is performed. At this time, if an error symbol is detected, the "error symbol present signal" 87 is set.
Next, a calculation process (hereinafter, referred to as a process 3) for obtaining the number of error symbols generated and the number thereof is executed in the ALU, and as a result, the calculation process corresponding to the number of error symbols is performed.
A determination process (hereinafter, referred to as process 4) of selecting a calculation formula for obtaining the position of the error symbol is performed.
Subsequently, a calculation process for obtaining the positions of up to two error symbols in the ALU according to the calculation formula selected here (hereinafter,
Processing 5) is performed, and the determination circuit similarly performs the processing 5
A "root" determination process (hereinafter, referred to as process 6) is performed. When the number and position of error symbols are known, calculation processing of an error correction pattern for correcting symbols according to the number of error symbols (hereinafter referred to as processing 7)
Is executed by the ALU. Here, the "error symbol present" signal 87 is set in the result of the processing 2, and
If there are up to two error symbols, the error correction pattern resulting from the process 7 is added to the error symbol, and symbol correction and RAM writing process (hereinafter referred to as process 8) are performed. If there is an "erroneous symbol" signal 87
If is not set, the process 8 is not executed. The above is the entire operation of the C1 error correction, but the C1 error correction can correct up to two error symbols.
In C1 error correction, when there are two or more error symbols, a C2 correction signal called a pointer is set. In addition, when all the operations are completed, “There is an error symbol”
The signal 87 is cleared.

Subsequently, in the C2 error correction processing, 4 symbols are used for 28 symbols excluding 4 symbols of the C1 error detection code.
Correction processing is performed up to the number of pieces. 28 written in RAM
The symbol data is read into the syndrome calculation circuit, and after the syndrome calculation processing (hereinafter referred to as processing 9) is performed, the judgment circuit determines from the result thereof whether there is an error symbol (10) (hereinafter referred to as processing 10). ) Is done. At this time, if an error symbol is detected, the "error symbol present" signal 87 is set. Next, a calculation process (11) for obtaining the number of erroneous symbols and the number of erroneous symbols (indicated by circled numbers in the figure, the same applies hereinafter) (hereinafter referred to as process 11) is executed by the ALU. As a result, a judgment process for selecting a calculation formula for checking the condition with the pointer if three or more error symbols have occurred and for calculating the position of the corresponding error symbol for up to two error symbols ( 12) (hereinafter, process 1
2) is performed. Subsequently, a calculation process (13) for obtaining the positions of up to two error symbols (hereinafter referred to as process 13) is performed in the ALU according to the calculation formula selected here, and thereafter, the "root" of the process 13 is performed by the determination circuit. The determination process (14) (hereinafter, referred to as process 14) is performed. C2
In the error correction process, a determination process (15) (hereinafter, referred to as process 15) for checking the match with the pointer set by the C1 error correction and the number of pointers is subsequently performed. When there are four error symbols, there are four error symbols and the signal 85 is set. Once the number and position of error symbols are known, the error correction pattern calculation process for correcting up to two error symbols (16)
(Hereinafter, referred to as processing 16) is executed by the ALU, and when the number of error symbols is 3, the error symbol position verification processing (17) (hereinafter referred to as processing 17) is performed. In the subsequent judgment process (18) (hereinafter referred to as process 18), it is checked whether or not this verification result is OK.
If K, the correction pattern calculation process (19) for correcting three error symbols (hereinafter referred to as process 19) is AL.
This is performed in U, but if the number of error symbols is up to two at this time, the result of processing 19 is invalid and the result of processing 16 is valid.

When there are four error symbols, the processing 17 to processing 19 is not performed by the above-mentioned "there are four error symbols" signal 85, and the correction pattern calculation processing of four error symbols (20) (hereinafter, Processing 20) is performed.
Up to this point, the number and position of up to four error symbols and the correction pattern have been known. Returning to the result of processing 10, if there is an error symbol, processing 16 is performed according to the number of error symbols. , 19 and 20 are added to the error correction pattern, and the symbol is corrected and written in the RAM (21) (hereinafter,
Processing 21) is performed. If the result of the process 10 is "none", the process 8 is not executed. The above is C2
This is the entire operation of error correction, and when all the operations are completed, the "error symbol present" signal 87 and "there are four error symbols present"
The signal 85 is cleared. Each process of this program decoder is performed by C1-A to G and C2 shown in FIGS.
The signals are output at the timings of −A to L, and as an example for realizing this, a circuit as shown in FIG. 14 is prepared. The program decoder 77 shown here is composed of a ROM to which a clock is input as an address and a plurality of gates. The outputs C1-A to G, C2-A to L of the program decoder 77 and the processing clock. 71 is supplied to each circuit. As can be seen from FIG. 14, if the "error symbol present" signal 87 is not set, the ALU processing instructions C1-D and C2-G are not output and the corrected symbol is not written in the RAM. Also, if the "4 error symbols are present" signal is set, the ALU processing instruction C2-F is output, and if it is not set, C2-D, E, L are output.

As described above, in the conventional error correction circuit,
In order to simplify the circuit configuration, for example, the determination process 2
Even if the result of 1 is "no error symbol", that is, in the state where the "error symbol" signal is not set in the circuit configuration, the operations of the processes 3 to 7 are performed. Although such a correction circuit has not been a problem in the past, in a system such as a CD-ROM which has recently emerged as a CD player application product, which requires a high operation speed, extra processing consumes an immediate current consumption. Will lead to an increase in heat and fever. Further, in the conventional CD player device, in order to simplify the circuit configuration in the error correction circuit, the processing instruction and clock for executing the calculation processing for obtaining the error symbol even if the error symbol is not detected are the program decoder. To ALU
However, in a system such as a CD-ROM that requires a high operating speed, there is a problem of increasing current consumption and heat generation. In order to solve the above problems, in the embodiment of the present invention, depending on the number of error symbols that are the detection results of error data, the error correction circuit does not execute any processing other than the processing necessary for the correction processing of that number. The program decoder is provided with a gate circuit that does not supply a processing instruction and a clock to related circuits such as an ALU and a determination circuit.

An embodiment of the second invention will be described below with reference to FIGS. The whole system and the algorithms for C1 error correction and C2 error correction are as shown in FIGS. The reproduced EFM signal demodulated by the EFM demodulation circuit is stored in the RAM 62 as digital data.
Is written in. The written data is read to the syndrome calculation circuit 72 and the syndrome is calculated. The calculation result is stored in the syndrome register 73, and the determination circuit 74 determines whether or not there is an error symbol. If there are no error symbols, "No error symbol signal" of the error detection signal (81-86)
81 is set. Then, the syndrome register 73
The calculation result stored in is input to the ALU 75, and the calculation for obtaining the number of error symbols is executed.
As a result, the determination circuit 74 executes the selection of the calculation formula for obtaining the position of the error symbol corresponding to the number of error symbols. The calculation formula selected here is executed by the ALU 75, and as a result, the determination circuit 74 checks whether or not there is a "root (solution) to be obtained" and if so, what is the condition with the pointer. When the number and positions of error symbols are secured by this, the positions of error symbols are stored in the working register 76. At this time, the following error detection signals are set according to the number of error symbols. First, if there is one error symbol, the "signal with one error symbol" 82 is set, if there are two, the "signal with two error symbols" 83 is set, and if there are three, " Signal with three error symbols "8"
When 4 is set and there are four, the "signal with four error symbols" 85 is set, and when the error symbol cannot be corrected, the "error symbol uncorrectable signal" 86 is set. Further, from the result of the syndrome register 73 described above and the position of the error symbol in the working register 76, the correction pattern of the error data is determined by the ALU7.
5, the error data is corrected.

The series of operations described so far are based on the output of the processing instruction 79 and the processing clock 71 of the program decoder 77 controlled by the gate circuit 11.
Only the necessary minimum operation is performed depending on the states of the error detection signals 81 to 86. In the above-described configuration, according to the contents of the processing instruction 79 and the processing clock 71 of the program decoder 77 controlled by the gate circuit 11, how the related circuit such as the ALU 5 operates and its movement are shown in the overall timings of FIGS. 16 and 17. chart,
This will be described in detail using the configuration of the program decoder 77 having the gate circuit 11 shown in FIG. The EFM demodulated digital data is written in the RAM as 32 symbol data in one frame, but in the correction circuit,
This one frame is set as one cycle of correction processing, and C1 error correction and C2 error correction are performed in this one cycle.

First, the 32-symbol data written in the RAM 62 is read into the syndrome calculation circuit 72 as C1 error correction processing, and the syndrome calculation processing (hereinafter referred to as processing 1) is performed. At 74, processing for determining the presence or absence of an error symbol (hereinafter referred to as processing 2) is performed. At this time, if no error symbol is detected, the “no error symbol signal” 81
Is set and no further processing is performed. When an error symbol is detected, how many error symbols have occurred,
A calculation process (hereinafter, referred to as process 3) for obtaining the number is executed in the ALU 75, and as a result, the determination process (hereinafter referred to as process 4) results in 3 error symbols
If it is judged that the number is not more than, it means that the error cannot be corrected, and the "error symbol uncorrectable signal" 86 and the pointer are set,
No further processing is performed. If it is determined in the process 4 that there are up to two error symbols, a calculation formula for determining the position of the error symbol corresponding thereto is selected. Subsequently, a calculation process for obtaining the positions of up to two error symbols by the ALU 75 according to the selected calculation formula (hereinafter referred to as process 5) is performed, and similarly, the determination circuit 74 determines the "root" of process 5 (process 5). Hereinafter, the process 6) is performed. Here, when the "root" is found, the "one error symbol present" signal 82 and the "two error symbol present" signal 83 corresponding to the number of error symbols are set. If no "root" is found, it is considered uncorrectable, the error symbol uncorrectable signal 86 is set, and no further processing is performed. Now, when the "root" is found and the number and position of error symbols are known, the error correction pattern calculation process (hereinafter referred to as process 7) for correcting symbols according to the number of error symbols is performed by the ALU75.
Processing by the ALU 75 (hereinafter, referred to as processing 8).
Is added to the error symbol and the resulting R
The writing process to the AM 62 is performed. The above is all about the C1 error correction according to the embodiment of the present invention. When the C1 error correction operation is completed, the error detection result signals 81 and 8 are output.
2,83,86 are cleared.

Subsequently, in the C2 error correction process, up to four correction processes are performed on 28 symbols excluding the 4 symbols of the C1 error detection code. 2 written in RAM 62
The 8-symbol data is read into the syndrome calculation circuit 72, and after the syndrome calculation processing (hereinafter referred to as processing 9) is performed, the judgment circuit 74 judges from the result thereof whether there is an error symbol (10) (hereinafter, Processing 10) is performed. At this time, if no error symbol is detected, the "no error symbol signal" 81 is set, and the subsequent processing is not performed. When an error symbol is detected, the calculation process (11) (hereinafter referred to as process 11) for obtaining the number of error symbols and the number of error symbols is performed by the ALU.
At 75. As a result, if three or more error symbols have occurred, a calculation formula is selected to check the condition with the pointer, and if up to two error symbols, a calculation formula for determining the position of the corresponding error symbol is selected. Judgment process (12) (hereinafter, process 12)
Is done. If there are up to two error symbols, the calculation process (13) (hereinafter, process 13) for determining the position of the error symbol by the ALU 75 is performed by the selected calculation formula. After that, the determination circuit 74 performs the "root" determination process (14) of the process 13 (hereinafter referred to as the process 14). At this time, if "one root (solution)" is not found with one error symbol, it is regarded as uncorrectable, the error symbol uncorrectable signal 86 is set, and no further processing is performed.

In the case of 2 error symbols, if "2 roots (solution)" cannot be found, there is a possibility of 3 or 4 errors. Therefore, 3/4 check processing described later is performed. To do. When the "root" is found in the process 14, in the C2 error correction process, the determination process (15) for checking the match with the pointer set by the C1 error correction and the number of pointers thereafter (15) (hereinafter, process 15) However, if it does not match the position of the pointer or the number of pointers does not match at this time, it is regarded as uncorrectable, the error symbol uncorrectable signal 86 is set, and no further processing is performed. By the way, in the process 12, there are three or more error symbols,
Alternatively, if it is determined in process 14 that there is a possibility of 3 or 4 error symbols, in process 15, the number of pointers is checked. First, if the number of pointers is two or less, it does not match the number of "roots", so that it is regarded as uncorrectable, the "error symbol uncorrectable" signal 86 is set, and the subsequent processing is not performed. In the case of three, it is highly possible that the position of the pointer is the position of three error symbols.
Here, the signal “with three error symbols” 84 is set. When the number of pointers is four, the position of the pointer is regarded as the position of four error symbols, and the “85 error symbols exist” signal 85 is set. If none of the above apply, it is considered uncorrectable,
The "error symbol uncorrectable" signal 86 is set and no further processing is performed. In the embodiment of the present invention,
Subsequent processing is from the signal "with n error symbols n" signal 82-
Controlled by 85. If the number of error symbols is two or less, the correction pattern of the error symbols corresponding to the number is calculated by the process (16) (hereinafter referred to as the process 16), and the processes (17) to (20) are not executed. .

If there are three error symbols, the processing 16 and the processing 20 are not performed, and it is considered that the position of the pointer is likely to be the position of three error symbols, and the verification processing (1
7) (hereinafter referred to as processing 17) is performed. This verification result is checked in the determination process (18) (hereinafter referred to as process 18) to see if it is OK, and if OK, a correction pattern of three error symbols is calculated in process (19) (hereinafter referred to as process 19). It If the verification result is NG, the "3 error symbols exist" signal is cleared, it is determined that the symbols cannot be corrected, and the "error symbol uncorrectable" signal 86 is set. The process is stopped. When there are four error symbols, the position of the pointer is regarded as the position of the error symbol, and the correction pattern calculation process (20) (hereinafter referred to as process 20) is executed. At this time, the processes 16 to 19 are not performed.
If all the conditions are satisfied up to this point, the addition of the correction pattern to the error symbol corresponding to the number of error symbols and the writing process to the RAM (21) (hereinafter,
The process 21) is executed. The above is the entire operation of the C2 error correction according to the embodiment of the present invention, and when the operation is completed, the error symbol detection signals 81 to 86 are cleared.

Each processing of the program data as described above is performed by C1-A to G and C2-A shown in FIGS.
The signals are outputted at the timings of ~ L, but as an example for realizing this, a circuit as shown in FIG. 18 is prepared. The circuit shown here includes a ROM to which a clock is input as an address, a program decoder 77 having a plurality of gates, and a gate circuit 11 included in the program recorder 77 for controlling the output thereof. The outputs C1-A to G, C2-A to L of this circuit and the processing clocks corresponding thereto are supplied to the ALU 75 and the determination circuit 74 shown in FIG. 15, and the error correction processing as described above is performed. It is done. As can be seen from FIG. 18, the processing instruction and the processing clock are required by the ALU 75 and the determination circuit 74 to be the minimum required by the “no error symbol” signal 81, the “n error symbol n” signals 82 to 85 and the “error symbol uncorrectable” signal 86. It can be seen that the supply is limited.

As described above, the program decoder in FIG. 18 has the gate circuit 11 built therein. However, in the present invention, the program decoder and the gate circuit are separately provided without incorporating the gate circuit in the program decoder. A circuit may be used. When the error correcting circuit of the CD-ROM and the audio correcting circuit are made common to the prior art and the syndrome monitoring means determines that there is no error,
No correction processing is performed on the audio or CD-ROM data, and the audio data correction request and C
There is a disk reproducing apparatus that prioritizes the correction of audio data when it conflicts with the data correction request of the D-ROM (JP-A-6-12791). this is,
The purpose is to realize the downsizing of the device and the speeding up of the correction process, but there is no description of a specific circuit configuration of how the correction process is not performed.

In the disc reproducing apparatus of the present invention, the correction circuit is provided with a gate circuit for turning on and off the output of the processing command and the processing clock, and the correction processing is suppressed to the minimum necessary depending on the number of errors. In the known disc reproducing apparatus, a series of correction operations are performed in the same manner as in the conventional case, and after all the elements necessary for the correction are prepared, the correction processing is performed by the number judgment at the end. The configuration is different from that of the invention, and as a result, many useless operations are performed in the transmission path including the disk reproducing device in which one error frequently occurs.

[0044]

As described above, the disk reproducing apparatus of the present invention executes the calculation processing for obtaining the number and position of error data and the error correction pattern after that when the error data is not detected in the error correction circuit. Do not do A
Related circuits such as LU are stopped, and the error correction circuit outputs an error detection effect corresponding to the number of error symbols, and control is performed based on the signal whether or not to perform the subsequent processing. Therefore, the related circuits such as the ALU are stopped except during the processing required depending on the number of erroneous symbols. As a result, the current consumption increases in the system that performs high-speed operation (for example, quadruple speed) such as CD-ROM. It is possible to suppress heat generation to the minimum necessary.

[Brief description of drawings]

FIG. 1 is a block diagram of a disk reproducing apparatus according to the present invention.

FIG. 2 is a block diagram of a signal processing circuit used in FIG.

FIG. 3 is a block diagram of an error correction circuit used in the embodiment of the first invention.

FIG. 4 is a flowchart illustrating a correction algorithm of the present invention.

5 is a block diagram of a program decoder and a gate circuit used in FIG.

FIG. 6 is an operation algorithm timing chart of the program decoder according to the first embodiment of the invention.

FIG. 7 is an operation algorithm timing chart of the program decoder according to the first embodiment of the invention.

8 is a block diagram of a program decoder used in FIG.

FIG. 9 is a flowchart showing an algorithm for C1 error correction.

FIG. 10 is a flowchart showing an algorithm for C2 error correction.

FIG. 11 is a flowchart showing an algorithm for C2 error correction.

FIG. 12 is an overall timing chart of a conventional program decoder.

FIG. 13 is an overall timing chart of a conventional program decoder.

FIG. 14 is a block diagram of a conventional program decoder.

FIG. 15 is a block diagram of an error correction circuit used in the embodiment of the second invention.

FIG. 16 is an operation algorithm timing chart of the program decoder according to the second embodiment of the invention.

FIG. 17 is an operation algorithm timing chart of the program decoder according to the second embodiment of the invention.

FIG. 18 is a block diagram of a program decoder used in FIG. 15.

FIG. 19 is a block diagram of an error correction circuit used in a conventional disc reproducing device.

FIG. 20 is a flowchart showing a correction algorithm of a conventional disc reproducing apparatus.

FIG. 21 is a block diagram of a program decoder and a gate circuit of a conventional disc reproducing device.

FIG. 22 is a timing chart of the operation algorithm of the conventional program decoder.

FIG. 23 is a timing chart of the operation algorithm of the conventional program decoder.

[Explanation of symbols]

1 ... Disc, 2 ... Disc motor, 3 ...
..Pickups (PU), 4 ... RF circuits, 5
... PLL circuit, 6 ... Signal processing circuit, 7 ...
・ Error correction circuit, 8 ... DAC, 9 ... L
PF, 10 ... Servo control circuit, 11, 70 ...
.Gate circuit, 61 ... EFM demodulation circuit, 62.
..Memory (RAM), 63 ... Output circuit, 71
... Processing clock, 72 ... Syndrome calculation circuit, 73 ... Syndrome register, 74 ...
Judgment circuit, 75 ... Logical operation unit (AL
U), 76 ... Working register, 77, 80
... Program decoder, 78, 87 ... Signal with error symbol, 79 ... Processing instruction, 81 ... Signal without error symbol, 82 ... Signal with one error symbol, 83 ... Error symbol Signal with 2 signals, 84 ... Signal with 3 error symbols, 85 ... Signal with 4 error symbols, 86 ... Error symbol uncorrectable signal.

Claims (7)

[Claims] 1. A correction processing means comprising: means for reading information data from a disc to generate reproduction data; memory means for storing the reproduction data; and correction processing means for performing error correction processing on the reproduction data. Is a syndrome calculation means for judging whether or not there is erroneous data in the reproduction data read from the memory means, a syndrome register for storing the calculation result by the syndrome calculation means, and the number of the erroneous data from the calculation result. A logical operation unit that corrects the error data by calculating a position and a correction pattern, and writes the correction result in the memory means,
Working register means for storing the correction result of the logical operation unit, determination means for determining the presence / absence, number, and position of error data from the calculation result of the syndrome calculation means and the correction result of the logical operation unit. A program decoder for supplying necessary processing instructions and clocks to these means, and a gate means for on / off controlling the output of the processing instructions and the clock output from the program decoder depending on the presence or absence of the error data. A disc reproducing device characterized by. 2. A correction processing means comprising: a means for reading information data from a disc to generate reproduction data; a memory means for storing the reproduction data; and a correction processing means for performing error correction processing on the reproduction data. Is a syndrome calculation means for judging whether or not there is erroneous data in the reproduction data read from the memory means, a syndrome register for storing the calculation result by the syndrome calculation means, and the number of the erroneous data from the calculation result. A logical operation unit that corrects the error data by calculating a position and a correction pattern, and writes the correction result in the memory means,
Working register means for storing the correction result of the logical operation unit, determination means for determining the presence / absence, number, and position of error data from the calculation result of the syndrome calculation means and the correction result of the logical operation unit. A program decoder having a gate means for supplying necessary processing instructions and clocks to these means, and controlling ON / OFF of the output of the processing instructions and the clock output from the program decoder depending on the presence or absence of the error data. A disc reproducing device characterized in that. 3. A correction processing means comprising: means for reading information data from a disc to generate reproduction data; memory means for storing the reproduction data; and correction processing means for performing error correction processing on the reproduction data. Is a syndrome calculation means for judging whether or not there is erroneous data in the reproduction data read from the memory means, a syndrome register for storing the calculation result by the syndrome calculation means, and the number of the erroneous data from the calculation result. A logical operation unit that corrects the error data by calculating a position and a correction pattern, and writes the correction result in the memory means,
Working register means for storing the correction result of the logical operation unit, determination means for determining the presence / absence, number, and position of error data from the calculation result of the syndrome calculation means and the correction result of the logical operation unit. , A gate for supplying necessary processing instructions and clocks to these circuits, and for turning on / off the output of the processing instructions and clocks output to related circuits such as these logical operation units according to the number of error symbols which are detection results of error data. A disk reproducing apparatus having a program decoder having a circuit. 4. A correction processing means comprising: a means for reading information data from a disc to generate reproduction data; a memory means for storing the reproduction data; and a correction processing means for performing an error correction process on the reproduction data. Is a syndrome calculation means for judging whether or not there is erroneous data in the reproduction data read from the memory means, a syndrome register for storing the calculation result by the syndrome calculation means, and the number of the erroneous data from the calculation result. A logical operation unit that corrects the error data by calculating a position and a correction pattern, and writes the correction result in the memory means,
Working register means for storing the correction result of the logical operation unit, determination means for determining the presence / absence, number, and position of error data from the calculation result of the syndrome calculation means and the correction result of the logical operation unit. , A program decoder that supplies necessary processing instructions and clocks to these circuits, and on / off output of processing instructions and clocks output to related circuits such as logical operation units according to the number of error symbols that are the detection results of error data. A disk reproducing device having a control gate circuit. 5. The disc reproducing apparatus according to claim 1, wherein when the determination circuit determines that there is no error data as a result of the syndrome calculating means, a correction process thereafter is performed. A data reproduction method characterized by stopping. 6. A clock generation circuit for generating a reproduction clock synchronized with a data signal obtained by binarizing information data read from a disc, and a data signal demodulation circuit for demodulating the data signal to generate reproduction data. And a correction processing circuit that performs error correction processing on the reproduction data, the correction processing circuit determining whether or not there is erroneous data in the reproduction data read from the memory means, and the syndrome calculation circuit. A syndrome register for storing a calculation result by a calculation circuit; and a logical operation unit for calculating the number, position and correction pattern of the error data from the calculation result to correct the error data and writing the correction result in the memory means. A working register for storing the correction result of the logical operation unit, A determination circuit for determining the presence, number, and position of error data from the calculation result of the syndrome calculation circuit and the correction result of the logical operation unit, a program decoder for supplying processing instructions and clocks necessary for these circuits, and A signal processing circuit, comprising: a gate circuit for turning on and off the output of the processing instruction and the clock output from the program decoder depending on the presence or absence of error data. 7. A clock generation circuit for generating a reproduction clock synchronized with a data signal obtained by binarizing information data read from a disc, and a data signal demodulation circuit for demodulating the data signal to generate reproduction data. And a correction processing circuit that performs error correction processing on the reproduction data, the correction processing circuit determining whether or not there is erroneous data in the reproduction data read from the memory means, and the syndrome calculation circuit. A syndrome register for storing a calculation result by a calculation circuit; and a logical operation unit for calculating the number, position and correction pattern of the error data from the calculation result to correct the error data and writing the correction result in the memory means. A working register for storing the correction result of the logical operation unit, A determination circuit for determining the presence, number, and position of error data from the calculation result of the syndrome calculation circuit and the correction result of the logical operation unit, and a processing instruction and a clock necessary for these circuits, and
A signal processing circuit, comprising: a program decoder having a gate circuit that controls on / off of the output of the processing instruction and the clock output from the program decoder depending on the presence or absence of the error data.