JPH1173738A - Recording medium, data transmitting device, data receiving device and optical disk device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To properly detect identification data ID even when a synchronized pattern is not recognized properly and to surely demodulate main data by arranging the identification patterns at tops of each frame, assigning the specific identification data on the top frame of a small block and assigning the data of fixed value at the end side of a preamble on the top of the block. SOLUTION: A reproduced signal MO is inputted to a binarization circuit 30 of a demodulation part 19 of the optical disk device, and from the binary signal S1, synchronized patterns SY0-SY6 are detected and outputted by a synchronized pattern detecting circuit 35. By a pattern deciding circuit 37, the noncoincident number of bits between the reproduced data of continued 72 bits and the logic pattern of 72 bits constituted of a cluster synchronized signal and the 1st synchronized pattern SY0 is detected. When the error is generated in the synchronized pattern SY0 at the top sector of the cluster from the noncoincident number of bits, a timing detecting signal TS is produced by a pattern discriminating circuit 38.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a recording medium, a data transmitting device, a data receiving device, and an optical disk device.
In particular, the present invention can be applied to a system for transmitting computer data or the like in a predetermined block unit or recording the data on an optical disk. The present invention detects the identification data placed at the beginning of the main data portion with reference to the fixed value data assigned to the end of the preamble, so that even if the identification pattern cannot be correctly detected due to a flaw or the like, the identification data ID Is detected correctly so that the main data can be reliably demodulated.

[0002]

2. Description of the Related Art Conventionally, in an optical disk apparatus, desired data is processed on a block basis and recorded on an optical disk. Data recorded on an optical disk is determined based on identification data assigned to each of these blocks. Has been made to play correctly.

That is, for example, in a DVD (Digital Versatile Disc) composed of this type of optical disk device,
A video signal and an audio signal sequentially input are converted into a digital signal to generate a digital video signal and a digital audio signal. Further, the optical disk device compresses the digital video signal in a format prescribed by the Moving Picture Experts Group (MPEG) and multiplexes the digital video signal with a digital audio signal which has been similarly compressed (hereinafter, the multiplexed data is referred to as AV data). ), Scramble processing.

Further, as shown in FIG. 16, the optical disk device has an identification data ID (Identification) indicating an address.
Data) and the like are added to the AV data and then divided into predetermined blocks, and each block is provided with an error correction code, a preamble (Pre Able), and a postamble (Post).
Able) is added, and data of one cluster is generated from the data of each block. As a result, the optical disk apparatus records and reproduces AV data on the optical disk in units of the error correction processing block consisting of one cluster. In FIG. 16, the number of frames is indicated by a symbol Fr. Hereinafter, a portion of one cluster excluding the preamble and the postamble is referred to as a main data portion.

Further, the optical disk apparatus forms data of 16 sectors from the main data of one cluster,
Further, as shown in FIG. 17, 26 sync frames are formed from the data of each sector. Here, each sync frame includes a sync pattern SY in 91-byte AV data or the like.
0 to SY7 are allocated and formed.

In a DVD, each sync frame is composed of 8
Synchronization patterns SY0 to SY7 (hereinafter referred to as first to eighth synchronization patterns) are sequentially assigned in a predetermined order. That is, in each sector, the first synchronization pattern SY0 indicating the start of the sector is assigned at the beginning,
Subsequently, a first sync frame is formed by ID data and the like. In each sector, a sixth synchronization pattern SY5 is subsequently allocated, and a sync frame is formed by AV data and the like.

[0007] Further, each sector divides the remaining 24 frames into three.
And the even-numbered frame of each block includes sixth, seventh, and eighth synchronization patterns SY5, SY5,
SY6 and SY7 are assigned. The odd frames of each block include second to fifth synchronization patterns SY1 to SY.
Y4 are sequentially assigned.

Thus, in the DVD, the first half block, the center block, and the second half block of each sector are determined based on the synchronization patterns SY5, SY6, and SY7 of the even frames, and the synchronization patterns SY0 to SY of the odd frames are further determined.
4 makes it possible to determine which frame of each block, and based on the result of this determination, it is possible to demodulate the data reproduced sequentially.

On the other hand, in the preamble and the postamble, eight sync frames are respectively allocated, and the postamble includes the fifth to first synchronization patterns SY4 to SY1 sequentially in two frames. , And a fifth synchronization pattern SY4, and data having no meaning is assigned following these synchronization patterns.

In one cluster formed in this way, the identification data ID is arranged in the first frame of each sector following the synchronization pattern SY0, and each sector can be identified based on this identification data ID. Made
Further, data can be correctly demodulated based on the identification result. Therefore, in the optical disc device, the identification data ID is detected based on the first synchronization pattern SY0, or based on the synchronization pattern preceding the first synchronization pattern SY0, and based on the detected identification data. To process the reproduced data.

[0011]

By the way, in this type of optical disk apparatus, when AV data is recorded at high density, a synchronous pattern may not be detected correctly due to the influence of scratches or the like. In particular, the preamble may be damaged by overwriting recording of an adjacent cluster, and may not be correctly detected in the synchronization pattern SY0 arranged at the head of the main data portion. In addition, in a synchronization pattern, a logic pattern similar to each other, which cannot be generated in other portions, is assigned, and thus an erroneous detection may be performed with another synchronization pattern.

Thus, in this type of optical disc device, it may be difficult to detect the identification data ID at the correct timing in the first sector following the postamble, and this makes it difficult to detect one cluster from the identification data ID. Could not be decoded correctly.

The present invention has been made in view of the above points, and even when a synchronization pattern cannot be detected correctly due to a flaw or the like, a recording that can correctly detect the identification data ID and reliably demodulate the main data. A medium, a data transmitting device, a data receiving device, and an optical disk device are proposed.

[0014]

According to the present invention, there is provided a recording medium, a data transmission device, and an optical disk device, in which a first frame of a small block constituting a block which is a unit of recording and reproduction is replaced with another frame. A specific identification pattern different from the identification pattern arranged in the small block is allocated, and when the identification data for identifying each of the small blocks is allocated to the first frame of this small block, at least the end of the preamble is fixed. Assign value data.

In the data receiving device and the optical disk device, fixed value data arranged at the end of the preamble is detected, and identification data of a small block following the preamble is detected based on the detection result of the fixed value data. Then, the data of each block is decoded based on the detection result of the identification data.

When data of a fixed value is allocated to the end of the preamble, a pattern longer than the identification pattern can be allocated. Thus, even when the synchronization pattern cannot be correctly detected, the timing of the identification data can be reliably detected based on the data of the fixed value, and the identification data can be detected based on the timing.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(1) Configuration of the First Embodiment FIG. 2 is a block diagram showing an optical disk device according to the first embodiment of the present invention. This optical disc device 1
It is connected to information devices such as a computer, and records the data D1 of these information devices on the optical disk 2, and reproduces and outputs the data D1 recorded on the optical disk 2.

For this reason, the optical disk device 1 is provided with an MCU (Mi
Various control commands and the like are input and output to and from an external device via a crocontroler unit 3, and the operation of each block is controlled by a control unit 4 having a microcomputer configuration in response to a control command input from the external device. .

In the optical disk device 1, the data input unit 5 is constituted by a buffer memory, temporarily stores various data D1 input from an external device, and outputs the data D1 in units of predetermined blocks forming a cluster. ID, EDC
The encoding unit 6 applies a predetermined error detection code (EDC: Error Detecting Code) to the output data of the data input unit 5.
Code), and then perform scramble processing. Further I
The D, EDC encoding unit 6 applies the identification data ID described above with reference to FIG.
Etc. are sequentially added and output.

The ECC encoder 7 adds an error correction code (ECC: Erc) to the output data of the ID and the EDC encoder 6.
ror Correcting Code) and output to the memory 8.
The memory 8 temporarily holds the output data of the ECC encoder 7 and outputs the data to the modulator 10 in a predetermined order.

The modulator 10 receives data output from the memory 8 in a predetermined order, and outputs the output data to the NRZI.
(Non Return to Zero Inverted) Modulates and outputs modulated data DR. The magnetic field modulation driver 11 drives the modulation coil 12 based on the output data of the modulation unit 10. Thus, the optical disc apparatus 1 applies a modulating magnetic field to the laser beam irradiation position of the optical pickup 14, and performs thermomagnetic recording of data D1 from a computer or the like.

Here, the optical disk 2 is a magneto-optical disk, and a pregroove serving as a guide groove for a laser beam is formed meandering on the information recording surface. Spindle motor 1
3 drives the optical disk 2 at a predetermined rotation speed under the control of the servo circuit 18.

The optical pickup 14 is held so as to face the modulation coil 12 with the optical disk 2 interposed therebetween.
The optical disk 2 is moved in the radial direction of the optical disk 2 by a predetermined thread mechanism, and the optical disk device 1 can seek by this. The optical pickup 14 irradiates the optical disk 2 with a laser beam, receives the returned light by a predetermined light receiving element, and outputs a light receiving result.

The RF amplifier 15 includes the optical pickup 1
After performing the current-voltage conversion processing on the light receiving result of No. 4, the arithmetic processing is performed,
Thus, the reproduction signal MO whose signal level changes according to the polarization plane of the return light, the tracking error signal TE whose signal level changes according to the tracking error amount, and the focus error signal FE whose signal level changes according to the focus error amount. ADIP (Address In Pre-groove) signal A whose signal level changes according to the meandering of the pre-groove
Output DIP. Further, the optical pickup 14 intermittently raises the light amount of the laser beam during recording.

The servo circuit 18 receives the ADIP signal AD
The spindle motor 13 is driven so that the center frequency of the IP becomes a predetermined frequency, whereby the optical disc 2 is rotationally driven under the condition that the linear velocity is constant. Also, the servo circuit 18
Moves the objective lens of the optical pickup 14 right and left and up and down according to the tracking error signal TE and the focus error signal FE, thereby performing tracking control and focus control of the optical pickup 14.

The ADIP signal demodulation circuit 16 receives the ADIP signal ADIP by a built-in frequency demodulation circuit, and generates a frequency demodulation signal whose signal level changes according to the displacement of the meandering period of the groove. Further, the ADIP signal demodulation circuit 16
Detects the position information of the laser beam irradiation position recorded on the optical disc 2 by the displacement of the meandering cycle of the groove by binarizing and sequentially latching the frequency demodulated signal. The ADIP signal decoding unit 17
The output data of the signal demodulation circuit 16 is detected as an error and output to the MCU unit 3.
The unit 3 detects an access position and can access a desired recording / reproducing position.

At the time of reproduction, the demodulation unit 19 generates a clock from the reproduction signal MO, and generates various reference signals necessary for processing the reproduction signal MO based on the clock. Further, the demodulation unit 19 generates reproduced data by binarizing the reproduced signal, and decodes the decoded data D3 from the reproduced data. I
The D decoding unit 20 outputs the identification data I from the decoded data D3.
D is detected, and the detection result is notified to a built-in memory control circuit.

The memory 21 sequentially inputs the decoded data D3 output from the demodulation unit 19 to a predetermined area by the address control of the memory control circuit.
Are output in a predetermined order. The ECC decoding unit 22
The decoded data D3 held in the memory 21 is subjected to error correction processing using an error correction code added to the decoded data D3, and is output.

The EDC decoding unit 23 performs error detection processing on the output data of the ECC decoding unit 22 and outputs the data. The data output unit 24 temporarily holds the output data D1 of the EDC decoding unit 23 and outputs the data to an external device. I do.

FIG. 3 is a block diagram showing in detail the generation of the recording data DR in the optical disk device 1. I
The D and EDC encoding unit 6 scrambles data (called main data) D1 output from the data input unit 5 by a built-in scramble circuit 6A. Further, the ID and EDC encoder 6 adds control data CTRL, identification data ID, and reserve data AUX to the main data D1 for one sector. Here, the control data CTRL is used for an identification signal of an A / B track in a so-called double spiral disc and a reserve for a future disc format, and 1-byte data based on logic 0 is assigned to the optical disc 2. . The identification data ID is used to identify each sector and decode the reproduced data, and 4-byte data is allocated. Data AUX for reserve
Are allocated so that they can be used variously as needed, and here, 6 bytes of data with logical 0 are allocated.

The ID and EDC encoding unit 6 uses a built-in parity generation circuit 6B to add a 2-byte parity (IE) for error correction to the control data CTRL and the identification data ID.
C). Further, the arithmetic circuit 6C converts the reserve data AUX and the main data D1 into a CRC (Cycl
ic Redundancy Check) code to generate a 32-bit error detection code EDC. It should be noted that a total of 12 × 172 bytes of data including the control data CTRL and the like is allocated to this one sector.

The ECC encoder 7 generates an error correction code ECC of a product code format in units of the data of 16 sectors generated in this manner, and then performs an interleave process by inputting / outputting data from / to the memory 8. The following modulator 10
Modulates the output data of the memory 21 by RLL (1, 7) according to the modulation rule shown in FIG. That is, for example, in FIG.
As shown in the second row of (a), when the modulated end data is logic 0 (Preceding channel bit), data of logic 00 is continuous (Current Input bits), and data of logic 1 is continued ( Following Input bits), logic 00
Is input to the logical 000 modulation data (Channel B).
its RLL (1,7)).

Further, the modulation section 10 includes a built-in DSV together with data DP for forming a preamble and a postamble.
The DSV (Digital Sum Value) is sequentially controlled by the control circuit 10A.
3) Control data for control is added, thereby suppressing low-frequency components of the modulation data DR. The modulating unit 10 performs NRZI modulation on the 16-sector data, preamble, and postamble data thus generated by the NRZI modulation circuit 10B, and adds a synchronization pattern to the modulated data.

FIG. 5 is a table showing the data structure of one sector generated by the ID and EDC encoder 6 in this manner. In this embodiment, after each sector, control data CTRL, identification data ID, parity IEC, and reserve data AUX continue from the beginning,
Main data is allocated, and an error detection code EDC is arranged at the end of the last sync frame. This 1
For the data of the sector, the optical disc device 1
An error correction code of 1 rows × 172 bytes is added by the CC encoding unit 7, and in this embodiment, one sector is 13 rows × 2 = 26 as a whole.
It is formed by a sync frame.

FIG. 6 is a chart showing the structure of one cluster generated in this manner. In this embodiment, one sector is formed by 26 sync frames formed by main data. Further, a preamble and a postamble are arranged on data of 16 sectors to form one cluster. Here, the preamble and the postamble are formed by 10 sync frames and 6 sync frames, respectively. Further, a predetermined synchronization pattern SY0 to SY6 is added to each sync frame in the modulation unit 10.

That is, seven types of synchronization patterns SY0 to SY6 shown in FIG. 7 are selectively assigned to each sync frame. Here, each synchronization pattern SY0 to SY
6 is suitable for PLL circuit synchronization, each value is different,
In addition, data of a logical pattern that does not occur in other parts is assigned. Also, the number of sync frames is smaller than the number of sync frames, thereby reducing the increase in redundancy caused by allocating the synchronization pattern.

Here, as shown in FIGS. 6 and 8, the modulating unit 10 controls the main data portion so that a synchronization pattern by the same combination is not generated within one sector between successive sync frames. That is, when a continuous frame is arbitrarily selected, the synchronization pattern is arranged such that the combination of the synchronization patterns assigned to this continuous frame is different from the combination of the synchronization patterns assigned to any other continuous frames. . As a result, when a continuous synchronization pattern can be correctly reproduced, the modulation unit 10 can specify a sync frame by using two consecutive synchronization patterns.

Further, as shown in FIG.
In the main data section, even in the synchronization pattern before and after one synchronization pattern is sandwiched, within one sector,
In order not to generate a synchronization pattern by the same combination, that is, when three consecutive frames are arbitrarily selected, the combination of the synchronization patterns assigned to the first frame and the last frame of the three consecutive frames is different from the other. The synchronization pattern is arranged so as to be different from the combination of the synchronization patterns assigned to the first frame and the last frame of any three consecutive frames. Thereby, the modulation unit 10 can specify the sync frame by the preceding and following synchronization patterns even when the synchronization pattern sandwiched between the three consecutive synchronization patterns cannot be correctly reproduced or when the reproduction is erroneously performed. I do.

In this way, in such a continuous synchronization pattern, and in a synchronization pattern before and after one synchronization pattern, a synchronization pattern by the same combination is not generated within one sector. For example, even for four consecutive synchronization patterns, the same combination of synchronization patterns does not occur within one sector.

Thus, a sync frame can be specified also by the synchronization pattern of three consecutive frames, and even when two or more continuous synchronization patterns cannot be correctly detected at a specific location, the sync frame is determined by the synchronization pattern of another location. Can be specified. Further, even if any one of the synchronization patterns is erroneously detected based on the synchronization patterns of four consecutive frames, the erroneously detected synchronization pattern can be specified, and the sync frame can be correctly specified.

Further, a first sync pattern SY0 different from other sync frames is assigned to the first sync frame of each sector, so that the start of each sector can be easily detected by this specific sync pattern SY0. Has been made.

On the other hand, in the preamble (FIG. 6), the seventh synchronization pattern SY6 is arranged at the head side so as to be continuous, so that the head of the cluster can be easily detected. Further, the synchronization patterns SY2, SY1,... Other than the seventh synchronization pattern SY6 are arranged as approaching the main data portion, so that the closer to the first sector, the more precise the position in the preamble can be characterized. .

On the other hand, in the postamble, the seventh synchronization pattern SY6 is repeated so that the end of the cluster can be easily specified.

FIG. 10 is a block diagram showing a circuit for generating data DP to be allocated to a preamble and a postamble in modulation section 10, and includes a scramble circuit 10C.
It consists of. In the optical disc device 1, the scramble circuit 10C scrambles continuous data based on logic 0 to generate data to be assigned to a preamble and a postamble. Note that the scramble processing for the main data section is also performed by a similar circuit configuration.

In this scramble circuit 10C,
At the start of the preamble, an 18-stage shift register 1
The initial value data DP1 is set to 0D, and the data held in the shift register 10D is sequentially transferred by a bit clock. Further, the scramble circuit 10C inputs the output data of the seventh stage of the shift register 10D and the output data of the final stage to the remainder operation circuit 10E, and calculates the remainder by modulo 2 from the sum data of these output data. The remainder is input to the first stage of the shift register.

Further, the scramble circuit 10C inputs the output data of the final stage of the seventh stage of the shift register 10D and the input data of logic 0 to the remainder operation circuit 10F, where the remainder data is modulo 2 from the sum data. And outputs the remainder as data DP to be allocated to the postamble and the preamble.

Here, the initial value data DP1 is set so that the logic level of the output data DP does not converge to logic 0 or 1.
Data according to a predetermined logic level is allocated. As a result, in the optical disc device 1, in each sync frame of the preamble, data having a predetermined fixed value is allocated. In this embodiment, of these, 48-bit data (constituted by hatching in FIG. 6) assigned to the end of the main data section is used for detecting the identification data ID. Note that this 48-bit data is logical "1001001001".
00010100010100100100000100100100100010 ″, and is hereinafter referred to as a cluster synchronization signal.

FIG. 1 shows a demodulation section 19 of the optical disk apparatus 1 for reproducing data recorded in cluster units in this manner.
FIG. 2 is a block diagram showing the details together with the peripheral configuration. The demodulation unit 19 equalizes the waveform of the reproduction signal MO output from the RF amplifier 15 and then inputs the reproduced signal MO to the binarization circuit 30. The binarizing circuit 30 outputs a reproduced signal M output from the waveform equalizing circuit.
O is binarized and a binarized signal S1 is output. The PLL circuit 31 generates a clock CK based on the binarized signal S1.
To play. The counter 32 is a ring counter,
A frame synchronization signal FCK whose signal level rises at the timing of the synchronization pattern by counting the clock CK with reference to the timing signal output from the OR circuit 33, and a synchronization signal whose signal level rises in a wider range than this frame synchronization signal FCK The detection window signal FCKW is output.

The demodulation circuit 34 detects reproduced data by sequentially latching the binary signal S1 with reference to the clock CK. Further, the demodulation circuit 34 decodes the decoded data D3 from the reproduced data and outputs the decoded data according to the demodulation rule shown in FIG. 11 as compared with FIG. That is, for example, as shown in the first row of FIG. 11, when the decoded data is logic 10 (Preceding channel bits), the logic 00
0 playback data continues (Current channel bits), followed by logic 1 or 0 playback data (Following
channel bits), and decodes the reproduced data of logic 000 into decoded data (decoded information bits) of logic 00.

The synchronization pattern detection circuit 35 detects the synchronization patterns SY0 to SY6 from the binarized signal S1 and outputs a detection result. That is, the synchronization pattern detection circuit 35
Synchronization pattern detection circuits 35A to 35A to detect synchronization patterns SY0 to SY6 and output corresponding detection results.
35G. Synchronous pattern detection circuit 35
In a shift register (not shown) corresponding to the bit length of the synchronization patterns SY0 to SY6, the binary signal S1 is sequentially latched and transferred by the clock CK,
A predetermined memory is accessed by the parallel output of the shift register, and when the synchronization pattern SY0 to SY6 appears in the binary signal S1, the logic level of the corresponding bit output of this memory is raised to generate the synchronization pattern SY0.
To SY6 are output.

The AND circuits 36A to 36G respectively output the synchronization patterns SY0 to SY0 output from the synchronization pattern detection circuit 35.
SY6 detection result and synchronization signal detection window signal F
The OR circuit 33 outputs a logical product signal with the CKW, and the OR circuit 33 outputs a logical sum signal of the logical product signals output from the AND circuits 36A to 36G as a timing signal. Thus, in the demodulation unit 19, a so-called flywheel circuit is configured by the counter 32, the synchronization pattern detection circuit 35, the AND circuits 36A to 36G, and the OR circuit 33, and the signal level rises at the timing when the synchronization pattern appears in the binary signal S1. Generate a frame synchronization signal FCK.

The pattern determination circuit 37 has a 72-bit shift register corresponding to the bit length of the synchronization pattern and the cluster synchronization signal, and sequentially latches the binary signal S1 by the clock CK and transfers this shift register. Further, the pattern determination circuit 37 is composed of a cluster synchronization signal followed by a synchronization pattern SY0 of the main part.
The parallel output of the shift register is compared with the bit logical pattern, and the number of mismatched bits is notified to the frame discrimination circuit 38.

When the cluster synchronizing signal and the following main part synchronizing pattern SY0 appear correctly in the parallel output of the shift register, the pattern judging circuit 37 notifies the frame discriminating circuit 38 of the number of mismatched bits of the value 0. I do. If the cluster synchronization signal and the subsequent main part synchronization pattern SY0 do not correctly appear in the parallel output due to flaws or the like, the number of mismatched bits according to the influence of the flaws or the like is notified.

The frame discriminating circuit 38 executes a predetermined processing procedure according to the cycle of the rising of the frame synchronizing signal FCK. The result of detecting the synchronizing pattern obtained through the AND circuits 36A to 36G, The start timing of the main data portion is detected based on the number. Thereby, the frame discrimination circuit 38
Outputs a timing detection signal TS whose signal level rises at the timing when the identification data ID and the subsequent parity IEC appear in the decoded data D3 based on the timing detection result.

The frame discrimination circuit 38 specifies the number of a sync frame in each sector from the detection result of the synchronization pattern obtained via the AND circuits 36A to 36G, and outputs the number SYNCO of the sync frame.
At this time, the frame discriminating circuit 38 specifies the number of the sync frame from the detection results of the sync patterns sequentially obtained for the three consecutive sync frames, thereby effectively avoiding false detection of the sync frame. Thus, in this embodiment, a continuous synchronization pattern and 1
In a continuous synchronization pattern with one synchronization pattern interposed therebetween, the same combination does not exist in one sector, so that a sync frame can be reliably specified in this manner.

The ID decode section 20 includes a latch circuit 20A
, The decoded data D3 is sequentially latched based on the timing detection signal TS, so that the identification data I
D, fetch parity IEC. Further, the ID decoding unit 20 corrects the error of the fetched identification data ID by the parity IEC in the error correction circuit 20B.
Notify the memory control circuit 20C. Memory control circuit 20
C specifies the sector of the decoded data D3 from the detection result of the identification data ID, and specifies the sync frame of the decoded data D3 from the sync frame number SYNO obtained from the frame discrimination circuit 38. , The address of the memory 21 is controlled.

At this time, the memory control circuit 20C once
When the identification data ID is detected and / or the sync frame number SYNO is notified from the frame discrimination circuit 38, the frame synchronization signal FCK,
By controlling the address of the memory 21 by counting the clock CK, the decoded data D3 is stored in the memory 21 in a correct arrangement even when the demodulation unit 19 cannot temporarily detect the synchronization pattern due to a bit error or the like. Thus, the ID decoding unit 20 outputs the decoded data D
3 is decoded into the original computer data D1 with the correct arrangement.

FIG. 12 is a flowchart showing a processing procedure in the frame discrimination circuit 38. The frame discrimination circuit 38 repeats this processing procedure according to the cycle of the frame synchronization signal FCK, and outputs a timing detection signal TS to the ID decoding unit 20. That is, the frame discriminating circuit 3
8, when the frame synchronization signal FCK rises, the process moves from step SP1 to step SP2, where the first synchronization pattern SY0 is detected at a timing corresponding to the frame synchronization signal FCK, and goes up backward from the synchronization pattern. Seven consecutive synchronization patterns (SY2-SY
5-SY6-SY5-SY1-SY6-SY0) are determined in the correct order. The frame discrimination circuit 38 takes in the detection result of the synchronization pattern obtained via the AND circuits 36A to 36G based on the frame synchronization signal FCK and holds the detection result for a predetermined period. The judgment in this processing procedure is executed based on the detection result.

If a positive result is obtained here,
Since the synchronization pattern described with reference to FIG. 6 is sequentially and correctly detected during a period of 7 frames from the head frame of the main data portion, the process proceeds to step SP3, and the first synchronization pattern SY0 is correctly detected. Judge that it was done. In this case, in the sync frame corresponding to the frame synchronization signal FCK that has started this processing procedure, the decoded data D including the identification data ID and the parity code IEC are included in the second to seventh bytes following the synchronization pattern.
3 is obtained, the frame discrimination circuit 38 proceeds to step SP4 and outputs a timing detection signal TS to the ID decoding unit 20, whereby the ID decoding unit 20
To detect the identification data ID. As a result, in this embodiment, the identification data ID is correctly detected by the ID decoding unit 20, and the address control of the memory 21 is executed based on the detected identification data ID.

After outputting the timing detection signal TS, the frame discrimination circuit 38 moves to step SP5 and ends this processing procedure.

On the other hand, if a negative result is obtained in step SP2, the frame discriminating circuit 38 proceeds to step SP6, where the first synchronization pattern SY0 is detected at a timing corresponding to the frame synchronization signal FCK, and this synchronization pattern is detected. Six synchronous patterns (SY5-SY6-SY5-SY1-SY6-SY6-S
It is determined whether or not (Y0) has been detected in the correct order.

Here, if a positive result is obtained, in this case,
Although the reliability is lower than when a positive result is obtained in step SP2, it can be determined that the first synchronization pattern SY0 has been correctly detected with sufficient reliability. Execute the processing procedure.

On the other hand, if a negative result is obtained in step SP6, the frame discriminating circuit 38 proceeds to step SP7, where the first synchronization pattern SY0 is detected at a timing corresponding to the frame synchronization signal FCK, and this synchronization pattern is detected. It is determined whether or not five synchronous patterns (SY6-SY5-SY1-SY6-SY0) have been detected in the correct order consecutively upward from the pattern.

Here, if a positive result is obtained, in this case,
Although the reliability is lower than when a positive result is obtained in step SP6, it can be determined that the first synchronization pattern SY0 has been correctly detected with sufficient reliability. Execute the processing procedure.

On the other hand, if a negative result is obtained in step SP7, the frame discrimination circuit 38 proceeds to step SP8, where the first synchronization pattern SY0 is detected at a timing corresponding to the frame synchronization signal FCK, and this synchronization pattern is detected. It is determined whether or not four synchronization patterns (SY5-SY1-SY6-SY0) have been detected in the correct order consecutively upward from the pattern.

If an affirmative result is obtained here, the reliability is lower than in the case where an affirmative result is obtained in step SP7, but the first result is obtained with sufficient reliability.
Since it can be determined that the synchronization pattern SY0 has been correctly detected, the process moves to step SP3, and the same processing procedure is executed.

On the other hand, if a negative result is obtained in step SP8, the frame discriminating circuit 38 proceeds to step SP9, where the first synchronization pattern SY0 is detected at a timing corresponding to the frame synchronization signal FCK, and this synchronization pattern is detected. It is determined whether or not three synchronous patterns (SY1-SY6-SY0) have been detected in the correct order in succession in reverse to the pattern.

If a positive result is obtained here, the first synchronization pattern SY0 is also generated with sufficient reliability, although the reliability is lower than in the case where a positive result is obtained in the immediately preceding step SP8. Since it can be determined that the detection has been correctly performed, the process proceeds to step SP3.
A similar processing procedure is executed.

On the other hand, if a negative result is obtained in step SP9, the frame discriminating circuit 38 proceeds to step SP10 and detects the first synchronization pattern SY0 at the timing corresponding to the frame synchronization signal FCK.
In addition, it is determined whether or not two synchronization patterns (SY6-SY0) have been detected in the correct order consecutively, going backwards from the synchronization pattern.

If a positive result is obtained here, the first synchronization pattern SY0 is also generated with sufficient reliability, although the reliability is lower than in the case where a positive result is obtained in the immediately preceding step SP9. Since it can be determined that the detection has been correctly performed, the process proceeds to step SP3.
A similar processing procedure is executed.

On the other hand, if a negative result is obtained in step SP10, the frame discriminating circuit 38 proceeds to step SP11, in which the pattern discriminating circuit 37 converts the continuous 72-bit reproduced data into the cluster synchronizing signal and the first synchronizing signal. It is determined whether or not the pattern completely matches the pattern SY0. If an affirmative result is obtained here, it can be determined that the first synchronization pattern SY0 has been correctly detected with sufficient reliability in this case.
Then, the same processing procedure is executed.

On the other hand, if a negative result is obtained in step SP11, the frame discriminating circuit 38 proceeds to step SP12, and determines whether or not the first synchronization pattern SY0 is detected at a timing corresponding to the frame synchronization signal FCK. In this case, although the reliability is low, since it can be determined that the first synchronization pattern SY0 has been correctly detected, the process proceeds to step SP3, and the same processing procedure is executed.

On the other hand, if a negative result is obtained in step SP12, the frame discriminating circuit 38 proceeds to step SP13, where the pattern discriminating circuit 37
Due to the discrepancy of less than or equal to bits, the reproduced data of continuous 72 bits is converted into the cluster synchronization signal and the first synchronization pattern SY.
It is determined whether the value matches 0. If a positive result is obtained here, the reliability is low in this case, but it can be determined that the first synchronization pattern SY0 has been correctly detected, and the process proceeds to step SP3 to execute a similar processing procedure. .

On the other hand, when the first synchronization pattern SY0 cannot be detected by the synchronization pattern detection circuit 35 and the pattern
When the bit reproduced data D2 is compared with the cluster synchronization signal and the first synchronization pattern SY0, if a mismatch of 3 bits or more occurs, it is determined that a sync frame start timing other than the head sync frame of each sector is started. If so, the process proceeds to step SP14, where it is determined that the first synchronization pattern SY0 is difficult to detect. And in this case,
The process proceeds to step SP5 without outputting the timing detection signal TS to the ID decoding unit 20, and the processing procedure ends.

(2) Operation of the First Embodiment In the above configuration, the data D1 input from the computer or the like (FIG. 2) is transmitted through the data input unit 5 in units of predetermined blocks constituting a cluster. , EDC encoding unit 6, where the data is scrambled, and control data CTRL, identification data ID, parity IEC of identification data, and reserve data AUX are added in units of sectors (FIGS. 3 and 5). ECC encoder 7
In, after the error correction code of the product code format is added,
After being interleaved by the input and output of the memory 8,
PLL (1, 7) modulation is performed in the modulation unit 10 (FIG. 4). Then, after a preamble and a postamble are allocated, a control bit for DSV control is added. After that, after the NRZI modulation, a synchronization pattern is added to generate recording data DR, and the modulation coil 12 is driven according to the recording data DR to perform thermomagnetic recording on the optical disc 2 in cluster units. .

At the time of recording in this manner, in each sync frame (FIG. 6), the synchronization pattern by the same combination is not continued in one sector, that is, a continuous frame is arbitrarily selected. In this case, the combination of the synchronization patterns assigned to the consecutive frames is
Seven types of synchronization patterns are selectively allocated so as to be different from the combination of the synchronization patterns allocated to any other continuous frames (FIG. 8).

Also, in the synchronization pattern before and after the one synchronization pattern, the same combination of synchronization patterns is not generated within one sector, that is, when three consecutive frames are arbitrarily selected. To
The combination of the synchronization patterns assigned to the first and last frames of the three consecutive frames is
Seven types of synchronization patterns are selectively assigned so as to be different from the combination of the synchronization patterns assigned to the first frame and the last frame of any other three consecutive frames (FIG. 9).

Thus, in each cluster, in one sector, the combination of the synchronization patterns assigned to the three consecutive frames arbitrarily selected is different from the combination of the synchronization patterns assigned to the other three consecutive frames. Is held. Similarly, the combination of the synchronization patterns assigned to the four consecutive frames is kept different from the combination of the synchronization patterns assigned to the other four consecutive frames selected in the same manner.

Thus, in the optical disk device 1, a sync frame is specified from a continuous synchronization pattern, and the sync frame can be specified correctly.

In the preamble, at the beginning,
The seventh synchronization pattern SY6 is arranged so as to be continuous,
As the position approaches the main data portion, synchronization patterns SY2, SY1,... Other than the seventh synchronization pattern SY6 are arranged, and in the postamble, the seventh synchronization pattern SY6 is repeated.

Further, in each sync frame of the preamble, data of logic 0 is scrambled by a scramble circuit 10C in which initial value data DP1 is set in a shift register 10D of 18 stages (FIG. 10).
As a result, data DP having a fixed value determined by the scramble processing is assigned. 48-bit data allocated to the end of the main data section (FIG. 6)
Is logical “1001001001000101000101001001000001001001
00100010 ”of the recording data DR, and the identification data ID
A cluster synchronizing signal is formed to assist in the detection of.

On the other hand, at the time of reproduction, in the optical disc apparatus 1 (FIG. 2), a reproduced signal whose signal level changes in accordance with the polarization plane of the returned light from the returned light obtained by irradiating the optical disc 2 with a laser beam. MO is obtained, and the reproduced signal MO is converted into decoded data D3 in the demodulation unit 19. Further, the decoded data D3 is subjected to deinterleave processing by input / output of the memory 21, and the ECC decoding unit 2
After the error correction processing by step 2, the data is descrambled. The error detection processing is performed by the EDC decoding unit 23, and the data is output from the data output unit 24.

In the above processing, the reproduced signal MO (FIG. 1) is converted by the demodulation section 19 into the binarizing circuit 3
After being converted into a binarized signal S1 by 0, the PLL circuit 3
At 1, the clock CK is reproduced from the binary signal S1. The binarized signal S1 is sequentially processed by the decoding circuit 34 using the reproduced clock CK to decode the decoded data D3.

In parallel with this series of processing, the synchronization pattern detection circuit 35 detects seven types of synchronization patterns S
When Y0 to SY6 appear in the binary signal S1, a pattern detection signal whose signal level rises is generated.
After the pattern detection signals are gated by AND circuits 36A to 36G by the synchronization signal detection window signal FCKW generated by counting the clock CK, the OR circuit 33 generates a logical sum signal. Further, the counter 32 is reset by the OR signal, thereby generating a frame synchronization signal FCK whose signal level rises at the timing of the synchronization pattern and a synchronization signal detection window signal FCKW whose signal level rises in a wider range than the frame synchronization signal FCK. Is done.

Further, the pattern determining circuit 37 detects the number of mismatched bits between the continuous 72-bit reproduced data and the 72-bit logical pattern composed of the cluster synchronization signal and the first synchronization pattern SY0. The number of mismatched bits is notified to the frame discrimination circuit 38.

In the frame discrimination circuit 38, the first synchronization pattern SY0 is detected at the timing of the frame synchronization signal FCK following the arrangement of the synchronization patterns in a predetermined order, based on the detection result of the synchronization pattern detection circuit 35. (FIG. 12, steps SP2, SP6,
SP7, SP8, SP9, SP10), in these cases, based on the timing of the frame synchronization signal FCK, the timing detection signal TS whose signal level rises between the second and sixth bytes of the corresponding sync frame. Is generated.

Similarly, in the frame discriminating circuit 38, based on the number of mismatched bits notified from the pattern discriminating circuit 37, it is determined whether all the continuous 72-bit reproduced data have been correctly detected and the first synchronization pattern SY0 has been detected. It is determined (step SP11 in FIG. 12) that the timing detection signal TS is generated based on the timing of the frame synchronization signal FCK.

On the other hand, only the first synchronization pattern SY
When 0 is detected (FIG. 12, step SP12), it is conceivable that an error has occurred in the reproduced data so far in the leading sector of the cluster, and is detected in a sector other than the leading sector of the cluster. In this case, the timing detection signal TS is generated based on the timing of the frame synchronization signal FCK.

Further, in the frame discriminating circuit 38, the reproduced data of 72 bits which are continuous and have 2 bits or less of mismatch are notified from the cluster synchronization signal and the first synchronization pattern SY.
It is determined whether they match 0 (FIG. 12, step SP1).
3), whereby the first sector in the cluster is
When an error occurs in the synchronization pattern SY0 itself, this is remedied and a timing detection signal TS is generated.

That is, since the synchronization pattern SY0 has a 24-bit length, if a mismatch of 2 bits or less is detected between the synchronization pattern SY0 and the cluster synchronization signal in consecutive 72 bits, a bit error is detected in the synchronization pattern SY0. Occur, and the probability that the synchronization pattern cannot be detected correctly can be determined to be extremely high. In this case, it is difficult to determine the correct timing when the head of the cluster is detected based only on the synchronization pattern SY0, whereas in this embodiment, the correct timing can be determined. As a result, even when the synchronization pattern cannot be correctly detected due to a flaw or the like, the identification data ID can be correctly detected and the main data can be reliably demodulated.

In this manner, the start of the head sector of the cluster and the start of the head sector of each sector are detected, and the frame discrimination circuit 38 determines the correspondence between the three consecutive synchronization patterns in each sector. The number SYNO of the sync frame to be synchronized is detected, and this number SYNO is notified to the ID decoding unit 20. At this time, in this embodiment, in a continuous synchronization pattern and a continuous synchronization pattern sandwiching one synchronization pattern, a synchronization pattern is allocated so that a synchronization pattern by the same combination does not occur in one sector. As a result, the number of the sync frame is specified without fail.

In the ID decoding section 20, the identification data ID allocated to the first sync frame of each sector is detected together with the parity code IEC based on the timing detection signal TS. Furthermore, this identification data ID
, The sector of the decoded data D3 input to the memory 21 is specified, and the sync frame in each sector is specified by the sync frame number SYNO notified from the frame discrimination circuit 38. Thus, the address control of the memory 21 is executed based on the identification data ID and the sync frame number SYNO, and the decoded data D3 is processed in a correct arrangement. At this time, if the timing of the identification data ID and the sync frame number SYNO cannot be correctly detected by the frame discrimination circuit 38, the address of the memory 21 is controlled by the interpolation processing in which the clock and the frame synchronization signal are counted.

(3) Effects of the First Embodiment According to the above configuration, the start of the head sector is started with reference to the cluster synchronization signal consisting of fixed value data arranged immediately before the head sector of the cluster. By detecting the timing, even when the synchronization pattern cannot be correctly detected due to a flaw or the like, it is possible to reliably detect the identification data ID assigned to the first sync frame and correctly process the decoded data.

Also, by assigning a specific synchronization pattern SY0 not assigned to other sync frames to the first sync frame of each sector, it is possible to reliably detect the start timing of each sector and detect identification data. Can be.

Further, in each sector, a synchronization pattern is assigned so that the same combination does not occur in successive synchronization patterns, and furthermore, the same synchronization pattern is interposed between one synchronization pattern. By allocating the synchronization pattern so that no combination occurs, the sync frame can be reliably specified, and the decoded data can be processed with the correct arrangement.

(4) Second Embodiment FIG. 13 is a block diagram showing a demodulation section of an optical disk device according to a second embodiment of the present invention together with peripheral circuits in comparison with FIG. The demodulation unit 49 according to this embodiment separately detects a cluster synchronization signal. FIG. 1
In FIG. 3, the same components as those described above with reference to FIG. 1 are denoted by the corresponding reference numerals, and redundant description will be omitted.

The demodulation unit 49 includes a pattern determination circuit 50
In, a cluster synchronization signal is detected. That is, FIG.
As shown in FIG. 4, in the demodulation unit 49, the binary signal S
1 (FIG. 14 (A)), the clock CK is counted by the counter 51, and the frame synchronization signal FCK and the synchronization signal detection window signal FCKW (FIG. 14 (E))
Generate Further, a window signal CW for detecting a cluster synchronization signal corresponding to the cluster synchronization signal (FIG. 14C).
Generate

In the pattern determination circuit 50, similarly to the pattern determination circuit 37, it is determined whether or not the 48-bit reproduced data detected by sequentially latching the binarized signal S1 matches the cluster synchronization signal. When the cluster synchronization signal appears in the binarized signal, a detection signal SC (FIG. 14B) of the cluster synchronization signal whose signal level rises is output. The AND circuit 52 uses the cluster synchronization signal detection window signal CW to generate a cluster synchronization signal detection signal SC.
And output.

In this embodiment, the first embodiment
The detection signal SY0 of the synchronization pattern SY0 of FIG.
(D) Window signal F for synchronizing signal detection to gate
The window width WC of the cluster synchronization signal detection window signal CW is set to be narrower than CKW,
As a result, a cluster synchronization signal in which the same logical pattern may occur even in a sync frame is reliably detected.

The frame determining circuit 53 detects and outputs the sync frame number SYNO in the same manner as the frame determining circuit 38 described above with reference to FIG. Further, the start timing of a sector is detected by the processing procedure shown in FIG. 15 in comparison with FIG. 12, and a timing detection signal TS is output. In FIG. 15, the same processing procedures as those in FIG. 12 are denoted by the corresponding reference numerals, and the description will be simplified.

That is, the frame discriminating circuit 53 starts the processing procedure from step SP1 and detects the start timing of the sector with reference to the successive synchronization pattern (steps SP2, SP6, SP7, SP8, SP9,
SP10), and outputs a timing detection signal (SP3,
SP4). In this series of processing, the synchronization pattern SY
If the first synchronization pattern SY0 cannot be detected following step 6, the process proceeds from step SP10 to step SP21, and the cluster synchronization signal can be detected from the output signal of the AND circuit 52 within the window of the cluster synchronization signal detection window signal CW. Is determined.

As described above, even when only the cluster synchronization signal is used as a reference, the detection result is restricted by the cluster synchronization signal detection window signal CW based on the frame synchronization signal FCK, so that the frame synchronization signal can be detected with high accuracy. Thus, the head of the main data can be detected. As a result, the frame discriminating circuit 53 performs step SP
In 21, when a positive result is obtained, the process proceeds to step SP 3, and the timing signal TS is output. On the other hand, when a negative result is obtained, the process proceeds to step SP 13 and the process proceeds to step SP 13.
The start of the sector is determined from the 2-bit reproduced data.

According to the configuration shown in FIGS. 13 to 15, when the synchronization pattern cannot be correctly detected due to a flaw even if only the cluster synchronization signal is used alone, the identification data ID
Is detected correctly, and the main data can be reliably demodulated.

(5) Other Embodiments In the above embodiment, the case where the last 48 bits of the preamble obtained by scrambling logical 0 data are used as the cluster synchronization signal has been described. The invention is not limited to this, and similar effects can be obtained by using various numbers of bits as the cluster synchronization signal.

In the above embodiment, the logic 0
Has been described as the case where the end of the preamble obtained by scrambling the data is used as the cluster synchronization signal. However, the present invention is not limited to this, and dedicated fixed data may be allocated as the cluster synchronization signal. At this time, the scrambling process may be omitted. For example, in this case, if data of F5F5F5F5h is allocated, 48-bit modulated data DR obtained by repeating the logic "1001000100" four times by modulation is obtained, and the start timing of the main data may be detected from the fixed data. .

Further, in the above-described embodiment, the case where one sector is composed of 26 sync frames has been described. However, the present invention is not limited to this, and is widely applied to the case where one block is composed of various sync frames. can do.

In the above-described embodiment, the case where seven types of synchronization patterns are arranged in one sector has been described. However, the present invention is not limited to this, and various types of synchronization patterns are arranged in one sector. Can be widely applied to.

Further, in the above-described embodiment, a case has been described where each frame is specified by the synchronization pattern so that the PLL circuit can be synchronized. However, the present invention is not limited to this. The present invention can be widely applied to a case where an identification pattern is arranged.

Further, in the above-described embodiment, a case has been described in which computer data is thermomagnetically recorded on an optical disk. However, the present invention is not limited to this, and AV data is recorded on a phase-change optical disk or a write-once optical disk. The present invention can be widely applied to recording and further to recording various data.

In the above-described embodiment, the case where the present invention is applied to the optical disk apparatus has been described. However, the present invention is not limited to this, and desired data can be transmitted through various transmission paths such as a magnetic recording medium. It can be widely applied to transmission.

Further, in the above-described embodiment, the case where desired data is recorded on a recording medium formed of an optical disk has been described. However, the present invention is not limited to this, and can be widely applied to a read-only recording medium. it can.

[0113]

As described above, according to the present invention, the identification data ID arranged at the head of the main data portion is detected with reference to the fixed value data assigned to the end of the preamble, thereby making it possible to detect a flaw or the like. Therefore, even if the synchronization pattern cannot be detected correctly, the identification data ID can be correctly detected and the main data can be reliably demodulated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a demodulation unit of an optical disc device according to a first embodiment of the present invention together with peripheral components.

FIG. 2 is a block diagram illustrating an optical disc device to which the demodulation unit in FIG. 1 is applied.

FIG. 3 is a block diagram for explaining data processing in the optical disk device of FIG. 2;

FIG. 4 is a table provided for describing an operation of a modulation unit in the optical disc device of FIG. 2;

FIG. 5 is a table showing a configuration of a leading sync frame in the optical disc device of FIG. 2;

FIG. 6 is a table showing a configuration of a cluster in the optical disk device of FIG. 2;

FIG. 7 is a chart showing a synchronization pattern.

FIG. 8 is a schematic diagram for explaining a continuous synchronization pattern;

FIG. 9 is a schematic diagram for explaining a continuous synchronization pattern with one synchronization pattern interposed therebetween;

FIG. 10 is a block diagram showing a scramble circuit.

FIG. 11 is a chart provided for describing an operation of a demodulation unit of the optical disc device in FIG. 2;

FIG. 12 is a flowchart showing a processing procedure of a frame discrimination circuit of the optical disc device of FIG. 2;

FIG. 13 is a block diagram showing a demodulation unit of an optical disc device according to a second embodiment together with peripheral components.

FIG. 14 is a signal waveform diagram for explaining the operation of the demodulation unit in FIG. 13;

FIG. 15 is a flowchart illustrating a processing procedure of a frame discriminating circuit in the demodulation unit in FIG. 13;

FIG. 16 is a chart showing a configuration of a cluster in a conventional optical disc device.

FIG. 17 is a table showing a configuration of a sector shown in FIG. 16;

[Explanation of symbols]

1 ... optical disk device, 2 ... optical disk, 8, 21 ...
... Memory, 6 ... ID, EDC encoding unit, 10 ...
Modulation section, 19, 49 ... demodulation section, 20 ... ID decoding section, 20C ... memory control circuit, 30 ... binarization circuit,
31, PLL circuit, 32, 51, counter, 34
... demodulation circuit, 35 ... synchronous pattern detection circuit, 37, 5
0: pattern determination circuit, 38, 53 ... frame determination circuit

Claims (23)

[Claims] 1. A frame is formed by a predetermined amount of data, a plurality of said frames form a small block, and a plurality of said small blocks form a block.
A preamble is arranged at the head of the block, and in a recording medium on which the data is recorded in units of the block and the preamble, an identification pattern for identifying each frame is arranged at the head of each frame, and at least the small block The first frame is assigned the specific identification pattern different from the identification pattern arranged in another frame, and the first frame of the small block is assigned identification data for identifying each of the small blocks. A recording medium, wherein fixed-value data is assigned to the end of the preamble. 2. An identification pattern having a smaller number of types than the number of frames forming the small block is sequentially assigned to each of the frames. In each of the small blocks, when a continuous frame is arbitrarily selected, The identification pattern is assigned such that a combination of the identification patterns assigned to the consecutive frames is different from a combination of the identification patterns assigned to any other consecutive frames. The recording medium according to the above. 3. In each of the small blocks, when three consecutive frames are arbitrarily selected, the combination of the identification patterns assigned to the first frame and the last frame of the three consecutive frames is as follows:
3. The recording according to claim 2, wherein the identification pattern is assigned so as to be different from the combination of the identification patterns assigned to the first frame and the last frame of any other three consecutive frames. Medium. 4. A frame is formed by a predetermined amount of data, and a small block is formed by a plurality of said frames.
In a data transmission device that forms a block by the plurality of small blocks, arranges a preamble in the block, and transmits the data in units of the block and the preamble, each frame is identified at the head of the frame. An identification pattern is arranged, and at least the first frame of the small block is assigned the specific identification pattern different from the identification pattern arranged in another frame, and the small block is identified as the first frame of the small block. A data transmission device, wherein fixed data is allocated at least at the end of the preamble. 5. A method according to claim 1, wherein the identification patterns of a smaller number than the number of frames forming the small block are sequentially assigned to the respective frames, and when a continuous frame is arbitrarily selected in each of the small blocks, The identification pattern is assigned such that a combination of the identification patterns assigned to consecutive frames is different from a combination of the identification patterns assigned to any other consecutive frames. Data transmission device. 6. In each of the small blocks, when three consecutive frames are arbitrarily selected, the combination of the identification patterns assigned to the first frame and the last frame of the three consecutive frames is:
6. The data transmission according to claim 5, wherein the identification pattern is assigned so as to be different from a combination of the identification patterns assigned to a head frame and a tail frame of any other three consecutive frames. apparatus. 7. A scramble process for data of a predetermined value,
The data transmitting apparatus according to claim 4, wherein data to be arranged in the preamble including the fixed value data is generated. 8. A scramble process for data of a predetermined value,
The data transmitting apparatus according to claim 4, wherein data to be arranged in the preamble excluding the fixed value data is generated. 9. A data receiving apparatus for receiving desired data transmitted in a predetermined block unit, wherein said block is formed by a plurality of small blocks with a preamble arranged at a head thereof, wherein each of said small blocks is a predetermined one. The data amount is formed by a plurality of frames based on the data, wherein each frame is arranged with an identification pattern of each frame, and a leading frame of the small block is arranged with identification data of each small block. Detecting fixed value data arranged at the end of the preamble, based on the detection result of the fixed value data,
A data receiving apparatus comprising: detecting the identification data of the small block following the preamble; and decoding data of the block based on a detection result of the identification data. 10. The data receiving apparatus according to claim 9, wherein the fixed value data is detected while permitting erroneous detection of a predetermined number of bits. 11. When the identification data is detected based on the identification pattern, and when the identification data cannot be detected based on the identification pattern, based on the detection result of the fixed value data, The data receiving device according to claim 9, wherein the identification data is detected. 12. A predetermined identification window is set for sequentially input data based on the detection result of the identification pattern, and the input data is determined by the identification window to determine a subsequent identification pattern. Detecting, setting a window for the fixed value data based on the detection result of the identification pattern, determining the input data by the window for the fixed value data, and detecting the fixed value data The data receiving device according to claim 9, wherein: 13. The fixed value data window for the fixed value data is set to be narrower in width than the fixed pattern data window width for the identification pattern. A data receiving device according to claim 1. 14. A frame is formed by data of a predetermined data amount, a small block is formed by a plurality of said frames, a block is formed by a plurality of said small blocks, and a preamble is arranged in said block. In an optical disc apparatus that records the data on an optical disc in units of, an identification pattern for identifying each frame is arranged at the beginning of each frame, and at least the first frame of the small block is arranged in another frame. Assigning the identification pattern different from the identification pattern that is different from the identification pattern, assigning identification data for identifying each of the small blocks to the first frame of the small block, and assigning fixed value data at least to the end of the preamble. An optical disc device characterized by the above-mentioned. 15. An identification pattern having a smaller number of types than the number of frames forming the small block is sequentially assigned to each of the frames, and when a continuous frame is arbitrarily selected in each of the small blocks, The identification pattern is assigned so that a combination of the identification patterns assigned to consecutive frames is different from a combination of the identification patterns assigned to any other consecutive frames. Optical disk device. 16. In each of the small blocks, when three consecutive frames are arbitrarily selected, the combination of the identification patterns assigned to the first frame and the last frame of the three consecutive frames is as follows:
16. The optical disc apparatus according to claim 15, wherein the identification pattern is assigned so as to be different from a combination of the identification patterns assigned to a head frame and a tail frame of any three other consecutive frames. . 17. The optical disk device according to claim 14, wherein data of a predetermined value is scrambled to generate data to be arranged in the preamble including the fixed value data. 18. The optical disc apparatus according to claim 14, wherein data of a predetermined value is scrambled to generate data to be arranged in the preamble excluding the fixed value data. 19. An optical disc apparatus for reproducing data recorded on an optical disc in a predetermined block unit, wherein said block is formed by a plurality of small blocks with a preamble arranged at the beginning, and each of said small blocks is a predetermined data The amount of the data is formed by a plurality of frames, each of the frames is arranged with an identification pattern of each frame, and a leading frame of the small block is arranged with identification data of each small block. Detect fixed value data arranged at the end of the preamble, based on the detection result of the fixed value data,
An optical disc apparatus, comprising: detecting the identification data of the small block following the preamble; and decoding the data of the block based on a detection result of the identification data. 20. The data processing apparatus according to claim 19, wherein said fixed value data is detected while permitting erroneous detection of a predetermined number of bits.
An optical disk device according to claim 1. 21. Detecting the identification data based on the identification pattern, and when the identification data cannot be detected based on the identification pattern, based on a detection result of the fixed value data, 20. The optical disk device according to claim 19, wherein the identification data is detected. 22. A predetermined identification window is set for reproduction data to be sequentially reproduced with reference to the detection result of the identification pattern, and the reproduction data is determined by the identification window to determine a subsequent identification pattern. Detecting, setting a window for the fixed-value data based on the detection result of the identification pattern, determining the reproduction data by the window for the fixed-value data, and detecting the fixed-value data. 20. The optical disk device according to claim 19, wherein: 23. The fixed value data window width for the fixed value data is set narrower than the width of the identification pattern window for the identification pattern. An optical disk device according to claim 1.