JP2001266509A - Error correction and descramble circuit, reproducing device provided with error correction and de-scramble circuit, and method for performing error correction and de-scramble processing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an error correction and de-scramble circuit which can perform high-speed data transfer with fewer power consumption, a reproducing device provided with such a circuit, a error correction and de-scramble method. SOLUTION: ECC layout block data reproduced from a recording medium are demodulated, and are once stored by an SDRAM 12. Error correction processing by a product code is performed only the number of times determined in a different direction on the stored ECC layout block data by an ECC circuit 13a, respectively. User data among the data which the error correction processing in an SDRAM 12 has been completed are read for the transfer to a host side by a DMA 11 and de-scramble processing is applied by an SCR circuit 13b before transferring to the read data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction / descrambling circuit, a reproducing apparatus provided with the error correction / descrambling circuit, and a method for performing error correction / descrambling processing. An error correction / descrambling circuit for reducing the number of accesses for error correction and descrambling processing to a memory storing reproduction data in block units, a reproduction apparatus including the error correction / descrambling circuit, and an error correction / decoding circuit The present invention relates to a method for performing a scrambling process.

[0002]

2. Description of the Related Art Conventionally, in a recording / reproducing apparatus for a magneto-optical disc as an example of a recording medium, a write system modulates scrambled user data by adding redundant data such as an error correction code to the magneto-optical disc. It is magneto-optically recorded thereon.

On the other hand, in the read system, scrambled data reproduced and demodulated from a magneto-optical disk is temporarily stored in a memory in units of error correction blocks, and thereafter, in error correction blocks for error correction processing. Is read. The read data in units of error correction blocks are subjected to an error correction process using, for example, a product code, and descrambling of the data is performed when an error residual determination is performed on the data on which the error correction process has been completed.

[0004] In this manner, the error-corrected and descrambled data in units of error-corrected blocks are written back to the memory again, and then the user data is read from the memory for output to the host.

[0005]

As described above, in the conventional recording / reproducing apparatus for a magneto-optical disk, the data in units of error correction blocks for which the error correction processing has been completed is descrambled and written back to the memory again. Since data is read out to the host side, the number of accesses to the memory for error correction and descrambling processing becomes very large, power consumption increases, and sufficient data is transferred to the host side. Therefore, there is a problem that it is impossible to allocate a short time, and high-speed data transfer cannot be performed in response to a request from the host.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an error correction / descrambling circuit which realizes higher-speed data transfer with less power consumption, a reproducing apparatus provided with such an error correction / descrambling circuit, and an error correcting apparatus. An object of the present invention is to provide a method for performing a correction / descrambling process.

[0007]

According to the present invention, in a reproducing apparatus for a recording medium on which scrambled data is recorded, an error correction / descrambling circuit for performing error correction and descrambling of reproduced data is provided with a random number. It has an accessible memory, a data writing unit, an error correction unit, a data reading unit, and a descrambling unit. The data writing means sequentially writes the scrambled data reproduced and demodulated from the recording medium into the memory in units of error correction blocks. The error correction means sequentially performs error correction processing on the data in units of error correction blocks stored in the memory. The data reading means reads out the scrambled data from the data of the error correction block stored in the memory and subjected to the error correction processing, and outputs the data to the host. The descrambling means performs a descrambling process on the scrambled data read by the data reading means for outputting to the host.

Preferably, the error correction means includes a product code correction means for reading data in units of error correction blocks stored in the memory, performing an error correction process using a product code, and writing the corrected data back to the memory. .

[0009] More preferably, the error correction / descrambling circuit further includes an error residual determination unit connected to the product code correction unit and configured to determine an error remaining of the data subjected to the error correction processing.

[0010] More preferably, the product code correction means sequentially performs error correction processing on the data in units of error correction blocks a predetermined number of times in the horizontal and vertical directions.

According to another aspect of the present invention, a reproducing apparatus for a recording medium on which scrambled data is recorded includes: means for reproducing and demodulating the scrambled data from the recording medium; An error correction / descrambling circuit for performing error correction and descrambling of the obtained data and outputting it to the host side. The error correction / descrambling circuit includes a randomly accessible memory, a data writing unit, an error correction unit, a data reading unit, and a descrambling unit.
The data writing means sequentially writes the reproduced and demodulated scrambled data into the memory in units of error correction blocks. The error correction means sequentially performs error correction processing on the data in units of error correction blocks stored in the memory. The data reading means reads out the scrambled data from the data of the error correction block stored in the memory and subjected to the error correction processing, and outputs the data to the host. The descrambling means performs a descrambling process on the scrambled data read by the data reading means for outputting to the host.

Preferably, the error correction means includes a product code correction means for reading data in units of error correction blocks stored in the memory, performing an error correction process using a product code, and writing the corrected data back to the memory. .

[0013] More preferably, the error correction / descrambling circuit further includes an error residual judging means connected to the product code correcting means and for judging an error remaining of the error-corrected data.

[0014] More preferably, the product code correction means sequentially performs error correction processing on the data in units of error correction blocks a predetermined number of times in the horizontal and vertical directions.

According to still another aspect of the present invention, in a reproducing apparatus for a recording medium on which scrambled data is recorded, a method for performing error correction and descrambling of reproduced data is performed by reproducing and demodulating from a recording medium. Sequentially writing the scrambled data into a memory that can be randomly accessed in units of error correction blocks, sequentially applying error correction processing to the data in units of error correction blocks stored in the memory, and Reading the scrambled data from the error-corrected block unit data subjected to the error correction processing and outputting the data to the host; and descrambling the scrambled data read for output to the host. Applying.

Preferably, the step of performing the error correction processing includes a step of reading data in units of error correction blocks stored in the memory, performing an error correction processing using a product code, and writing back the corrected data to the memory. Including.

More preferably, the method of performing error correction and descrambling further includes a step of determining whether an error remains in the data that has been subjected to the error correction by the product code.

More preferably, the step of performing an error correction process using a product code includes a step of sequentially performing a predetermined number of error correction processes in the horizontal and vertical directions on the data in units of error correction blocks.

As described above, according to the present invention, the scrambled user data read from the memory for output to the host is descrambled. It is possible to reduce the number of accesses to a memory storing data for error correction processing. As a result, power consumption can be reduced, the time allocated for data transfer to the host can be increased, and high-speed data transfer can be realized.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same or corresponding portions have the same reference characters allotted, and description thereof will not be repeated.

First, a format of information recorded and reproduced on a magneto-optical disk as a recording medium to which the present invention is applied will be described.

Referring to FIG. 1, a plurality of tracks (t ₁ , t ₂ , t ₃ , t ₄ ,..., T _n-1 ) are concentrically (or spirally) formed on a recording surface of a magneto-optical disk _1. , T _n ) (FIG. 1 shows only a part of the track formed on the entire surface of the disk in a sector shape), and the plurality of concentric tracks further extend from the outer circumference to the inner circumference. in the radial direction to form a band for each track of several adjacent (e.g. tracks t ₁ ~t ₄ in forming one band Figure 1), a buffer area (not shown) between the adjacent bands and band formation Is done.

Each track on the magneto-optical disk is divided at equal intervals, and a plurality of frames 2 as information recording units are arranged.

As shown in FIG. 1, each frame 2 has 39 segments (S0, S1, S2, S3,..., S).
n,..., S38). The first segment S0 of the 39 segments is an address segment, and the remaining 38 segments S1 to S38 are data segments.

In each of the address segment and the data segment, a fine clock mark (FC) serving as a phase reference for generating a clock signal serving as a reference for a recording / reproducing operation is provided at a head position in each segment.
M) is formed.

Referring to FIG. 1, the physical shapes of the address segment S0 and the data segment Sn are schematically shown. Each track is composed of a pair of lands and grooves. Grooves indicated by diagonal lines are
The grooves are formed on the recording surface, and the lands are other portions.

First, as described above, in both the address segment and the data segment, the FCM is preformatted at the head position of each segment by reversing the concavo-convex relationship between the groove and the land. The area where the FCM is formed in this way is
It is called a field.

In the address segment S0, FC
In the address field subsequent to the M field, the boundary line between the groove and the land is wobbled by the signal obtained by modulating the address information on the frame during the manufacture of the magneto-optical disk, so that the address information is preformatted.

On the other hand, in the data segment Sn,
Subsequent to the FCM field, a data field for magneto-optical recording of data is provided. The data can be magneto-optically recorded on either or both of the grooves and lands constituting the track.

Next, with reference to FIG. 2, the format of a frame as a recording unit of the above information will be described in more detail.

As described above, each frame is composed of a total of 39 segments, for example, segment 0 to segment 38 (FIG. 2A). Each segment is, for example, 532 bits long, so that F
The CM is repeated at a cycle of 532 bits.

As shown in FIG. 2B, the leading segment 0 of the 39 segments is an address segment. This address segment is composed of a 12-bit FCM field in which the FCM is pre-formatted, and a 520-bit address field in which the address data is pre-formatted.

As shown in FIG. 2C, the second segment 1 of the 39 segments corresponds to the first data segment. The first data segment 1 is 1
A 2-bit length FCM field, a pre-write field in which a 4-bit fixed pattern “0011” indicating data writing is recorded, and 320 bits (40 bits) used for confirming a recording start position in frame units during reproduction.
Byte) fixed length header field,
It is composed of a 192 bit (24 byte) data field for storing data, and a post-write field in which a 4-bit fixed pattern "1100" indicating the end of the data field is recorded.

As shown in FIG. 2D, the remaining segments 2 to 38 are all data segments of the same format. Each of these data segments is composed of a 12-bit long FCM field, a 4-bit long pre-write field, a 512-bit (64-byte) long data field, and a 4-bit long post-write field.

As apparent from FIGS. 2C and 2D, the first data segment 1 of the data segments
Only include header fields.

Next, the format of an ECC (Error Correction Code) layout block as a data unit for error correction will be described with reference to FIG.

First, in one frame composed of the 39 segments shown in FIG. 2A, as shown in FIG. 3A, the remaining 39 data segments S1 to S38 excluding the address segment S0 are used. From the header and data fields, as shown in FIG. 3B, a 40-byte header field and 24 bytes + 64 bytes × 37 = 2
A data block composed of a data field (main data field) having a length of 392 bytes is formed.

Then, as shown in FIG.
The data blocks shown in (b) are collected for 16 frames to constitute a block called an ECC block in the magneto-optical recording standard.

The error correction processing (hereinafter, ECC processing) does not actually cover the entire ECC block shown in FIG.

First, as shown in FIG. 3D, a block is composed of 16 frames of main data (2392 bytes each) excluding the header (2392 bytes × 16 = 38).
272 bytes), and as shown in FIG. 3 (e), the remaining 37856-byte length data obtained by removing the 416-byte DSV (Digital Sum Variation) from the actual
It becomes an error correction block for CC processing. Hereinafter, this block is referred to as an ECC layout block.

Further, as shown in FIG.
The data of the CC layout block includes the original user data (2048 bytes x 16 frames = 32768 bytes), ECC, EDC (Error Detection Code),
D and other redundant data (5088 bytes). The ECC processing of the ECC layout block data of FIG. 3F will be described later in detail.

FIG. 4 is a functional block diagram showing the configuration of a magneto-optical disk recording / reproducing apparatus to which the present invention is applied.

Referring to FIG. 4, the recording operation of the recording / reproducing apparatus will be described first. First, data to be recorded is input to the error correction code adding circuit 113, scrambled, and redundant data such as an error correction code (ECC data) is added. The data to which the error correction code has been added is digitally modulated by the data modulator 114 and supplied to the magnetic head drive circuit 115. The magnetic head driving circuit 115 controls the magnetic head 1 based on the input data.
The magnetic head 116 applies a magnetic field modulated based on the data to the magneto-optical disk 101.

The laser driving circuit 117 drives a semiconductor laser (not shown) in the pickup 102 so as to generate a laser beam having a predetermined intensity.
Irradiates the magneto-optical disk 101 with laser light of a predetermined intensity. As a result, magnetic domains having magnetizations in different directions are formed on the magneto-optical disk 101 based on the data, and the data is magnetically modulated and recorded.

Next, the reproducing operation of the recording / reproducing apparatus will be described with reference to FIG. First, data is reproduced by the pickup 102 from the magneto-optical disk 101 rotated and driven by the motor 116, and the signal operation circuit 10
0 is given. The signal calculation circuit 100 calculates each sensor output signal of the pickup to record the reproduced data signal RF, the tangential push-pull signal TPP for detecting the FCM of each segment, and the wobbling in the address field of the address segment. And a radial push-pull signal RPP for reproducing the reproduced address data.

A reproducible frequency is extracted from the reproduced data signal RF via a band-pass filter (BPF) 103, and is converted into a digital signal by an AD converter 104. The output of the AD converter 104 is waveform-equalized by a waveform equalization circuit 105 and supplied to a well-known Viterbi decoder 106.

The output decoded by the Viterbi decoder 106 is
The digital modulation applied to the data demodulator 108 and applied at the time of recording is digitally demodulated.
9 given. The error correction circuit 109 performs error correction using redundant data such as an error correction code (ECC data) added at the time of recording. The details of the error correction will be described later in detail.

The output of the Viterbi decoder 106 is also given to a header detection circuit 107, which outputs
The position of the header field recorded in the aforementioned segment 1 is detected, and a header detection signal is generated and provided to the data demodulator 108.

On the other hand, the TPP signal output from signal operation circuit 100 is applied to PLL circuit 110, and PLL circuit 110 generates data clock CLK based on the TPP signal which is a signal obtained by reproducing the FCM of each segment. I do. Data clock CL generated by PLL circuit 110
K is the aforementioned AD converter 104, waveform equalization circuit 105,
The signal is supplied to the Viterbi decoder 106, the header detection circuit 107, and the data demodulator 108, and is also supplied to the address detection circuit 111 and the data modulator 114.
Further, a signal corresponding to FCM is supplied from the PLL circuit 110 to the address detection circuit 111 based on the TPP signal.

Further, the RPP signal extracted from signal operation circuit 100 is applied to address detection circuit 111. The address detection circuit 111 detects a synchronization signal included in the address data reproduced from the address segment, accurately extracts the address information of the frame, and supplies the extracted address information to the controller 112.

The controller 112 controls the data demodulator 10
8 and the error correction circuit 109, the error correction code addition circuit 113, and the data modulator 114.

Next, FIG. 5 is a block diagram schematically showing a circuit configuration in the case where the portion 10 relating to error correction and modulation / demodulation, which is surrounded by a broken line in the recording / reproducing apparatus shown in FIG. FIG.

First, referring to FIG.
The operation of the recording / reproducing apparatus at the time of writing will be briefly described. At the time of writing, user data to be recorded is provided to the DMA 11 from the host via a host interface (I / F). The given data is DM
The data is sequentially written to the SDRAM 12 by A11.

The data stored in the SDRAM 12 is E
The data is read out to the CC / EDC / SCR / encoder / decoder 13 and scrambled by a known method to user data, and redundant data including codes (ECC data and EDC data) for error correction and error detection is added. And written back to the SDRAM 12.

The data written back to the SDRAM 12 is
The data is digitally modulated by the modulator / demodulator / formatter / deformatter 14, adjusted to a predetermined data format suitable for recording, and applied to the magnetic head drive circuit 115 of FIG. 4 as write data.

Next, referring to FIG.
The operation of the recording / reproducing apparatus at the time of reading will be briefly described. At the time of reading, the data reproduced from the magneto-optical disk 101 is subjected to the waveform equalization and the Viterbi decoding circuit 15.
To perform waveform equalization and Viterbi decoding. The waveform-equalized and Viterbi-decoded data is modulated by a modulator / demodulator / formatter / deformatter 14.
The data is digitally demodulated, deformed into the data of the ECC layout block described above, and written into the SDRAM 12.

The data stored in the SDRAM 12 is E
The data is read out by the CC / EDC / SCR / encoder / decoder 13 and subjected to various processes such as error correction, error detection, and descrambling. The data subjected to these processes is SDR
It is written back to AM12.

The user data among the data written back to the SDRAM 12 is read via the DMA 11 and sent to the host via the host I / F.

The DMA 11, SDRAM 12, EC
C / EDC / SCR / encoder / decoder 13, modulator / demodulator / formatter / deformatter 14, waveform equalization and Viterbi decoding circuit 15, controller 1
12 (FIG. 4) exchange control signals with each other via the MPU bus.

FIG. 6 shows a conventional error correction (ECC), error detection (EDC), and descrambling of read-system data reproduced from a magneto-optical disk in the circuit configuration of the LSI shown in FIG. FIG. 3 is a diagram extracting and showing a circuit configuration for performing (SCR) processing.

Referring to FIG. 6, a description will now be given of a conventional ECC, EDC, and SCR process for read data. The read system data output from the waveform equalization and Viterbi decoding circuit 15 in FIG. 5 is supplied to a modulator / demodulator / formatter / deformatter 14, and the modulator / demodulator / formatter / deformatter 14 converts the data into digital data. Demodulated, and then de-formatted into the 37856-byte ECC layout block shown in FIG.
Write to AM12.

FIG. 7 is a diagram schematically showing one ECC layout block stored in a two-dimensional memory area of the SDRAM 12. Referring to FIG. 7, the data of the ECC layout block has a length of 182 bytes consisting of 172 bytes of data and 10 bytes of PI parity in the horizontal direction, and 192 lines of data and 16 bytes in the vertical direction.
It has 208 lines consisting of the PO parity of the line.

In the ECC layout block shown in FIG. 7, PI parity and PO parity, which are ECC data, are calculated and added to user data by a well-known product encoding method using a Reed-Solomon code.

FIG. 8 shows a one-dimensional display of data corresponding to one frame of a data portion excluding ECC data (PI parity and PO parity) in the ECC layout block of FIG. Referring to FIG.
Data equivalent to a frame includes a 6-byte data ID field, a 6-byte reserved field RSV,
048 bytes of scrambled user data;
And EDC data of bytes. FIG. 8 shows the data structure in a one-dimensional manner for convenience. As shown in FIG. 7, in a two-dimensional memory area, data corresponding to one frame (excluding ECC data) is 172 bytes × It has a two-dimensional array of 12 lines, with ID and RSV fields at the beginning, and an EDC field at the end.

FIG. 9 is a table showing the contents of data (excluding ECC data) corresponding to one frame shown in FIG. Referring to FIG. 9, data ID of first 6 bytes
Are allocated at byte positions 0 to 5 in the memory area, the 6-byte reserved field RSV (all "0") is allocated at byte positions 6 to 11, and the 2048-byte user data is stored at byte positions 12 to 2059. The 4-byte EDC data is allocated to the last byte positions 2060 to 2063. The 4-byte EDC data is operated on the entire data of 2064 bytes corresponding to one frame. On the other hand, bit scrambling is performed only on the 2048-byte user data.

Next, ECC processing for data of one ECC layout block stored in the SDRAM 12 will be described.

First, 208 lines of horizontal (PI direction) data (182 bytes each) are sequentially read from the SDRAM 12 line by line to the ECC circuit 13a, and error correction is performed for each line. The ECC circuit 13a can correct up to 5 bytes out of 182 bytes in the PI direction, for example, and writes only the corrected data back to the SDRAM 12. This ECC processing is called PI1.

Next, 182 lines of vertical direction (PO direction) data (each 208 bytes) are sequentially read line by line from the SDRAM 12 to the ECC circuit 13a, and error correction processing is performed for each line. The ECC circuit 13a can correct up to 15 bytes out of, for example, 208 bytes in the PO direction, and writes only the corrected data back to the SDRAM 12. This ECC processing is called PO1.

Next, 192 lines of horizontal (PI direction) data (182 bytes each) are sequentially read from the SDRAM 12 to the ECC circuit 13a line by line, and error correction is performed for each line. This ECC processing is called PI2.

In the conventional circuit configuration shown in FIG.
All scrambled user data (2048 bytes) subjected to ECC processing in the PI2 processing of the circuit 13a is subjected to descrambling processing for descrambling by the descrambling circuit 13b. The descrambled user data is written back to the SDRAM 12, and the EDC circuit 13c detects the presence or absence of an error.

The user data among the data of the ECC layout block in the SDRAM 12 which has been subjected to the ECC processing is read out by the DMA 11 and transmitted to the host side (host computer) via the host I / F.

FIG. 11A is a diagram showing the pipeline processing by the conventional circuit configuration shown in FIG. FIG.
Referring to (a), an ECC layout block (hereinafter, simply referred to as a block) n demodulated by a demodulator / deformatter 14 is subjected to ECC, ED by an ECC circuit 13a, an EDC circuit 13c, and an SCR circuit 13b in the next stage.
Each process of C and SCR (descrambling) is performed, and during that period, the next block n + 1 is demodulated in parallel.

In the next stage, block n is DMA11
, During which the subsequent block n + 1
Undergoes ECC, EDC, and SCR processing, and simultaneously demodulates the next block n + 2. Hereinafter, similarly, the processing of demodulation → ECC / EDC / SCR → OUT is continued in a pipeline manner.

Next, in the conventional circuit configuration of FIG.
Consider the number of times the SDRAM 12 is accessed for CC, EDC, and SCR processing.

First, in FIG. 6, writing from the demodulator / deformatter 14 indicated by WM1 to the SDRAM 12 is 182 bytes × 208 lines = 37856.
An ECC layout block of byte = 18928 words is written to SDRAM 12.

Next, as for reading from the SDRAM 12 for PI1 processing indicated by RPI1, the entire ECC layout block of 182 bytes × 208 lines = 18928 words is read to the ECC circuit 13a.

Next, regarding writing to the SDRAM 12 after the PI1 processing indicated by WPI1, it is assumed that there is an error of 5 bytes which is the maximum number correctable for each line, and 5 bytes × 208 lines = The 1040-byte corrected data is written back to the SDRAM 12.

Next, as for reading from the SDRAM 12 for the PO1 processing indicated by PRO1, the entire ECC layout block of 208 bytes × 182 lines = 18928 words is read to the ECC circuit 13a.

Next, regarding writing to the SDRAM 12 after the PO1 processing indicated by the WPOI, it is assumed that there is a 15-byte error that is the maximum number that can be corrected for each line, that is, 15 bytes × 182 lines = Correction data of 2730 bytes is written back to SDRAM 12.

Next, for reading from the SDRAM 12 for PI2 processing indicated by PRI2, an ECC layout block of 182 bytes × 192 lines = 34944 bytes = 17472 words (182 bytes since parity does not need to be corrected and returned) (Excluding parity of × 16 lines) is read out to the ECC circuit 13a.

Of the data of the ECC layout block subjected to the PI2 processing, 2064 for each frame
Only the data of the byte excluding the ECC data (PI parity, PO parity) is given to the SCR circuit 13b,
SDR as descrambled and indicated by WPI2
It is written back to AM12. That is, in the process indicated by WPI2, 2064 bytes × 16 frames = 3302
4 bytes = 16512 words of data in SDRAM 12
Will be written back.

Next, for reading data from the SDRAM 12 indicated by RD1 to the host side, only user data needs to be sent to the host side.
16 frames = 32768 bytes = 16384 words are read from the SDRAM 12 to the DMA 11.

Here, at the time of correction, since writing is performed at addresses discrete in bytes, the number of accesses (number of writes) of the SDRAM 12 is equal to the number of bytes.

Therefore, the total number of write accesses to SDRAM 12 is 18928 (WM1) +1040
(WPI1) +2730 (WPO1) + 16512 (W
PI2) = 39210 times.

The number of accesses to read data from SDRAM 12 is 18928 (RPI1) +18928 in total.
(RPO1) + 17472 (RPI2) + 16384
(RD1) = 71712 times.

Therefore, the total number of write and read accesses to SDRAM 12 is 110922.
The number of accesses to the SDRAM 12 becomes very large, which requires time for the access operation and also increases power consumption.

FIG. 10 is a diagram showing an example in which E
FIG. 1 is a block diagram showing a circuit configuration according to an embodiment of the present invention for performing CC, EDC, and SCR (descrambling) processing.

The circuit configuration shown in FIG. 10 differs from the conventional circuit configuration shown in FIG. 6 in the following points. That is, EC
The data corrected by the PI2 processing by the C circuit 13a is written back to the SDRAM 12.

The data subjected to PI2 processing is ED
It is provided to the C circuit 13c, and finally detects whether an error remains in the data. The descramble of the scrambled user data is executed by the SCR circuit 13b on the user data read from the SDRAM 12 by the DMA 11 for transfer to the host.

FIG. 11B is a diagram showing pipeline processing by the circuit configuration according to the embodiment shown in FIG. Referring to FIG. 11B, the ECC layout block (hereinafter, block) n demodulated by the demodulator / deformatter 14 is used in the next stage by the ECC circuits 13a and ED.
ECC and EDC processes are performed by the C circuit 13c, and during that period, the next block n + 1 is demodulated and SDR
It is written to AM12.

In the next stage, block n is DMA11
, Descrambled by the SCR circuit 13b, and output to the host. During this period, the following block n + 1 is subjected to ECC and EDC processing, and at the same time, the next block n + 2 is demodulated and
Written in 12. Hereinafter, similarly, demodulation → ECC /
The processing of EDC → SCR / OUT is continued in a pipeline manner.

The data read to the DMA 11 is
It is 2060 bytes (1030 words) consisting of ID, RSV, and user data.
The descrambling process is performed by the CR circuit 13b.
At this time, in order to change the descrambling pattern according to the ID information, reading is performed from the ID data.

For such a circuit of FIG. 10, SDR
Consider the number of accesses to AM12.

WM1, RPI1, WPI1, R in FIG.
Regarding the processes of PO1, WPO1, RPI2 and RD1, the number of times of writing to the SDRAM 12 is the same as that of the conventional example of FIG. 6, but the number of times of reading is different. That is, W
M1 = 18928 words, RPI1 = 18928 words, WPI1 = 1040 bytes, RPO1 = 18928
Word, WPO1 = 2730 bytes, RPI2 = 174
Same as the conventional example with 72 words, but RD1 is 2060 bytes × 16 frames.
1 = 16480 words.

In the embodiment of FIG. 10, unlike the conventional example of FIG. 6, only the correction data after the PI2 processing is written into the SDRAM 12, as indicated by WPI2, and the maximum number of correctable data for each line is obtained. Assuming that there is an error of 5 bytes, the correction data of 5 bytes × 192 lines = 960 bytes is written back to the SDRAM 12.

Therefore, the number of times of writing access to the SDRAM is 18928 (WM1) +1040 (W
PI1) + 2730 (WPO1) + 960 (WPI2)
= 23658 times.

The total number of times of reading access to SDRAM 12 is 18928 (RPI1) +18928
(RPO1) + 17472 (RPI2) + 16480
(RD1) = 71808 times.

Therefore, the total number of write / read accesses to SDRAM 12 is 95466 times, which is about 14 times as compared with 110922 times in the conventional circuit of FIG.
% Decrease. Therefore, according to the embodiment of the present invention, the number of accesses to SDRAM 12 can be reduced, the power consumption can be reduced, and the time required for data transfer to the host can be increased. Thus, it is possible to respond to a request for high-speed data transfer with high burst characteristics from the host side.

FIG. 12 is a diagram showing the mapping of the ECC layout block data to the decoding area of the SDRAM 12 at the time of reading over time.

That is, one area constituting the decoding area of the SDRAM is a memory area corresponding to one ECC layout block data. In FIG. 12, the upper area corresponds to the past data, and the lower area corresponds to the lower area. It corresponds to future data as soon as possible.

In FIG. 12, when the latest ECC layout block data read from the disc and demodulated is stored in the third area from the top, it is stored in the second area from the top one block before. The ECC layout block data is subjected to ECC / EDC processing by the circuit configuration of FIG. Further, the user data of the ECC layout block data, which has already been subjected to the ECC / EDC processing and is stored in the uppermost area one block before, is read out via the DMA 11 and subjected to the scramble processing, and thereafter the host Transferred to the side.

Note that the reading of the data after the ECC / EDC processing from the SDRAM is not always performed immediately after the end of the ECC / EDC processing. For example, EC
It is also possible to accumulate data in the SDRAM after the C / EDC processing has been completed, read it all at once when requested by the host, and transfer it to the host.

As described above, according to the embodiment of the present invention, the ECC and EDC processes have been completed, and the descrambling process is performed on the user data read for transfer to the host. SDRA
The number of accesses to M is reduced, power consumption is reduced, and high-speed data transfer is enabled.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0105]

As described above, according to the present invention, since the user data subjected to the error correction processing is descrambled when read from the memory in order to output the data to the host, The number of accesses to the memory can be reduced, power consumption can be reduced, and high-speed data transfer to the host can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing a relationship between a signal recording mode and a signal format on a magneto-optical disk.

FIG. 2 is a schematic diagram showing in detail a format of one frame of recording data.

FIG. 3 is a schematic diagram showing a process of forming data of an ECC layout block.

FIG. 4 is a schematic block diagram of a magneto-optical recording / reproducing apparatus according to an embodiment of the present invention.

5 is a schematic block diagram in a case where a part related to error correction and modulation / demodulation in the recording / reproducing apparatus shown in FIG. 4 is realized by an LSI.

6 is a block diagram showing a conventional circuit configuration related to error correction and descrambling processing in the circuit configuration shown in FIG.

FIG. 7 shows one unit of EC stored in the SDRAM of FIG. 6;
FIG. 3 is a diagram illustrating a data configuration of a C layout block.

8 is a schematic diagram showing a data structure of one frame excluding ECC data in the data structure shown in FIG. 7;

FIG. 9 is a schematic diagram listing the contents of the data configuration shown in FIG. 8;

FIG. 10 is a diagram showing a circuit configuration relating to error correction and descrambling according to the embodiment of the present invention.

FIG. 11 is a schematic diagram showing pipeline processing according to a conventional technique and an embodiment of the present invention, respectively.

FIG. 12 is a schematic diagram showing mapping over time to a decoding area of the SDRAM according to the embodiment of the present invention;

[Explanation of symbols]

1 magneto-optical disk, 2 frames, 10 LSI, 1
1 DMA, 12 SDRAM, 13 ECC / EDC
/ SCR / encoder / decoder, 13a ECC circuit, 13b SCR circuit, 13c EDC circuit, 14
Modulator / Demodulator / Formatter / Deformatter, 15
Waveform equalization and Viterbi decoding circuit, 100 signal operation circuit, 101 magneto-optical disk, 102 pickup,
103 BPF, 104 AD converter, 105 waveform equalization circuit, 106 Viterbi decoder, 107 header detection circuit, 108 data demodulator, 109 error correction circuit, 1
10 PLL circuit, 111 address detection circuit, 112
Controller, 113 error correction code adding circuit, 114
Data modulator, 115 Magnetic head drive circuit, 116
Magnetic head, 117 Laser drive circuit.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G11B 20/18 572 G11B 20/18 572F G06F 11/10 330 G06F 11/10 330L H03M 13/29 H03M 13 / 29 F term (reference) 5B001 AA13 AB02 AB03 AC08 AD03 AE02 5J065 AA01 AB01 AC03 AD03 AD10 AD13 AF01 AF03 AH06

Claims (12)

[Claims] 1. An error correction / descrambling circuit for performing error correction and descrambling of reproduced data in a reproducing apparatus for a recording medium on which scrambled data is recorded, the memory comprising: a randomly accessible memory; Data writing means for sequentially writing the scrambled data reproduced and demodulated from the medium to the memory in error correction block units; and sequentially error correcting the error correction block unit data stored in the memory. Error correction means for performing the following; data reading means for reading out the scrambled data from the data of the error correction block stored in the memory and having been subjected to the error correction processing, and outputting the scrambled data to a host side; The scramble read by the data read means for output to the host side It has been provided with a descrambling means for performing descramble processing on the data, error correction and descrambling circuitry. 2. The error correction unit reads out the data of the error correction block unit stored in the memory and performs an error correction process using a product code.
2. The error correction / descrambling circuit according to claim 1, further comprising a product code correction unit for writing the corrected data back to said memory. 3. The error correction / descrambling circuit according to claim 2, further comprising: an error residual determination unit connected to said product code correction unit and configured to determine an error residual of said error-corrected data. . 4. The error correction apparatus according to claim 2, wherein said product code correction means sequentially performs error correction processing on the data in units of error correction blocks a predetermined number of times in a horizontal direction and a vertical direction. Correction and descrambling circuit. 5. A reproducing apparatus for a recording medium on which scrambled data is recorded, comprising: means for reproducing and demodulating the scrambled data from the recording medium; and reproducing and demodulating the scrambled data. An error correction / descrambling circuit that performs error correction and descrambling of the data and outputs the result to the host side.The error correction / descrambling circuit includes a random accessible memory, and the reproduced and demodulated scrambled data. Data writing means for sequentially writing the corrected data to the memory in error correction block units; error correction means for sequentially performing error correction processing on the error correction block unit data stored in the memory; and storing in the memory. Out of the data of the error correction block unit subjected to the error correction process, Data reading means for reading the scrambled data and outputting the data to the host side; and descrambling means for performing descrambling processing on the scrambled data read by the data reading means for output to the host side. Including, playback device. 6. The error correction means reads out the data of the error correction block unit stored in the memory and performs an error correction process using a product code.
6. The reproducing apparatus according to claim 5, further comprising a product code correcting unit for writing the corrected data back to said memory. 7. The reproducing apparatus according to claim 6, further comprising: an error residual determination unit connected to the product code correction unit and configured to determine an error residual of the error-corrected data. 8. The reproduction according to claim 6, wherein said product code correction means sequentially performs error correction processing on the data in units of error correction blocks a predetermined number of times in a horizontal direction and a vertical direction. apparatus. 9. A method for performing error correction and descrambling of reproduced data in a reproducing apparatus for a recording medium on which scrambled data is recorded, wherein the scrambled data reproduced and demodulated from the recording medium is reproduced. Sequentially writing data to a memory that can be randomly accessed in units of error correction blocks, sequentially applying error correction processing to the data in units of error correction blocks stored in the memory, and storing the data in the memory. Reading the scrambled data out of the error-corrected block unit data subjected to the error correction processing, and outputting the scrambled data to the host; and outputting the scrambled data to the host. Performing a descrambling process. 10. The step of performing the error correction processing includes: reading out the data of the error correction block unit stored in the memory and performing an error correction processing by a product code;
The method of claim 9, comprising writing back the corrected data to the memory. 11. The method according to claim 10, further comprising the step of determining whether an error remains in the data that has been subjected to the error correction processing using the product code. 12. The method according to claim 11, wherein the step of performing the error correction process using the product code includes the step of sequentially performing a predetermined number of error correction processes in the horizontal and vertical directions on the data in units of the error correction blocks. Item 12. The method according to Item 10 or 11.