JPH07244935A - Cd-rom decoder - Google Patents

Abstract

PURPOSE:To reduce a load of a control microcomputer controlling the operation of a CD-ROM decoder. CONSTITUTION:A synchronizing signal counter 31 generates a predictive signal rising at the timing when the matter that a synchronizing signal is detected next is predicted based on a timing signal outputted from a synchronizing signal detection circuit 14. A detection error signal showing that the detection error of the synchronizing signal occurs is generated by a synchronism protection circuit 32 from the result of comparison between the predictive signal and the timing signal to be supplied to an error counter 33. The error counter 33 imparts a stop instruction to an interruption instruction generation circuit 26 when the count is advanced continuously by the prescribed number of sectors by the detection error signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CD-ROM system which uses a compact disc or a laser disc as a read-only memory, and transfers CD-ROM data read from the disc in response to an instruction from a host computer. It relates to a ROM decoder.

[0002]

2. Description of the Related Art CD-R which utilizes a compact disk (CD) conventionally used for digital audio as a read-only memory (ROM) for digital data.
In the OM system, C read from the disc
In order to improve the reliability of the D-ROM data, the read error of the CD-ROM data is doubled. These correction processes are configured such that the reproduction unit side that reads digital data from the disc executes the first time, and the CD-ROM decoder connected to the reproduction unit executes the second time. Generally 1
Regarding the correction processing for the second time, it is attempted to be shared with an audio CD player.

FIG. 6 is a block diagram showing the structure of a CD-ROM system. The pickup unit 2 that receives the reflected light of the laser light applied to the compact disc 1 takes out the intensity of the reflected light as a change in voltage value and supplies it to the analog signal processing unit 3. The analog signal processing unit 3 is
From the signal input from the pickup unit 2, the optical disc 1
The digital data written in is read and digital data conforming to a predetermined format is serially output. The digital signal processing unit 4 performs signal processing according to the CD format on the digital data output from the analog signal processing unit 3 to generate CD-ROM data. In the signal processing in the digital signal processing unit 4, compatibility with a CD system for digital audio is maintained, and demodulation of 14-bit digital data into 8 bits and Reed-Solomon code are used. A code error is detected / corrected. The CD-ROM decoder 5 is a CD-ROM input from the digital signal processing unit 4.
The ROM data is again subjected to code error correction processing and transferred to the host computer as error-free CD-ROM data. The buffer RAM 6 is a CD-RO
The CD-ROM data which is connected to the M decoder 5 and taken into the CD-ROM decoder 5 from the digital signal processing circuit 4 is stored for a predetermined period. And the control microcomputer 7
Controls the operation of each of the analog signal processing unit 3, the digital signal processing unit 4, and the CD-ROM decoder 5 according to the operation program so that each unit can execute various processes at the correct timing.

CD output from the digital signal processing unit 4
As shown in FIG. 7, the ROM data is composed of 2352 bytes as one sector, and the synchronization signal (12 bytes),
Header (4 bytes), user data (2336 bytes)
Are assigned respectively. The sync signal indicates the head position of the sector, and is attached to the beginning of each sector as a fixed pattern. The 4-byte header further includes absolute time information (minute / second / frame number: 1 byte each) corresponding to the address on the disc and a mode identification code (1 byte) that determines the format of the data in the sector.
Assigned to. In the case of CD-ROM data, 2340 is obtained by removing 12 bytes of the sync signal from the data of 1 sector.
The bytes are scrambled so that the same pattern as the sync signal is hard to occur, and are descrambled at the stage of being input to the CD-ROM decoder 5 to be restored to the original data.

FIG. 8 is a block diagram showing the structure of the CD-ROM decoder 5. The descramble circuit 11 is
CD-RO input every 2352 bytes (1 sector)
Of the M data, 2340 bytes excluding the 12-byte sync signal are descrambled, and the data returned to a predetermined format is output. The write buffer 12 takes in 2336 bytes of user data out of the data output from the descrambling circuit 11 and writes the user data into the buffer RAM through the first data bus 16. The header register 13 takes in a 4-byte header from the data output from the descramble circuit 11, and transfers the header information from the second data bus 17 to the control microcomputer 7. The sync signal detection circuit 14 detects a 12-bit sync signal added to the beginning of each sector of the input data, and inputs the CD-R.
A timing signal indicating the start of a sector of OM data is applied to the operation control circuit 24 described later. When the sync signal is not detected, the data indicating the detection error is transferred from the second data bus 17 to the control microcomputer 7. The error flag register 15 fetches an error flag indicating that an error remains in the error correction processing in the digital signal processing section 4 provided in the preceding stage of the CD-ROM decoder 5, and controls the second data bus 17 from the control microcomputer. Transfer to 6.

The write address generation circuit 18 generates continuous addresses at a constant cycle, and the write buffer 1
2 designates the write address of the CD-ROM data to be written in the buffer RAM 6. The head address generation circuit 19 writes the address when the head of each sector is written in the buffer RAM 6 into the write address generation circuit 1.
The first data bus 1 is read from the first data bus 1 after holding it until the writing of one sector of CD-ROM data is completed.
Send to 6. Further, the head address is transferred from the second data bus 17 to the control microcomputer 7 so as to generate preset data of the transfer address generation circuit 21 described later. The error correction circuit 20 takes in the head address data sent to the first data bus 16 and writes the CD-RO in the buffer RAM 6 based on the data.
The M data is sequentially read and the error detection code (EDC) and error correction code (E) set in the user data are read.
CC) to detect and correct the code error. Here, the data for which the predetermined correction processing has been completed is written in the buffer RAM 6 again, and then sequentially transferred from the transfer buffer 24 to the host computer.

The transfer address generation circuit 21 loads preset data corresponding to the address of the buffer RAM 6 in which the CD-ROM data to be read is written, and in response to the instruction from the transfer trigger generation circuit 22,
The addresses corresponding to the preset data are generated at the beginning and consecutive addresses are generated at a constant cycle. The address generated here is from the first data bus 16 to the buffer RAM.
6, the read address of the CD-ROM data for which the error correction processing has been completed is designated. The transfer byte counter 23 is a CD-RO to be read from the buffer RAM 6.
After loading data indicating the number of bytes of M data as preset data, the buffer RAM 6 is loaded onto the CD-ROM.
It counts down each time data is read, and gives a stop instruction to the transfer trigger generation circuit 22 when a predetermined number of counts are completed. The transfer buffer 24 takes in the CD-ROM data read according to the address generated by the transfer address generation circuit 21 through the first data bus 16 and transfers it to the host computer. The preset data loaded into the transfer address generation circuit 21 and the transfer byte counter 23 is generated by the control microcomputer 7 based on the head address transferred from the head address generation circuit 19 and the transfer instruction given from the host computer.

The operation control circuit 25 includes a sync signal detection circuit 1
Based on the timing signal output from No. 4, the period until the error correction processing by the error correction circuit 20 is completed is measured, and a timing signal indicating the completion of the operation is generated. The error correction processing by the error correction circuit 20 is performed by the buffer R.
This is performed inside the error correction circuit 20 after the CD-ROM data for one sector is fetched from the AM 6, while the CD-ROM data of the next sector is written in the buffer RAM 6. The interrupt instruction generation circuit 26 receives a timing signal from the operation control circuit 25 or an instruction to stop the transfer byte counter 23, and transmits an interrupt instruction to the control microcomputer 7. The control microcomputer 7, which controls the operation of the analog signal processing unit 3 and the digital signal processing unit 4 by time-division processing, responds to the interrupt instruction from the interrupt instruction generation circuit 26 and temporarily interrupts the processing operation up to that point. The CD-ROM decoder 5 is made to execute the following processing operation.
For example, in response to an interrupt instruction from the interrupt instruction generating circuit 26, after interrupting other processing operations, the transfer trigger generating circuit 22 is activated and data transfer from the buffer RAM 6 to the host computer is started.

In the above CD-ROM system,
The header information for each sector is repeatedly fetched and fetched by the control microcomputer 7, and the sector requested by the host computer side is detected by the address information in the header information.

[0010]

Among various CD-ROM data formats, the CD-ROM XA standard and C
In the case of the mode 2 format used in DI,
The error detection / correction code does not target the header. Therefore, at the stage of the error correction processing by the CD-ROM decoder 5, the header is not protected against the error and the reliability is inferior to the user data. Therefore, the control microcomputer 7 refers to the error flag transferred from the error flag register 15, determines whether the header information is correct, and then gives an operation instruction to the CD-ROM decoder 5. Further, if the synchronization signal is not detected for a long period of time, or if the header information includes a repeat code error, the control microcomputer 7 determines that the input digital data itself is defective, and the CD-ROM
Data transfer is stopped.

However, in the control microcomputer 7, since the detection of the sync signal and the determination of the header information are performed in parallel with the operation control of the analog signal processing unit 3 and the digital signal processing unit 4, the control microcomputer 7 is controlled. Is becoming a heavy burden. In particular, when a synchronization signal detection error occurs or the header information includes a code error, it is necessary to estimate correct information, which further increases the load on the control microcomputer 7. Therefore, it is difficult to speed up the control operation of the control microcomputer 7, and the CD-
The amount of data that can be handled by the ROM decoder 5 is limited.

Therefore, an object of the present invention is to provide a CD-ROM decoder which has a high function and is easy to use, while reducing the load on a microcomputer for operation control.

[0013]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and the first feature is that digital data read from a disk medium is included in the data. In a CD-ROM decoder that performs error correction processing and transfers it to the computer device side, means for detecting specific information attached to digital data continuously read from a disk medium at fixed intervals, and the specific information are predetermined. And a means for generating an interrupt signal when the signal is not continuously detected for a period of, and the transfer of the digital data read from the disk medium to the computer device side is stopped in response to the interrupt signal.

The second characteristic is that the specific information having a regularity is extracted from the digital data continuously read from the disk medium at a constant cycle, and the extracted specific information is at least one cycle before. Means for determining whether a predetermined regularity is maintained with respect to the specific information, and means for generating an interrupt signal when the regularity of the specific information is not repeatedly maintained for a certain period, The transfer of the digital data read from the disk medium to the computer device side is stopped in response to the interrupt signal.

[0015]

According to the first feature of the present invention, since the interrupt signal is issued when the specific information is not continuously detected from the input digital data for a certain period, the control microcomputer is instructed. The transfer of digital data is stopped without interruption. Therefore, the control microcomputer side does not need to confirm the detection of the specific information, and the load on the microcomputer is reduced.

According to the second feature of the present invention, for the specific code which maintains the predetermined regularity, the interrupt signal is issued when the regularity is not continuously maintained. The transfer of digital data is stopped without asking for instructions. Therefore, it becomes unnecessary for the control microcomputer side to determine whether the specific code is correct, and the load on the microcomputer is reduced.

[0017]

1 is a block diagram showing a first embodiment of a CD-ROM decoder of the present invention. In this figure,
The descrambling circuit 11, the error correction circuit 20, and the like are the same as those in FIG. 8 except for the detection confirmation unit 30 that confirms the detection of the synchronization signal, and are denoted by the same reference numerals.

Based on the timing signal output from the sync signal detection circuit 14, the detection confirmation unit 30 for judging whether or not the sync signal of the CD-ROM data is correctly detected includes a sync signal counter 31 and a sync protection circuit 32. And an error counter 33. The synchronization signal counter 31 is activated by a timing signal supplied from the synchronization signal detection circuit 14, counts a predetermined number of clocks having a constant cycle, and measures the period in which one sector of CD-ROM data is input. A prediction signal that coincides with the timing predicted to detect the sync signal is generated. The synchronization protection circuit 32 includes the prediction signal and the synchronization signal detection circuit 1
The timing signal of No. 4 is taken in, and when the respective signals match, the timing signal is output as it is. When the signals do not match, the timing signal is replaced with the prediction signal and output.
As a result, even when the sync signal detection circuit 14 cannot detect the sync signal, the timing signal is supplied to the operation control circuit 25 as if the sync signal was detected. When the timing signal does not match the prediction signal, a detection error signal indicating that the synchronization signal has not been detected is generated, and this detection error signal is output to the error counter 3
Supply to 3. The error counter 33 performs a counting operation in response to the detection error signal after loading the preset data, and when the count value reaches a certain value, generates a stop instruction and supplies it to the interrupt instruction generating circuit 26.
The preset data loaded in the error counter 33 sets the number of sectors of the sync signal detection error for which the stop instruction is generated, and an arbitrarily changeable value is supplied from the control microcomputer 7. . When the preset data is fixed data, if a register for storing the fixed data is added and the preset data is fetched from this register, it is not necessary to supply the preset data from the control microcomputer 7.

FIG. 2 is a block diagram showing a concrete configuration example of the synchronization protection circuit 32, and FIG. 3 is a timing chart for explaining its operation. The synchronization protection circuit 32 is composed of, for example, an OR gate 34 and an AND gate 35, and includes the timing signal A from the synchronization signal detection circuit 14 and the synchronization signal counter 3.
The prediction signal from 1 is input to the OR gate 34, and the timing signal B which is synchronously protected is obtained from the output of the OR gate 34. Then, the inverted signal of the timing signal A and the output of the OR gate 34 are input to the AND gate 35, and the detection error signal is obtained from the output of the AMD gate 35.

As shown in FIG. 3, the synchronization signal detection circuit 14
If the synchronization signal is not detected by the above, the rising edge of the pulse of the timing signal A disappears, but since the prediction signal has the rising edge of the pulse at a predetermined cycle, OR
In the timing signal B obtained from the gate 34, a pulse rises at a predetermined cycle. Therefore, even when the sync signal detection circuit 14 cannot detect the sync signal, the timing signal B equivalent to that when the sync signal is detected can be obtained from the sync protection circuit 32. And
When the timing signal A and the timing signal B do not match, that is, when a synchronization signal detection error occurs, the detection error signal rises at the timing according to the timing signal B and the error counter 33 counts down.
Therefore, when the stop instruction is generated when the synchronization signal cannot be detected continuously for 3 sectors, “3” is loaded as the preset data in the error counter 33,
The error counter 33 is down-counted at the rising edge of the output of the AND gate 35, and a stop instruction is generated when the count value becomes "0". Therefore, when the sync signal is not detected for one sector or two sectors, the missing pulse of the timing signal A is compensated without generating a stop instruction, and if three or more sectors are not continuously detected, the stop instruction is an interrupt instruction generating circuit. 26.

With the above arrangement, when the synchronization signal detection error continues for several sectors, the transfer of the CD-ROM data is stopped on the CD-ROM decoder 5 side.
At this time, since the control microcomputer 7 that controls the operation of the CD-ROM decoder 5 does not need to perform the detection confirmation of the synchronization signal, it is possible to perform other control operations. Figure 4
FIG. 8 is a block diagram showing a second embodiment of the CD-ROM decoder of the present invention. In this figure, the descrambling circuit 11, the error correction circuit 20, etc. are the same as those in FIG.

As for the CD-ROM data descrambled by the descramble circuit 11, user data is written from the write buffer 12 to the buffer RAM 6 through the first data bus 16, and the header information is taken into the header information judging section 40. . The header information determination unit 40 has an address information determination unit that determines address information and a mode information determination unit that determines a mode identification code.

The address information judging section includes an address information register 41, an adder 42, and a final address information register 4.
3, a selection circuit 44 and a comparison circuit 45.
The address information register 41 fetches and stores 3 bytes of address information representing the minutes, seconds and frame number among the 4 bytes of header information attached to each sector of the CD-ROM data. The adder 42 uses the address information register 4
The address information is read from the 1 or the final address information register 43, and "1" is added to the address information and output. The final address information register 43 fetches and stores the address information output from the adder 42. The selection circuit 44 receives the address information read from the address information register 41 and the final address information register 43, selects one of them and outputs it. Comparison circuit 45
Receives the address information read from each of the registers 41 and 43, determines whether the contents of the information match each other, and generates a control pulse corresponding to the result.

The mode information discriminating section is composed of a mode information register 46, a final mode information register 47, a selection circuit 48 and a comparison circuit 49. Mode information register 4
Reference numeral 6 captures and stores a 1-byte mode identification code of 4-byte header information attached to each sector of the CD-ROM data. The final mode information register 47 fetches and stores the mode identification code read from the mode information register 46. The selection circuit 48 receives the mode identification code read from the mode information register 46 and the final mode information register 47, selects one of them and outputs it. The comparison circuit 49 includes registers 46, 4
The mode identification code read from 7 is received, it is judged whether the contents of mutual information match each other, and a control pulse corresponding to the result is generated.

The control pulse output from the comparison circuits 45 and 49 of each unit is input to the selection control circuit 50 together with the control pulse supplied from the error flag register 15 and used for selection control of the selection circuits 44 and 48. For example, when the address information stored in the address information register 41 and the address information stored in the final address information register 43 match, the address information in the address information register 41 is selected, and when they do not match, the address information in the final address information register 43 is selected and output. It Similarly, when the mode identification codes stored in the mode information register 46 and the final mode information register 47 match, the mode identification code of the mode information register 46 is selected, and when they do not match, the mode identification code of the final mode information register 47 is selected. Is output. These selection controls are similarly performed by the control pulse from the error flag register 15. Normally, the selection control according to the control pulse from the error flag register 15 has priority. At the same time, the control pulse output from the comparison circuit 45 is input to the error counter 51 and causes the error counter 51 loaded with the preset data to count. The error counter 51 has the same configuration as the error counter 33 of FIG. 1, counts control pulses given from the comparison circuit 45 after loading predetermined preset data, and the count value reaches a constant value. Occasionally, a stop instruction is generated and supplied to the interrupt instruction generation circuit 26.

The address information stored in the final address information register 43 deviates by 1 sector from the address information stored in the address information register 41 at the same timing, but "1" is added. , If there is no sign error, the address information stored in the respective registers 41 and 43 match. However, when a code error occurs, the address information stored in the address information register 41 becomes discontinuous, whereas the address information stored in the final address information register 43 becomes continuous at the same timing. Each register 4
The address information stored in Nos. 1 and 43 do not match.
For example, as shown in FIG. 5, the address information register 41
Due to a sign error, the address information input to
It should be "03:15:59" next to "03:15:59" after "5:58".
The address information entered in 3 is "03:15:58" followed by "03:
15:59 ”and regularity is maintained. Therefore, when the address information read from the two registers 41 and 43 does not match, it is determined that the address information stored in the address information register 41 includes a code error,
The comparison circuit 45 causes the selection circuit 44 to select the address information read from the final address information register 43.
At the same time, the comparison circuit 45 counts down the error counter 51, and the count value becomes one smaller than the preset data.

Here, when the stop instruction is generated when the address information contains a code error in three consecutive sectors, as shown in FIG. 5, "3" is loaded into the error counter 51 as preset data. Then, the error counter 51 is down-counted at the rising edge of the control pulse of the comparison circuit 45, and a stop instruction is generated when the count value becomes "0". Therefore, if the address information including a code error is within two consecutive sectors, the address information is corrected without generating a stop instruction, and if three or more sectors are consecutive, a stop instruction is given to the interrupt instruction generating circuit 26.

According to the above configuration, when the correction process of the address information continues for several sectors, the transfer of the CD-ROM data is stopped on the CD-ROM decoder 5 side. At this time, the control microcomputer 7 that controls the operation of the CD-ROM decoder 5 does not need to determine the address information and can perform other control operations.

[0029]

According to the present invention, the CD-ROM decoder itself confirms the detection of the synchronization signal and the determination of the header information without asking for the instruction of the control microcomputer.
If the synchronization signal detection error or the header information code error continues for a predetermined sector or more, the CD-ROM
The decoder judges that the CD-ROM data is defective and automatically stops the transfer to the host computer side. Therefore,
The control microcomputer side does not need to perform detection confirmation of the synchronization signal or judgment of the header information, the load on the control microcomputer can be reduced, and the CD-ROM decoder can promptly respond to the instruction from the host computer. Further, also in the application product of the CD-ROM system, the control microcomputer can be easily developed and the versatility can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a synchronization protection circuit.

FIG. 3 is a timing diagram illustrating the operation of the first embodiment.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a timing diagram illustrating the operation of the second embodiment.

FIG. 6 is a block diagram showing a configuration of a CD-ROM system.

FIG. 7 is a diagram showing a format of CD-ROM data.

FIG. 8 is a block diagram showing a configuration of a conventional CD-ROM decoder.

[Explanation of symbols]

 1 Compact Disc 2 Pickup Section 3 Analog Signal Processing Section 4 Digital Signal Processing Section 5 CD-ROM Decoder 6 Buffer RAM 7 Control Microcomputer 11 Descramble Circuit 12 Write Buffer 13 Header Register 14 Sync Signal Detection Circuit 15 Error Flag Register 16 First Data bus 17 Second data bus 18 Write address generation circuit 19 Start address generation circuit 20 Error correction circuit 21 Transfer address generation circuit 22 Transfer trigger generation circuit 23 Transfer byte counter 24 Transfer buffer 25 Operation control circuit 26 Interrupt instruction generation circuit 30 Detection Confirmation unit 31 Synchronization signal counter 32 Synchronization protection circuit 33 Error counter 40 Header information determination unit 41 Address information register 42 Adder 43 Final address information register 44 selection Circuit 45 comparison circuit 46 the mode information register 47 final mode information register 48 select circuit 49 comparison circuit 50 select control circuit 51 the error counter

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location G06F 11/00 320 B

Claims (4)

[Claims] 1. A CD-ROM decoder that performs correction processing of errors contained in data on digital data read from a disk medium and transfers the digital data to a computer device side. And a means for generating an interrupt signal when the specific code is not continuously detected for a predetermined period, and a computer device for digital data read from the disk medium. A CD-ROM decoder characterized in that the transfer to the side is stopped in response to the interrupt signal. 2. A CD-ROM decoder that performs correction processing of errors contained in data on digital data read from a disk medium and transfers the digital data to a computer device side. Each of the digital data continuously read from the disk medium. A synchronization signal detection circuit for detecting a synchronization signal attached to each sector and generating a first timing signal;
Start up with the first timing signal, measure the period until the input of the digital data for one sector is completed, and then set the second timing signal at the timing at which the synchronization signal is predicted to be detected next. A first counter that occurs,
A second counter that sequentially counts when the first timing signal does not match the second timing signal, and that generates a stop instruction signal when a predetermined number of counts continue. A CD-ROM decoder which stops the transfer of digital data read from the disk medium to the computer device side in response to the stop instruction. 3. A CD-ROM decoder that performs correction processing of errors contained in data on digital data read from a disk medium and transfers the digital data to a computer device side, and continuously reads from the disk medium at a constant cycle. A means for extracting specific information having regularity from the digital data, and at least one piece of the extracted specific information.
And a means for generating an interrupt signal when the regularity of the specific code is not repeatedly maintained for a certain period, and a means for determining whether or not the regularity of the specific information before the cycle is maintained. , Transfer of digital data read from the disk medium to the computer device side,
A CD-ROM decoder which stops in response to the interrupt signal. 4. A CD-ROM decoder that performs correction processing of an error contained in data on digital data read from a disk medium and transfers the digital data to a computer device side, is continuously read from the disk medium at a constant cycle. A first register for extracting and storing specific information that changes according to a certain rule from digital data;
An arithmetic circuit for predicting the specific information after at least one cycle by performing certain arithmetic processing on the specific data stored in the register, and a second operation for storing the arithmetic result of the arithmetic circuit and storing for at least one cycle Register and the above first
And a comparison circuit that determines whether the stored content of the register is matched with the stored content of the second register, and the stored content of the first register is determined not to match the stored content of the second register. And a counter that generates a stop instruction signal when a predetermined number of counts have successively progressed, and the transfer of digital data read from the disk medium to the computer device side is stopped. A CD-ROM decoder which stops in response to an instruction.