JP3300376B2 - Optical disk signal processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing method suitable for digital signal processing of an optical disc, particularly a write-once optical disc, that is, a write-once compact disc.

[0002]

2. Description of the Related Art Recently, audio compact disks have been widely used as optical storage media using lasers, and analog records are being replaced with compact disks.

On the other hand, as a storage medium for digital data, a so-called CD-ROM for recording / reproducing computer data and the like by using a compact disk in a magnetic memory area conventionally used as a large-capacity memory is used. It has become This CD-ROM can record computer data, still images, graphics, etc. in the audio signal area while maintaining system compatibility with audio compact discs.
It has a recordable capacity of 540 Mbytes and is used for mass copying and distribution as well as audio compact discs.

As these conventional compact discs, there are compact discs for audio and CD-ROMs used for electronic publishing as described above, and all of them are read-only ROMs (read-on-read). Memory) type, and the manufacturer of the compact disc records information on the disc in advance. In order to play back this compact disc, there are many decoder playback devices from various manufacturers. However, these devices are playback-only devices, and no writing circuit is supported.

Recently, a write-once optical disc which satisfies the compact disc standard has been proposed, and a so-called Orange Book standard which has established a format for recording and reproducing on the write-once disc has also been proposed.

[0006]

As described above, since recording on a compact disc was conventionally performed by the manufacturer of the compact disc, the recording apparatus was large in size for recording and the like. As described above, the conventional compact disk decoder and playback device are used for playback and the like, and it is impossible to incorporate a recording device used by a manufacturer of a compact disc into a playback device. The present invention provides a so-called Orange Book-compliant semiconductor integrated circuit for recording and reproducing data on and from a write-once compact disc, and a signal processing method for easily manufacturing a recording / playback apparatus for a write-once compact disc.
That is the subject.

[0007]

SUMMARY OF THE INVENTION The present invention relates to an optical disk.
Read data and write to optical disc
Optical disk for writing write data into storage means
The signal processing method according to claim 1, wherein the storage unit includes a plurality of pages.
The page is divided into units, and the page is
I / O buffer for exchanging data with disk
ADPCM buffer that stores pages and ADPCM data
Allocated to the I / O buffer page
Data can be transferred between the buffer pages for ADPCM and ADPCM
And the I / O buffer page is external when encoding.
While taking in data from the host CPU, ADP
Write to optical disk transferred from CM buffer page
Holds the ADPCM data to be read and decodes the optical disc
From the host CPU or A
Holds data to be sent to the DPCM buffer page,
While reading the disk, while continuing the read operation, A
Write when DPCM decoding is needed
ADPCM encoding is completed while reading operation data.
Completed data to the optical disk without passing through the host
When I want to write, I / O buffer page and ADP
It is characterized in that data is transferred between CM buffer pages .

Further, the present invention takes the area of one page wider than the data format specified in the optical disk, and sets an audio flag for indicating an uncorrected block to be sent to the host CPU in a surplus area of the page. It is characterized in that it is used as an area in which information or a flag obtained at the time of error correction for a block for performing error correction and used for the next error correction is written.

Further, the present invention relates to an ADPC for the storage means.
The buffer page for M is allocated so that it can be used freely through the interface with the host CPU and the serial port when reading the signal fetched into the storage means and writing the data signal for writing. It is characterized by.

[0010]

SUMMARY OF] According to the present invention, among the data read from the optical disk, and need to be sent to the host CPU rather name AD
Blocks used for PCM playback etc. can be ADPC at high speed
The data can be transferred to the M decoder, and the ADPCM decoder does not need to have its own buffer memory. Further, according to the present invention, the storage means can be used efficiently. Furthermore, while writing and reading to and from the optical disc, the AD
PCM playback and ADPCM encoding become possible,
Expand the range of applications.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

[0012] Figure 1 a schematic block diagram of a signal processing semiconductor integrated circuit using the invention in Yoko, FIG. 2 is a block diagram showing the overall structure.

As shown in FIGS. 1 and 2, a compact disk-digital audio (hereinafter abbreviated as CD-DA) interface circuit 100 includes a signal read from a compact disk and EFM-demodulated.
IRC (Cross Interleaved Reed Solomon
A serial signal of a signal (hereinafter abbreviated as a CD-DA signal) corrected by code demodulation is captured. Then, the CD-DA interface circuit 100 converts a serial signal into a parallel signal.

On the other hand, since the above-mentioned CD-DA signal is scrambled, the taken-in CD-DA signal is descrambled, and an external 128-Kbit static random access memory (hereinafter abbreviated as RAM). .) Is sent to the internal data bus 1 in order to store this signal in 10. At this time, the RAM is sent from the CD-DA interface circuit 100 to the internal address bus 2.
Address data to be written to 10 is given. The read data signal transmitted to the internal data bus 1 is RA
It is provided to the RAM 10 via the M interface 880. The RAM 10 has a RAM interface 880
, The address is specified by the address data supplied to the internal address data bus 2, and the read data signal is stored in a predetermined area of the RAM 10.

Further, the CD-DA interface circuit 1
00 is provided with an audio (A) flag indicating that error correction could not be performed during CIRC decoding. This A flag is stored as error detection in a predetermined area of the RAM 10 via the internal data bus 1 and the RAM interface 880 in the same manner as described above.
Further, the CD-DA interface circuit 100 receives a word synchronization signal at the time of reading and a serial out enable (SOE) signal at the time of writing. At the time of writing, a block synchronization signal is created based on the SOE signal. At the time of writing, the CD-DA interface circuit 100 reads out write data from the RAM 10, scrambles the data, converts a parallel signal into a serial signal, and outputs the serial signal.

An error correction code (hereinafter abbreviated as ECC) generation and error correction circuit 200 is a RAM 10.
Is read out, error-corrected, and the error-corrected data is transferred to the RAM 1 via the internal data bus 1 and the RAM interface 880.
0 is stored in a predetermined area. The RAM 10 is connected to the ECC addition / error correction circuit 20 via the RAM interface 880.
The address is designated by address data given to the internal address bus 2 from 0.

Further, the EEC addition / error correction circuit 200
At the time of writing, the CPU reads out the write data stored in the RAM 10 to generate an ECC, and stores the ECC in a predetermined area of the RAM 10 as described above.

Error detection code (hereinafter referred to as EDC)
The addition and error detection circuit 300 extracts the read data stored in the RAM 10 and performs error detection. At the time of writing, the data for writing stored in the RAM 10 is read to generate an EDC, and the EDC is stored in a predetermined area of the internal RAM 10. At this time, the address of the RAM 10 is specified by applying the address generated by the address generation circuit 450 of the EDC / sector logic to the RAM interface 880 via the internal address bus 2.

The sector logic circuit 400 is a RAM 10
The header and the subheader are read from the data taken in by the. Then, the read header and subheader are stored in a syscon register in a syscon interface 500 for interfacing with an externally provided system controller processor (hereinafter referred to as syscon) for controlling the system of this integrated circuit. I do. The sector logic circuit 400 fetches the header and sub-header stored in the system register and adds the data to the data in the RAM 10 via the internal data bus 1. At this time, the address specification of the RAM 10 is ED
The address generated by the C / sector logic address generation circuit 450 is transferred to the RA via the internal address bus 2.
This is performed by being provided to the M interface 880.

The sequencer 350 includes an ECC addition / error correction circuit 200 and an EDC addition / error detection circuit 30
0, respectively controls the sector logic circuit 400 and the EDC / sector logic address generation circuit 450.

RAM logic 850 between pages of pages
Is a circuit for transferring a direct memory access (hereinafter abbreviated as DMA) between the I / O buffer and the ADPCM buffer of the RAM 10 in page units.

The host interface circuit 600 interfaces with a host data bus of an external host CPU (hereinafter referred to as a host) and controls DMA between the host and the RAM 10. The host interface circuit 600 and the system controller interface circuit 500 are connected to each other by a communication function block circuit 700 described later, and commands and indications are exchanged between the host and the system controller.

The serial port circuit 900 has a RAM 10
Is read out and serially output, and the serially input data is written into the RAM 10. It also outputs read data serially.

Arbitration logic circuit 800
Are the CD-DA interface 100, the sequencer 350, the sector logic circuit 400, the host interface 600, and the RAM logic 8 between RAM pages.
50, connected to the serial port 900,
The arbitration is performed when an access request to the AM 10 collides, and the RAM 10 is arbitrated according to a predetermined priority.
Determine access to.

The RAM interface circuit 880 outputs an internal data bus 1, an internal address bus 2, a RAM write signal, and a read signal.

The system controller interface circuit 500
It interfaces with the system control processor bus, determines the state of each circuit, and controls each unit. As described above, the system interface circuit 500 and the host interface circuit 600 are connected to each other by the communication function block circuit 700, and commands and indications are exchanged between the host and the system controller.

The communication function block circuit 700 includes a command register file and an indication register file, and controls communication between the host and the system controller.

The master state logic circuit 950 includes:
This is used when the state of the entire chip is controlled and the state of the chip is monitored by the system controller in synchronization with the block synchronization.

The semiconductor integrated circuit of this embodiment is constructed as described above, and each of these circuits is provided on the same semiconductor substrate to form a one-chip digital signal processing semiconductor device. However, the specific configuration of each of the above components will be sequentially described with reference to FIGS.

(1) CD-DA interface 100 (see FIG. 3)
FIG. 3 is a block diagram showing details of the CD-DA interface 100.

In the CD-DA interface circuit 100, RDATA composed of a serial signal of a CD-DA signal read from a compact disk is input to a serial / parallel conversion shift register 101.

On the other hand, the word synchronizing signal is
14 is input. The counter 114 is reset by the word synchronization signal and counts from 0 to 97. The output of the counter 114 is provided to a decoder 115,
The decoder 115 calculates a counter value. Then, the calculated counter value is supplied to the control circuit 125. After word synchronization, the control circuit 125
When the value of 4 becomes a predetermined value, a signal is given to the shift register 101. The shift register 101 takes in RDATA based on a signal from the control circuit 125, and
When 16 bits of A are fetched, the selector 103
To output a 16-bit signal.

The selector 103 is controlled by the system controller, and selects and outputs one of the output of the register 102 for taking in the data read from the RAM 10 and the output of the shift register 101. Assuming now that data is to be read from a CD, the selector 103 selects and outputs the output of the shift register 101. This selector 10
The output from 3 is supplied to the synchronous pattern detection circuit 107 and the exclusive OR circuit 105.

When the synchronization pattern detection circuit 107 detects a synchronization signal from the received RDATA, the detection circuit 10
7 to the block synchronization signal generator 118 and the control circuit 1 respectively.
25. The control circuit 125 establishes block synchronization based on the detection of the synchronization signal, resets the word counter 116, and sends a signal from the block synchronization signal generator 118 to the page counter 119. The page counter 119 is used to select a page of the RAM 10 that has been paged as shown in FIG.

Here, the external RAM 10 will be briefly described. In this embodiment, an external R of 8K × 16W is used.
The AM 10 is connected, and the RAM 10 is paged as shown in FIG. Then, RDATA read from the disk or data WDA to be written to the disk
The TA is cyclically stored in blocks of pages 0 to 3 of the IO buffer. Also, IO buffer and AD
The data is transferred between the PCM buffer and the PCM buffer in a page unit by the RAM inter-page DMA logic circuit 850. This operation will be described later.

FIG. 5 shows the data format of the IO buffer. In this embodiment, four formats can be selected. Which format is selected is determined by a signal from the system controller or bits 5 and 8 output from the sector logic circuit 400. An address to which data is to be written is determined according to each format.

When the synchronous pattern detecting circuit 107 detects the synchronous pattern, the block is synchronized.
The word counter 116 is reset, its output is given to the absolute address generator 121, the output of the page counter 119 is calculated by the decoder 12, and the number of pages is also supplied to the absolute address generator 121 by the decoder 120. The address corresponding to FIG. 4 and FIG.
22 to the internal address bus 2. First, RDATA is stored in page 0 of the IO buffer. Then, the page counter 1 is obtained by the following synchronization pattern.
19 is incremented, and data is stored in page 1. In addition, ECC,
EDC and HRD (processing performed by the sector logic circuit 400) are performed by the operation of each circuit described later. Then, the page counter 119 is incremented every block synchronization, and the process is repeated.

The three-state buffer 122 is controlled by an address enable (AE) signal output from the arbitration logic circuit 800.

On the other hand, since RDATA selected by the selector 103 from the shift register 101 is scrambled, the exclusive OR circuit 105 and the 1,0 signal output from the scrambler / descrambler circuit 104 and the exclusive logic The sum is descrambled and supplied to the selector circuit 110.

The timing of taking in the audio flag is controlled by the control circuit 125, and the shift register 1
The output of the shift register 123 is supplied to a shift register 109 for serial / parallel conversion via an OR circuit 108 and the internal data bus 1 and the sector logic circuit 400 via three-state buffers 112 and 113. Are supplied as flags.
The output of the shift register 109 is supplied to the selector 110. The shift register 109 and the selector 110 are controlled by the control circuit 125. The reason why the audio flag is taken into the shift register 109 is that the audio flag is used in controlling to write this flag in an extra area of the page because the host may want to know the audio flag in some cases. The data selected by the selector 110 is transferred to the RAM 1 via the three-state buffer 111.
The signal is sent to the internal data bus 1 in order to store this signal in the "0". At this time, the internal address data bus 2 is connected to the RAM
The address data to be written to 10 is given from the absolute address generator 121.

The control circuit 125 receives a system control signal, a block synchronization at the time of writing, and a serial out enable SOE signal. In addition, the control circuit outputs an RQ signal requesting reading or writing to the arbitration logic 800 at the time of reading / writing. Then, the three-state buffers 111, 112, 113
Arbitration logic circuit 80 corresponding to Q signal
It is controlled by a write enable signal WE from 0.

A page signal is output from the decoder 120, and this signal is supplied to circuits for generating EDC and ECC addresses, respectively. From the shift register 106, the write data WDATA read from the RAM 10 is ORed by the exclusive OR circuit 105 with the signal output from the scrambler / descrambler circuit 104, and the scrambled signal is input. This signal is output as a serial signal. A predetermined 1, 0 signal is output from the scrambler / descrambler circuit 104,
By taking exclusive OR, the read signal is descrambled and the write signal is scrambled. Therefore, the scrambler / descrambler circuit 104 is used for both writing and reading.

Then, between the fifth bit and the eighth bit of the 16-bit data of the shift register 101 are supplied to the sector logic circuit 400 as bit 5 and 8 signals.

(2) ECC addition / error correction circuit 200
(See FIGS. 6 to 14)

The ECC addition / error correction circuit 200 calculates R
The read data stored in the AM 10 is taken out, error correction is performed, and the error-corrected data is transferred via the internal data bus 1 and the RAM interface 880.
The data is stored in a predetermined area of the RAM 10 according to the format shown in FIG.
0 is read out to generate EEC, and this ECC is stored in the RAM 10 in the same manner as described above.
Is stored in a predetermined area.

Before describing a specific embodiment of the ECC addition / error correction circuit 200, the features of the circuit in this embodiment will be described.

The ECC addition / error correction circuit 200 in this embodiment integrates error correction and ECC generation. That is, a syndrome (hereinafter abbreviated as sy) calculation circuit 211, a GF calculation unit 230, and an address generation unit 25
0, the register for writing is commonly used.

The circuit of this embodiment generates a signal (PPQQ) from the address generation unit 250 when reading data of an address corresponding to the P and Q parity units in the syndrome calculation at the time of ECC generation, and generates a sy calculation circuit. It is configured to disable the gate at the entrance of 211 and load zero into the sy calculation circuit.

A selector is provided at the input unit of the GF operation unit 230, and a mechanism for generating a coefficient is provided to one input of the selector, so as to cope with both error correction and parity generation.

The ECC addition / error correction circuit 200
Is controlled by the sequencer 350, but the sequencer 3
At 50, the syndrome calculation at the time of correction and generation is performed by the same code (subroutine).

With the above-described configuration, both functions of ECC generation and error correction can be realized with a small circuit scale. The sequencer 350 can also be implemented on a small scale by subroutines.

Encoding in the format of CD-I,
At the time of decoding, at the time of sy calculation, when the address of the data corresponding to the header is generated from the address generation unit 250, (PPQQF1) is output, the gate at the entrance of the sy calculation circuit 211 is disabled, and zero is calculated. 21
1 is configured to be loaded.

At the time of error correction in the CD-I format, it is determined that there is an error in the header portion, and when the error is to be corrected, the same signal (PPQQF1) as above is output from the address generator 250. RAM10 by signal
It is configured to prevent writing of correction data to the memory.

With the above configuration, the sequencer and the ECC signal processing unit 210 can be used in a CD-ROM, a CD-I
Can be exactly the same. Erroneous correction of the header can be prevented. C
At the time of DI, the header part is regarded as zero.

Error correction and ECC generation are performed in 8-bit units, but access to the external RAM 10 is performed in 16 bits. That is, the standard orange
Format of write-once optical discs conforming to the standard
Means that the number of words in the processing unit handled at one time as signal processing is
It is defined in the standard. Upper byte of this processing word
Side and lower byte side.
It is defined in the standard to perform encoding and decoding.
For this reason, the RAM 10 stores the upper byte as described later.
The plane that collects only the side bytes and the lower byte
And each plane
A similar ECC process is performed.

Therefore, the sy calculation circuit 211, the exit gate, the write register, the entrance selector, the error determination circuit, the error word position register, the exit gate, and the flag counter are divided into two for the upper byte and the lower byte.
The other parts are configured for one byte. It has a function of switching between the upper byte and the lower byte, and the above upper and lower bytes are selected by this switching, so that the actual processing unit of the sequencer is configured to be the same for both the upper and lower bytes. Upper byte, lower byte sy
The calculation, the counting of the number of flags, and the storage of the error word position are performed simultaneously.

With the above configuration, the data width of the external RAM 10 can be set to 16 bits, and a system can be easily connected to a 16-bit host. Since the entire circuit does not have 2 bytes, the size of the circuit can be reduced. Further, the size of the sequencer can be reduced. The number of access circuits to the RAM 10 can be reduced and the RAM 10 can be used for RAM access of other blocks.

Further, the ECC addition / error correction circuit 200 of this embodiment stores an error flag when there is an error determined to be uncorrectable at the time of decoding, and uses the flag at the time of next decoding. It is configured to perform erasure correction. Further, it is configured to perform error correction by combining detection correction, erasure correction using an audio flag, and the above correction.

Even if the result of the sy calculation is S0 ≠ 0 or S1 ≠ 0, the in-range determination is performed without immediately performing the one-symbol error correction, and the error flag is set without performing the error correction if the error is out of the range. It is configured as follows.

With the above configuration, two symbols can be corrected by the erasure without using the audio flag, and a high error correction capability can be provided without using the RAM for the audio flag.

Next, the ECC addition / error correction circuit 200 according to this embodiment will be further described.

As shown in FIG. 6, the ECC addition / error correction circuit 200 includes an ECC signal processing section 210 and an ECC address generation section 250.

First, a syndrome (sy) calculation circuit 211 is sent from the internal data bus 1 to the ECC signal processing unit 210.
Is supplied to the RAM 10, and the sy calculation circuit 211 performs sy calculation according to a calculation formula described later to generate ECC or correct an error. The syndrome is calculated and input to the sy calculation circuit 211 in advance, and the calculation result is supplied to the IN bus 201 of the ECC addition / error correction circuit 200 and the IN bus 20
1 to the error word correction logic 220 and the GF operation unit 230, respectively. The GF calculation unit 230 performs calculations based on the PENC calculation formula and the QENC calculation formula described later, calculates an error pattern from the error pattern calculation function unit of the GF calculation circuit 230, and outputs the result from the IN bus 201 as an error. Word correction logic 2
20. Error word correction logic circuit 22
A predetermined error correction such as one symbol correction at 0, two symbol correction by erasure correction using an error flag obtained as a result of pre-decoding (DEC), and two symbol correction using an audio flag is performed. The data is supplied to the data bus 1 and stored in the RAM 10.

The error word position calculation function of the GF operation unit 230 supplies error word position data to the word position address conversion circuit 280 of the ECC address generation unit 250 via the EA bus 202. GF
The error detection result is supplied from the arithmetic unit 230 to the error flag number count / error number determination circuit 240. Further, an error flag is provided from the internal data bus 1 to the error flag number count / error number determination circuit 240, and a load signal is supplied from the error flag number count / error number determination circuit 240 to the flag word position register 241.

The output of the flag word position register 241 is supplied to the EA bus 202.
The number of errors is output to 50.

The ECC address generating section 250 has a word position counter 260, and the respective P and Q counter values from the word position counter 260 are supplied to a word position / address conversion circuit 280 and a flag word position register 241. Word position address conversion circuit 280 to absolute address conversion circuit 2
Data is output to 90, the absolute address of the RAM 10 is calculated, and an address signal is supplied to the internal address bus 2.

Each of these circuits is controlled by a sequencer 350, and the sequencer 350 supplies a control signal to each circuit. Further, the arbitration logic circuit 80
0 to request signal RQ for writing / reading to / from RAM 10
And the signal EX indicating the execution right to the RAM 10 is given from the arbitration logic circuit 800.

Next, the ECC signal processing section 210 will be further described with reference to FIG. First, ECC (PENC, QEN
The generation of C) will be described.

The sy calculation circuit 211 has the S1H calculation circuit 2
15, an S0H calculation circuit 214, an S1L calculation circuit 213, and an S0L calculation circuit 212. Here, L indicates low byte and H indicates high byte. Hereinafter, L and H are the same.

After clearing the S0L calculation circuit 212, data is sequentially input from the internal data bus 1 via the AND circuit 10L, and sys0L is calculated. This syS0L is output to the gate 1L. ECC for AND circuit 10L
Based on the PPQQ from the address generation circuit 250, a DBE signal generated by the arbitration logic circuit 800 with the timing adjusted to the RAM access is input.
That is, data is sequentially input from the internal data bus 1 in accordance with the RAM access timing by the arbitration logic circuit 800.

The ECC is processed in units of bytes. Since the internal data bus 1 has a 16-bit structure, access to the RAM 10 is always made in units of words (16 bits). Then, since the ECC processes the 16-bit configuration in byte units, as described above, each calculation circuit is provided with two upper and lower bits, and is configured to input the upper and lower bytes, respectively. I have. Therefore, S0L
The lower byte is input to the calculation circuit 212. Also, R
The access request to AM 10 is output from the sequencer. After clearing the S0H calculation circuit 214 as well, data is sequentially input from the internal data bus via the AND circuit 10H, and SYSOH is calculated. This AND circuit 10H
, A DBE signal is input, and data is sequentially input from the internal data bus 1 in accordance with the RAM access timing by the arbitration logic circuit 800. The upper byte is input to the S0H calculation circuit 214. The calculation result is output to the gate 1H.

On the other hand, when the ECC is generated, the part corresponding to the parity is 0 in the syndrome calculation, and when writing the data of the RAM 10 corresponding to this, the DBE is used.
The signal becomes false, and 0 is forcibly input to the SOL calculation circuit 212 and the SOH calculation circuit 214.

After the S1L calculation circuit 213 is also cleared, data is sequentially transferred from the internal data bus 1 to the AND circuit 2.
SY1L is calculated by inputting via 0L. The AND circuit 20L is configured to receive a DBE signal and sequentially input data from the internal data bus 1 in accordance with a RAM access timing by the arbitration logic circuit 800. This S1L calculation circuit 2
13 is input with the lower byte. The calculation result is output to the gate 2L.

After the S1H calculation circuit 215 is also cleared,
Data is sequentially input from the internal data bus 1 via the AND circuit 20H, and sysS1H is calculated. The DBE signal is input to the AND circuit 20H, and data is sequentially input from the internal data bus 1 in accordance with the RAM access timing by the arbitration logic circuit 800. The upper byte is input to the S1H calculation circuit 215. The calculation result is output to the gate 2H.

As described above, at the time of ECC generation, a part corresponding to parity is 0 in the syndrome calculation.
Therefore, when writing data in the RAM 10 corresponding to this, the DBE signal becomes false and the S1L calculation circuit 2
0 is forcibly input to 13 and the S1H calculation circuit 215. In this way, the respective calculation results are calculated from the sy calculation circuit 211, and this data is supplied to the GF calculation unit 230 and the error word correction logic 220.

The equation for calculating the syndrome of PENC and QENC and the equation for calculating the parity of P and Q to be calculated next are shown below. By making the DBE signal false as described above, the last two terms of each formula can be forcibly set to zero.

Calculation formula of PENC Syndrome S0L = W0L + W1L + ... + W22L + W23L + 0 + 0 S1L = α ²⁵ W0L + α ²⁴ W1L… α ³ W22L + α ² W23L + 0 + 0 S0H = W0H + W1H + ... … + W22H + W23H + 0 + 0 S1H = α ²⁵ W0H + α ²⁴ W1H… α ³ W22H + α ² W23H + 0 + 0 Parity P0L = α ²³⁰ S0L + α ²³⁰ S1L P0H = α ²³⁰ S0H + α ²³⁰ S1H P0 = (P0H, P0L) P1L = α ²³¹ S0L + α ²³⁰ S1L P1H = α ²³¹ S0H + α ²³⁰ S1H P1 = (P1H, P1L)

Calculation formula of QENC Syndrome S0L = W0L + W1L + ... + W41L + W42L + 0 + 0 S1L = α ⁴⁴ W0L + α ⁴³ W1L… α ³ W41L + α ² W42L + 0 + 0 S0H = W0H + W1H + ... … + W41H + W42H + 0 + 0 S1H = α ⁴⁴ W0H + α ⁴³ W1H… α ³ W41H + α ² W42H + 0 + 0 Parity Q0L = α ²³⁰ S0L + α ²³⁰ S1L Q0H = α ²³⁰ S0H + α ²³⁰ S1H Q0 = (Q0H, Q0L) Q1L = α ²³¹ S0L + α ²³⁰ S1L Q1H = α ²³¹ S0H + α ²³⁰ S1H Q1 = (Q1H, Q1L)

Next, the calculation of the parity of P and Q is shown in FIG.
This will be described with reference to FIG. Both these parities are calculated by the GF operation unit 2
30, calculated by the error word correction logic 220.

The calculation of the P parity will be described. Clear the registers W10, W3L, W3H. Then, the gate 1L is opened and the log S0L is loaded from the ROM 231 in which the logarithm is stored in the register W9 in advance. on the other hand,
A constant 230 is generated from the coefficient generation circuit 232, and this coefficient is loaded into the register W8 by selecting the selector 8 on the B side. After the two values are added by the adder / subtractor 233, the selector 234 is selected on the A side and the selector 10 is selected on the A side, and α ²³⁰ S0L is loaded into the register W10.

The gate 2L is opened and the above RO is stored in the register W9.
Similarly, logS1L is loaded from M231. Further, a constant 230 is generated from the coefficient generation circuit 232 and
Is selected on the B side, this coefficient is stored in the register W8.
Is loaded. After the two values are added by the adder / subtractor 233, the selector 234 is selected on the A side and the selector 10 is selected on the A side, and α ²³⁰ S1L is loaded into the register W10. After the two values are added by the adder / subtractor 233, the selector A is selected on the A side, and the selector 10 is selected on the A side.
When loaded into the register W10, the value α ²³⁰ S0L + α ²³⁰ S1L of the parity P0L is stored in the register W10.

Subsequently, the gate G10 is opened, and the
L is selected on the B side, and the parity P0L is loaded into the register W3L via the internal data bus 1. Similarly, the parity P0H is obtained and loaded into the register W3H. The gate G3 is opened, and the P0 parity is written to a predetermined address in the RAM 10 via the internal data bus 1.

Further, by simply changing the coefficient, the P1 parity is similarly calculated, and the value is written to the RAM 10. Also, the calculation of the Q parity can be calculated in the same manner as can be understood from the above-described calculation formula.

The address is an ECC address generation circuit 250
Is generated by controlling the P counter and the Q counter. The address generating circuit 250 for generating this address will be described later in detail.

Next, error correction will be further described. As shown in the flowchart of FIG.
Is decoded (DEC). In the Q1DEC, one symbol correction by detection correction or two symbol correction by erasure correction using an audio flag is performed. Subsequently, P1DEC is performed. In P1DEC, one symbol correction by detection correction or two erasure correction by erasure correction using a flag obtained as a result of the previous DEC.
Symbol correction is performed.

Then, it is determined whether or not to perform error correction. If error correction is to be continued, Q2D
EC and P2DEC are performed. Q2DEC, P2DE
In C, one symbol correction by detection correction or two erasure correction by a flag obtained as a result of the previous DEC.
Symbol correction is performed. Error correction in this embodiment will be further described.

First, sy calculation is performed. This sy calculation is performed by the same method using the same circuit as the ECC generation. That is, for this sy calculation, the same circuit is used for ECC generation and error correction. However, the control of PPQQ in the address generation circuit 250 is different from that at the time of ECC generation, and the DBE signal is always true.

Subsequently, the count of the number of flags (FN) and the error word position (J ′, K ′) are stored in the flag word position register 241.

In Q1DEC, an audio flag is read from the data D16 and D17 from the internal data bus 1 at the same time as the Sy calculation, the number of flags is counted by the flag counter 240, and the position of the first flag (QCN
T, and the selector PQ at this time (Q side) is stored in the registers JL and JH as J '. Further, the position of the second flag is similarly set to K ′, and the register KL and the register K
Store in H. When the number of flags is two, these J 'and K' become error word positions, and two symbol correction by erasure correction is performed.

In P1DEC, Q2DEC, and P2DEC, an error flag obtained by the previous error correction processing is used instead of the audio flag. In this case, S
Apart from the y calculation, the error flag is read out, the number of flags FN is counted, and the error word positions J 'and K' are stored. In addition, the number of errors (ER)
The error position (J) is calculated.

The gate 1L is opened and the register W8 stores the ROM2
Word logS0L from 31. At this time, the selector 8 is selected on the A side.

The gate 2L is opened and the register W9 stores the ROM2
Load logS1L from 31. Register W8, W
The output of 9 is supplied to an in-range determination circuit 251, an error number determination circuit H252, and an error number determination circuit L253, respectively. Depending on the configuration of the ROM 231, the registers W8, W9
By examining D8 of the syndrome S0L (S0
H) and zero detection of S1L (S1H ).

When the values of the registers W8 and W9 are subtracted by the adder / subtractor 233, log (S1L / S0L) is output, and an error position is output. This is the error position J.

Then, the syndromes S0L ≠ 0, S1L
$ 0, ie a single error or apparently a single error
If there is a flag , the in-range determination is performed, and if J is QDEC, the flag number FN is smaller than 44, if J is PDEC, it is smaller than 25.
In the case of # 2, one-symbol error correction is performed. When the number of flags FN = 2, two-symbol error correction is performed.
When FN ≠ 2, SOL = 0, and SIL = 0, it is determined that there is no error, no error correction is performed, and the error flag is set to 0.
And Otherwise, the error flag is set to 1.

For the high byte, the signal S0L is
The output from the Sy calculation circuit 211 is selected so that the SIL changes to the SIH and the error (ER) calculation and the error position (J) calculation are performed in the same manner as described above.

Next, one-symbol error correction (detection correction) will be described. First, the registers W3H, W3L, W1
Clear O. The error pattern at this time is S0L. The GIL is opened, the selector 3L is set to the B side, and SOL is loaded into the register W3L.

The error position conversion circuit 1 converts the error position (J) into an error word position J '. The error word position J 'is converted to J' = (44-J) for QDEC and J '= (25-J) for PDEC.

Then, the gate G8 is opened to output the error word position J 'to the EA bus 202.

The ECC address generation circuit 250 generates an address of error data, and loads data having an error into the registers W3H and W3L. The error is corrected by opening the gate 1L, selecting the selector 3L on the B side, and loading the register W3L. An address is generated again by the ECC address generation circuit 250, and the registers 3WH and W3L
Is written in the RAM 10. At this time, the H (high) byte side simply reads / writes the same data.

Next, two-symbol correction (erasure correction)
Will be described. In the case of two-symbol correction, the error word positions J'L and K'L are both in the registers JL,
Stored at KL.

First, an error pattern EJL is calculated.
The registers W10, W3L, W3H are cleared. Then, the gates 6L and 56 are opened, and the K of α is stored in the register W10.
Load L-th power. At this time, the selector 234 selects the B side, and the selector PQ2 selects the Q side for QDEC and the P side for PDEC. Then, the error position conversion circuit converts the error word position into the error position.

The gate G10 is opened and KL is loaded into the register W8. At this time, the selector A has selected the A side. The gate 1L is opened, and logS0L is loaded from the ROM 231 into the register W9. Then, the register W10 is cleared.

Subsequently, the gate G8 is opened to open the register W10.
Is loaded with S0L of α to the power of KL. At this time, the adder / subtractor 233 performs addition, the selector 234 is on the A side,
0 selects the A side.

Next, the gate 2L is opened and the register W10 is opened.
A value A obtained by adding S1L to S0L of α to the power of KL is loaded. Then, the gate G10 is opened and the log 9 is stored in the register 9.
A is loaded and the register W10 is cleared.

Thereafter, the gates 5L and 56 are opened, and α is raised to the power of JL into the register W10.
4 is B side, selector PQ2 is Q, PDE in case of QPEC
In the case of C, P is selected. The error position conversion circuit 237 converts an error word position into an error position.

The gates 6L and 56 are opened, and the register W10 is opened.
Is loaded with a value B obtained by adding α to the KL and α to the JL. At this time, the selector 234 is connected to the selector PQ242.
Is the same as above.

Next, the gate G10 is opened, and the register W8 is opened.
To load logB. At this time, the selector A has selected the A side. Then, after clearing the register W10, A / B = EJL is loaded into the register W10. At this time, the adder / subtractor 233 is subtracted, the selector A is selected on the A side, and the selector 10 is selected on the A side.

Thereafter, the gate G10 is opened and the register W3 is opened.
2. Load the EJL. At this time, the selector 3L outputs B
Is selected.

Next, the gates 5L and 56 are opened, and the error word position J 'is output to the EA bus 202. At this time, the selector PQ2 selects P for PDEC and Q for QDEC. And an ECC address generation circuit 2
50 generates the address of the error data, and the error correction is performed by loading the error data into the registers W3H and W3L. At this time, the selector 3L has selected the A side.

After that, the address generation circuit generates an address again, opens the gate G3, and stores the corrected data in the RAM 10.
Is written to.

Thereafter, similarly, the gate 1L is opened, and ES + S0L = EK is loaded into the register W10. Then, the registers W3H and W3L are cleared. Thereafter, the gate G10 is opened and EK is loaded into the register W3L.

Then, the gates 6L and 56 are opened, the error word position J 'is output to the EA bus 202, and the ECC
The address generation circuit 250 generates an address of the error data, performs error correction in the same manner as described above, and writes the corrected data to the RAM 10.

Next, flag writing will be described. As for the flag, there is no error, error flag = 0 is written at the time of 1 symbol correction execution and 2 symbol correction execution, and error flag = 1 is written at other times. The type of the error flag to be written is determined by the error number determination circuits 252 and 253,
P counter and Q counter 2 of C address generation circuit 250
60 is controlled to generate a flag address, and the gate G4 is opened to write a flag.

The calculation formulas used for the above-mentioned PDEC and QDEC are shown below.

DEC calculation formula QDEC syndrome S0L = W0L + W1L + ... + W43L + W44L S1L = α ⁴⁴ W0L + α ⁴³ W1L… αW43L + W44L S0H = W0H + W1H + …… + W43H + W44H S1H = α ⁴⁴ W0H + α ⁴³ W1H ... ^αW43H + W44H PDEC syndrome S0L = W0L + W1L + ...... + W24L + W25L S1L = α 25 W0L + α 24 W1L ... αW24L + W25L S0H = W0H + W1H + ...... + W24H + W25H S1H = α 25 W0H + α ²⁴ W1H… αW24H + W25H

Number of Flags The flags are read and the number is counted by FNLCNT and FNHCNT. At the same time, check the error position.

[0116]

(Equation 1)

[0117]

(Equation 2)

[0118]

(Equation 3)

Whether each of them is 0 or not 0 is not 0 depending on the case, but may seem as a single error in appearance.

Single error correction (detection correction)

[0121]

(Equation 4)

FIGS. 9 and 10 are flowcharts showing the P and Q decoding operations described above. 9 and 10, H indicates a high byte, L indicates a low byte, FN indicates the number of flags, and J and K indicate error positions.

Next, the address generation circuit 25 of this embodiment
0 will be described.

First, the assignment of addresses in the RAM 10 will be described. The header, user data, P parity, Q parity, P flag, and Q flag are allocated in the I / O buffer page as follows.

[0125]

[Table 1]

This address generating circuit 250 generates the addresses shown in FIGS.

FIG. 11 shows the assignment of Q word addresses.
2 indicates the assignment of the address of the P word.

In FIG. 11, parity is written in QY0 and QY1, and the address of a flag for writing the result of QECC is specified in QFL. The address is specified by the values of the Q counter (QCNT) and the P counter (PCNT). The PEL 26 is an address of a P flag to be referred to in the case of QECC.

FIG. 12 shows the address of the P flag for writing the result of the PECC.
Performed by T and PCNT.

Note that 1239-1279 (41 words) are addresses that are not subject to ECC. The address has two branes of L bytes and H bytes.

FIG. 13 shows the address of the Q flag to be referred to in the case of PECC. The address is circulated by the group number NP and the data number MP in order to associate the data with the position of the Q flag.

The function of the ECC address generation circuit 250 is E
This is to generate an address when generating a CC and decoding an ECC. The values of the P counter 261 and the Q counter 262 as the position counter 260 of the ECC address generation circuit 250 are output as QCNT and PCNT, and are given to the selector P263 and the selector Q264. Selectors P263 and Q264 are PCNT, QCN
Select the error address from the T and EA bus 202.
The outputs from the selectors P263 and Q264 are ROMP, RO for creating an address from the count values of P and Q.
The signals are respectively supplied to the MQs and are supplied to the decoder PQ and the selectors PR and QR. The selectors PR and QR select the outputs from the ROMP and Q and the counter values P and Q.

The outputs from the selectors PR and QR are added to the adder 2
It is added at 65 and input to the mod 1118 circuit.
An output from the mod 1118 circuit is input to an absolute address conversion circuit 290, and an absolute address is calculated by this circuit, and the calculated address is supplied to the internal address bus 2.

Also, the P counter 261 and the Q counter 26
The counter value from 2 is input to the selector PQ via the decoder P and the decoder Q, respectively, and the selector PQ outputs PPQQ as a PQ parity address.

Next, the operation of each selector and the mod 1118 circuit will be described. Selector PA (home) B (when error correction of PECC is performed) Selector QA (home) B (when error correction of QCCC is performed) Selector PR A (home) B (QS43-45) Selector QR A (home) B ( PS26 & QCCC
QS # 43 to 45 & PECC) mod 1118 circuit When QS <43 & PS <26, the circuit is enabled and performs the operation of mod 1118.

In the above case, the addresses shown in FIGS. 11 and 12 can be generated.

Under the control of the P counter 261 and the Q counter 262, addresses for syndrome calculation, ECC addition, error correction execution, flag writing, and reading are generated. PPQQ is used to calculate a syndrome with parity set to 0 when ECC is generated.
24, 25 (at PENC), QC = 43, 44 (QEN
C) becomes active.

PPQQF1 is the CD-IFORM1 E
To support CC, PS = 0,25 (Q
ECC), and becomes active when QS = 0, 1 (PEECC). This is used when accessing the header. That is, in the syndrome calculation at the time of encoding and decoding in the CD-I format, the address generation circuit 250
This PPQQF1 is output from the address generation circuit 250 when an address of data corresponding to a header portion is generated. Then, the gate 10 of the Sy calculation circuit 211
L, 10H, 20L, 20H are disabled and 0 is S
This is loaded into the y-calculation circuit 211 to perform syndrome calculation. With this configuration, the sequencer and the ECC signal processing unit can be made completely the same for CD-ROM and CD-I. Also, when an error is corrected in the CD-I format, it is determined that there is an error in the header portion, and when the error is to be corrected, the PPQQF
1 is output, and writing to the RAM 10 is inhibited by this signal. With this configuration, the header portion is regarded as zero at the time of CD-I, and erroneous correction of the header is prevented.

(3) EDC addition / error detection circuit (30
0) (see FIGS. 15 and 16)

The error correction code (EDC) uses a CRC code. This EDC addition / error detection circuit 30
0 can be configured as shown in FIGS. 15 and 16, for example.

The addition of the EDC code is performed by the circuit shown in FIG. The data read from the RAM 10 is input to the data buffer circuit 301. Then, data is sent from the data buffer circuit 301 to the CRC operation circuit 302 via the switch S2. The CRC operation circuit adds an EDC code composed of a cyclic code to the data based on the generator polynomial, and outputs the data through a gate. The timing of each circuit described above is controlled by the timing control circuit 303.

As described above, in the EDC generation circuit shown in FIG. 15, EDC addition of data is executed.

An error can be detected depending on whether the data code read from the RAM 10 is divisible by the generator polynomial. This process can be performed by the circuit shown in FIG. That is, the data read from the RAM 10 is input to the data buffer circuit 301 and the CRC operation circuit 302. An error is detected by the CRC operation circuit 302 and the remainder check circuit 304 based on the generator polynomial depending on whether or not the data includes a cyclic code. The timing of each circuit described above is controlled by the timing control circuit 305.

As can be seen from FIG. 15 and FIG.
The C generation and error detection circuit can also serve as the CRC operation circuit 301 and the data buffer circuit 302.

The EDC addition / error detection circuit 300 is controlled by the sequencer 350, and the address for reading and writing data from the RAM 10 is EDC.
/ Sector address generation circuit 450. That is, since the address generation of the EDC addition / error detection circuit 300 and the sector logic circuit 400 do not overlap each other, the configuration is such that the address generation circuit is commonly used and the circuit scale is reduced. The configuration of EDC / sector address generation circuit 450 will be described later.

(4) Sector logic circuit 400 (FIG. 1)
7 to 20)

Before describing a specific embodiment of the sector logic circuit 400, features of the circuit in this embodiment will be described.

The sector logic circuit 400 in this embodiment is configured to write a sync pattern at a predetermined position in the RAM 10 to add a sync pattern to data transferred from a host or the like. The circuit of this embodiment is configured so that it is possible to select whether or not to add a header or a subheader, as described above.

In the first block, the header time is added with the initial value written by the system controller, and thereafter, the time is automatically incremented. In the circuit of this embodiment, the mode byte of the header can be automatically generated, and if the system controller gives a start / end instruction, the mode byte of the link block, the first line block, the second line block, the first run out block, and the second run out block is generated. It is configured to be added. In the case of the CD-ROM mode 1, a function of writing a predetermined position zero in the RAM 10 to eight bytes (zero field) of all zeros is provided, and a circuit for generating this zero is shared with a circuit for generating a sync pattern. ing.

By providing the function of setting the address generation to an appropriate initial value and the function of incrementing it,
It is used in common with the address generator 450 for EDC generation / error detection. With such a configuration, the format of the write block can be constructed in the RAM 10 with less burden on the system controller and the host. Also, the circuit scale can be reduced.

Further, the RAM input from the CD drive
After the error correction process and the error detection process are completed for the data stored in the memory 10, the header and the subheader are read from the RAM 10 and written in a register that can be read by the system controller.

It is configured such that the audio flag determines which of the subheader to be selected before and after the subheader written twice is determined as follows.

When the previous byte flag is 0 → previous byte data When the previous byte flag is 1 → post byte data With the above configuration, the system controller can know the corrected header and subheader values. The system controller can know the value of the subheader which is more certain.

Next, the sector logic circuit 400 according to this embodiment will be further described.

The sector logic circuit 400 is a RAM 10
A portion corresponding to the header and the subheader of the data taken in the data is read through the internal data bus 1 and taken into the header reading register 420 and the subheader reading register 415. Then, the read header and subheader are output to an internal syscon data bus 1A to a syscon interface 500 for interfacing with a syscon for controlling a system of this integrated circuit provided outside, which will be described later.

The sector logic circuit 400 adds the data written in the header write register 420 and the sub-header write register 410 by the system controller to the data in the RAM 10 via the internal data bus 1. At this time, the address of the RAM 10 is specified by applying the address generated by the address generation circuit 450 of the EDC / sector logic to the RAM interface 880 via the internal address bus 2.

The header time of the header write register 420 is determined by the header time incrementer circuit 440.
Is automatically incremented.

Furthermore, the sector logic circuit 400 is provided with an audio flag check circuit 430,
The audio flag transmitted from the DA interface 100 is checked, and the result is output to the subheader read register 415.

The operation of each of the above circuits is controlled by the control logic 445.

Next, the operation of each circuit will be described with reference to FIGS.
0 will be described. FIG. 18 shows a header read register 420, a header write register 425, and a header time incrementer circuit 440 for generating and detecting a header.
FIG. 19 shows a sub-header write register 410 and a sub-header read register 415.
FIG. 20 shows a control logic.

First, the operation at the time of reading (at the time of decoding) will be described. When reading, the sector logic is ECC, E
When DC decoding is completed, the header subheader is stored in RAM1.
It is read from 0 and stored in a register readable by the system controller.

The read sequence will be described.
A start pulse from the sequencer 350 is input to the register , and the start pulse causes the control logic 445 to operate.
Starts. The control logic 445 includes a counter 446 and a decoder 447.
In accordance with E and FORM, a control signal of the address generation circuit 450, a RAM access request signal (RQ), and a load signal for storing read data in a register are sequentially generated to control reading of the header and subheader.
When the reading is completed, the control logic 448 returns an end pulse to the sequencer 350, and enters an idle state.

To explain the reading of the subheader, each byte is written twice in the subheader, and one of the two is selected by using the audio flag and the register 0 is selected.
Store to ~ 5. Then, the audio flag, bits 5 and 8, and the word number of the header / subheader are input from the CD-DA interface 100, and the values of the audio flag corresponding to each byte of the header / subheader are held in registers 0-5.

Bits 5 and 8 automatically detect the mode and form, and are stored in registers 0, 2, and 4. The contents of the registers 0 to 5 are transferred to the register FLG 411 by block synchronization. That is, in the block-by-block pipeline, the processing is shifted from the buffering stage to the sector processing stage.

One of the twice-written subheaders is selected by the audio flag, and the read register 415, the registers RC1F, RSMD, RCNO, R
Stored in FNO. Both the preceding byte and the succeeding byte are read from the RAM 10. If the previous flag is 0, the previous byte is stored in the register. If the previous flag is 1, the subsequent byte is stored in the register. Table 2 shows the relationship between the flags and the bytes stored in the registers.

[0165]

[Table 2]

In the CD-ROM mode, the subheader is not read.

The audio flag will now be described.
From FLG, the system controller can read the audio flag of the header and subheader. Also, for the sub-header part, AND of the front and rear flags is taken.

The reading of the header will be described. In response to a header load signal from the control logic 445, each of the registers RMOD, RBLK,
The header is stored in RSEC and RMIN.

Explaining the auto mode and the form, when reading a CD-ROM, it is determined whether the read block is MODE1 or MODE0 or 2 by bit 0 (W1B8) in the mode byte of the header. CD-I
At the time of reading, it is determined from the bit 5 (W3B5, W5B5) in the submode byte of the subheader section whether the read sector is FORM1 or FORM2. Also in this determination, selection before and after is performed using the audio flag. These determination results are sent to the system controller interface 500 as auto mode and form signals, and are selected by selecting the mode and form set by the system controller. Then, it is used to determine the mode and form.

The operation at the time of writing (at the time of encoding) will be described. At the time of writing, prior to generation of ECC and EDC, an operation of adding a sync pattern, header, subheader, and zero field to user data in the RAM 10 is performed. .

Describing the additional sequence, the control logic is started by a start pulse from the sequencer. The control unit sequentially outputs a control signal of the address generation circuit 450, a RAM access request signal (RQ), and a gate control signal of a write register. Then, when the addition is completed, the control logic 445 returns an end pulse to the sequencer and enters the idle state.

Explaining the addition of a sync pattern,
The sync pattern generated by the sync pattern generation circuit 435 is added to a predetermined position in the RAM 10 according to the format of the block.

Explaining the addition of the header and the subheader, the header and the subheader are added at predetermined positions according to the format of the block. Whether this header or subheader is added is selected by a system control signal. The original header and subheader are DFFMO
D, BLK, SEC, MIN, DFFC1F, SMD,
Written in the CNO and FNO by the syscon respectively. The header and the sub-header are the registers WMOD, WBLK, and WRLK of the write registers 410 and 425, respectively.
WSEC, WMIN, registers WC1F, WSMD, W
After being transferred to CNO and WFNO in synchronization with the block,
The data is written to the RAM 10. In the mode in which the subheader is not added, the subheader is read from the data in the RAM 10 and stored in the form bit register AFORM.
It has a function to determine the autoform at the time of encoding.

Explaining the addition of the zero field, in the case of the block of CD-ROM MODE1, zero is written at a predetermined position. The circuit for generating the zero uses the sync pattern generation circuit 435.

Increment of the header time and generation of the header mode byte The operation of the procedure for incrementing the header time will be described. The system control is performed by the D flip-flops DFFBLK, SEC, and MIN as latches (FIG. 18).
Write the initial value for each. And it does not increment at the time of pre-encoding. Whether or not pre-encoding is performed is given as a system control signal.

Then, a start pulse is given from the sequencer in synchronization with the block synchronization signal. Under the control of the control logic in the increment circuit 440, as shown in Table 3, the value of the D flip-flop (DEF) is changed to each of the registers WBLK,
Transferred to WSEC, WMIN.

[0177]

[Table 3]

In the next block, the time is as shown in the following Table 4.
Is incremented by the increment circuit 440 in synchronization with the block synchronization signal.

[0179]

[Table 4]

The operation of the procedure for generating a header mode byte will be described. Then, when the system controller gives a start / end instruction, the system control signal causes a link block (LINKBLOCK), a first run-in block (1'stRUNINBLOCK), a second run-in block (2'ndRUNINBLOCK), and a user data block (USERDATABLOCK). , First
Run-out block (1'stRUNOUTBLOC
K), 2nd run-out block (2'ndRUNOUT
BLOCK). Then, a MODE BAYTE (corresponding to the Orange Book) corresponding to these blocks is generated by the mode byte generating circuit 436.

(4) EDC / Sector Address Generation Circuit (See FIG. 21) As described above, this address generation circuit 450 has a function of setting an appropriate initial value and a function of incrementing the EDC, and an EDC addition / error detection circuit. 300 and an address generator of the sector logic circuit 400. Hereinafter, description will be made with reference to FIG.

The control signal from the sector logic 400 and the control signal from the sequencer 350 are supplied to the initial value generator 45, respectively.
6 and a counter 457. An appropriate initial value is loaded into counter 457. The output of the counter 457 is provided to the decoder 458 and the absolute address generator 45. The form mode is input to the decoder 458. The sync pattern generation circuit 46 from the decoder 458 via the LAST signal and the D flip-flop 462
1 to the sync pattern generation circuit 461
Output a sync pattern.

The absolute address output from absolute address generator 459 is output to internal address bus 2 via D flip-flop 460. Then, if the counter (mod 1:70) is incremented after accessing the RAM 10, an address is generated.

(5) Sequencer

FIG. 22 is a flowchart showing the operation of sequencer 350. The sequencer 350 follows the flowchart, and the ECC addition / error correction circuit 200, ED
C addition / error detection circuit 300, sector logic circuit 4
00 and the EDC / sector address generation circuit 450. In FIG. 22, H is a header, and R is ED.
C and P indicate PECC, and Q indicates QECC.

(6) Host Interface Circuit (See FIG. 23) Before describing a specific embodiment of the host interface circuit 600 of this embodiment, the features of the circuit in this embodiment will be described.

The host interface circuit in this embodiment is configured so that a block connected to a high-speed host bus in one chip is controlled by a clock faster than a system clock.

The circuit in this embodiment is configured not to directly output a signal from this block to a block operating with a system clock, but to set / clear a register or the like in synchronization with the system clock. . Further, a signal from a block operating with a system clock is configured to detect a change point with a fast clock and take in the block.

Furthermore, the register file 604 stores the counter 6
05 to form a FIFO and register file 60
4, the handshake between RAM access and direct memory access controller (DMAC) is switched.

When the data transfer from the host is completed, the register 606 stores the value of the counter 605 to write the remaining data in the register file 604 to the RAM 10 and has a function of comparing the value 607.

With the above configuration, it is possible to cope with a high-speed host and execute data transfer with the host at high speed.

A block operating with a fast clock and a block operating with a slow clock can be integrated on one chip. Also, a slow RAM can be shared.

Further, the use efficiency of the host bus is improved.
Accurate transfer word count can be secured.

The host interface circuit 600 of this embodiment will be described with reference to FIG. In this embodiment, the clock operates at three times the system clock.

The host interface circuit 600 is connected to the host bus by the host bus interface unit 606, and data transferred from the host is transmitted via the host bus interface unit 606, the internal host data bus 611, and the selector 603 with a high-speed clock. And stored in the register file 604. The data from the host stored in the register file 604 is stored in the control circuit 60.
At 2, the data is transferred from the internal data bus 1 to each block in synchronization with the system clock of the integrated circuit. Each block is set or cleared by the register 606 so as to synchronize the system clock, and is supplied to each block.
Data transferred to the host is stored in the register file 604 from the internal data bus 1 via the selector 603. The data from each block stored in the register file 604 is supplied from the internal host data bus 6111 by a high-speed clock under the control of the control circuit 602.
From the host bus interface unit 606 to the host bus.

The start address and transfer direction are set in the A counter 601 by the host. And
The control circuit 602 increments the counter 605 each time data is written to the register file 604 or data is read from the register file 604. The value of the counter 603 is sent from the decoder 608 to the control circuit 602. The value of the counter 605 is given to the address terminal of the register file 604, and the counter 605 and the register file 604 constitute a FIFO.

The value of the counter 605 is stored in the register 609 when a signal (DONE) indicating the last data is input while data is being transferred from the host, and the counter 605 is cleared. Is done. Then, the value of the register 609 and the value of the counter 605 are compared by the comparator 610.

A signal (RQ) output from the control circuit 602 to each block is taken into a register RQ 606 and used to synchronize with the system clock.
6 is set or cleared. Further, a signal from each block synchronized with the system clock is detected by a falling detection circuit 607 which detects a change point with a high-speed clock.

The operation of transferring data from the integrated circuit to the host in this embodiment will be described. (A) The host sets the start address and the transfer direction in the A counter 601. (B) Then start the DMA. (C) The control circuit 602 outputs (RQ) requesting access to the RAM 10. (D) Subsequently, when access to the RAM 10 is permitted,
The address is output from the gate GA, and B
The data is written to the register file 604 through the above path. (E) The A counter 601 and the counter 605 are incremented. (F) the counter 605 overflows, ie
The above operations (c), (d), and (e) are repeated until the register file 604 becomes full. (G) The host bus interface unit 606 allows the DM
Register file 6 while handshake with AC
Open the gate GH to output the data 04 to the host bus. (H) Increment the counter 605. (J) The above operations (g) and (h) are repeated until the counter 605 overflows, that is, the register file 604 becomes empty. (K) The processes from (c) to (j) are performed until a signal (DONE) indicating the last data is input from the DMAC during execution of (g), and (g) is being executed. When the DONE signal is input to the terminal, the processing is terminated.

An operation of transferring data from the host to the integrated circuit in this embodiment will be described. (A) The host sets the start address and the transfer direction in the A counter 601. (B) Then start the DMA. (C) The host bus interface unit 606 sends the DM
The host bus data is written into the register file 604 through the A path of the selector 603 while performing handshake with the AC. (D) The counter 605 is incremented. (E) the counter 605 overflows, ie
The above operations (c) and (d) are repeated until the register file 604 becomes full. (F) The control circuit 602 outputs RQ. (G) Subsequently, when access to the RAM 10 is permitted,
The address is output from the gate GA and the gate G
D is opened, and the contents of the register file 604 are written to the RAM 10 via the data bus. (H) The A counter 601 and the counter 605 are incremented. (I) The operations (f) to (h) are repeated until the counter 605 overflows, that is, the register file 604 becomes empty. (J) The processes from (c) to (i) are performed until a signal (DONE) indicating the last data is input from the DMAC during the execution of (c), and the process of (c) is being executed. When the DONE signal is input to the counter 6
Transfer the value of 05 to the register and clear the counter. (K) Until the value of the register and the value of the counter are the same,
(F) Repeat (g) and (h).

(7) Communication function block (see FIG. 24)

The communication function block 700 connects the system interface circuit 500 for interfacing with the system controller and the host interface circuit 600, and exchanges commands and indications between the host system.

The communication function block 700 includes an indication register file 710 and a command register file 720. 16-bit data is sent from the internal host data bus to the command register file 720, and the selector 721 is transmitted from the command register file 720 in 8-bit units. Sent to And the selector 72
1 through the gate 722 to the internal system data bus 7
Data is sent to 40.

The internal system data buses 740 to 8
Bit is directly stored in the indication register file 71
The data is sent to the indication register file 710 after being delayed to 0 and 8 bits by the flip-flop 711, respectively. Then, 16-bit data is sent from the indication register file 710 to the internal host data bus 730 via the gate 712.

A header write or read signal is input to the counter H 750, an output from the counter 750 is input to a header interrupt generation circuit 751, and a header interrupt request signal is output from the generation circuit 751.

A subheader write or read signal is input to the counter S760, an output from the counter 760 is input to the subheader interrupt generation circuit 761, and a subheader interrupt request signal is output from the generation circuit 761.

(8) Arbitration logic circuit (see FIGS. 25 and 27)

This arbitration logic circuit 80
0 is the ECC addition / error correction circuit 200, EDC addition / detection circuit 300, sector logic circuit 400, CD
-DA interface circuit 100, host interface circuit 600, serial port circuit 900, RAM
The inter-page DMA logic circuit 850 is connected to the external RAM 10
Used when accessing.

Of the above circuits, the worst five circuits are RAM
10 may be requested at the same time. When these RAM access requests are generated, the arbitration logic circuit 800 gives priority to the RAM access request with the highest priority, and causes other requesting circuits to wait until the order comes.

The features of the arbitration circuit in this embodiment will be described first. In the circuit of this embodiment, a plurality of blocks used by this RAM in one chip operate independently of each other, and
When an access request to M is generated, an access request signal is issued to the arbitration logic, and if permission is obtained, the access is actually performed.

After the arbitration logic returns a permission signal to each section, actual RAM access is performed one clock cycle later.

The arbitration logic is configured as an independent block for each unit and cascade-connected in priority order.

Each block independent block in the arbitration logic can be enabled and disabled.

With the above configuration, the timing adjustment of each block is simplified. Also, the RAM can be used without conflicting accesses.

Further, the skew of the read, write, and address enable signals of each block is reduced.

Further, the circuit design can be simplified. It is easy to cope with an increase or decrease in the number of blocks. Testing and debugging are easy.

FIG. 25 is a block diagram showing a general circuit for requesting an arbitration logic circuit, FIG. 26 is a timing chart thereof, and FIG. 27 is a specific circuit diagram of the arbitration logic circuit.

As shown in FIG. 25, each block receives a read or write request (RQ
R, RQW) to the arbitration logic circuit 800
To send to. The arbitration logic circuit 800 is an EX that permits execution of a read or write request from a block with the highest priority.
Give a signal. Then, when this EX signal is given to control section 810, control section 810 gives control signals to data processing section 811 and address generation section 815, respectively. At the time of writing, a write enable signal WRE is supplied to the gate G, and data is supplied from the data processing unit 811 to the internal data bus 1 via the flip-flop 813. When reading, read enable signal R
DE is applied to register 812, and data is applied to register 812 from internal data bus 1. The address data of the internal address bus 2 is given from the address generator 815 via the flip-flop 814 and the gate, and the block and the RAM 10 are accessed.

As shown in FIG. 26, a read or write request (RQR,
RQW) is not waited, and is executed as an EX that permits the execution to be performed as it is, via a requesting block, the block and the RAM 10 being accessed, and data and addresses are updated. or,
EX waits for requests below the following priority
When a low-priority block is requested, if a WAIT (EX) is applied, R
Execution of access to the AM 10 is awaited, and when WAIT is exhausted, EX that permits access to the block is executed.
A signal is output and access is started.

The operation of arbitration logic circuit 800 will be described with reference to FIG. Read or write request (RQ) from the block with the highest priority
R1, RQW1) are executed without being waited, and are executed as EX1 permitting the execution as it is, via a request source block.
10 are accessed.

EX1 is a WAIT signal for the next lower priority request. When PQR2 is requested, if WAIT (EX1) is applied, RQR2 is taken into DFF1, and when WAIT is exhausted, DRQ1 is output.
While being transferred to FF2, DFF1 is cleared if the RQR has not arrived at that time, EX2 is returned to the request source, and a WAIT is generated in the next stage and below. WAIT
If (EX1) is not applied, in the next clock cycle taken into DFF1, the data is transferred to DFF2, EX2 is returned, and a WAIT is generated in the next stage and below.
As long as the gate delay permits, the blocks A within the dotted line can be cascaded. The EN signal of each stage can enable and disable each stage independently and is used at the time of TEST.

(9) DMA logic between RAM pages (see FIG. 28)

During the read operation, while the read operation is continued, A
When it becomes necessary to perform DPCM reproduction, or when it is desired to write data that has been subjected to ADPCM encoding during write / read to a disk without passing through a host,
Data transfer between the I / O buffer and the ADPCM buffer is performed by the inter-page DMA. The configuration and operation of the RAM inter-page DMA logic circuit 850 will be described with reference to FIG.

The I / O buffer page, ADPCM page, transfer direction are determined, and the word counter is cleared.

At the time of reading, the selector 851 is switched, the page switching address of the transfer source is generated by the absolute address generator 854, and the data is taken into the register 852.

At the time of writing, the selector 851 is switched, the switching address is generated in the transfer destination page by the absolute address generator 854, the gate GD is opened, and the data of the register 852 is written in the RAM 10.

Then, the address counter 853 is incremented. The above operation is repeated until the transfer of one page is completed. The above operations are controlled by the control circuit 855.

The circuit according to the embodiment of the present invention is constructed as described above. However, the CD-DA interface circuit 100, the arbitration logic circuit 800, and the RA
The external RAM 10 is used as follows using the DMA logic circuit 850 between M pages and the like. Hereinafter, how to use the RAM will be described.

In this embodiment, the RAM 10 is divided into pages as shown in FIG.
ADPCM pages are allocated, and data is transferred between the I / O buffer page and the ADPCM page.

This RAM 10 stores one page in a CD-RO
An audio flag information EDB (block not performing error correction) which is taken wider than the data format defined by M and sent to the host, or is obtained at the time of error correction, and is used in the next error correction. (A block to be executed).

The ADPCM buffer in the external RAM 10 is configured to be completely freely used through the host interface or the serial port even when reading the read data (RDATA) or writing the write data (WDATA).

With the above configuration, blocks read out from the disk, which need not be sent to the host and are directly used for ADPCM reproduction or the like, can be read at high speed.
It can be passed to the DPCM decoder. Further, the RAM can be used efficiently.

[0233] ADPCM encoding can be performed while writing and reading data to and from a disk, and the range of applications is expanded.

A method for generating a page will be described. The page is generated at the time of encoding / decoding as follows.

The generation of the I / O buffer page at the time of encoding / decoding is as follows. Page counter value PCNT CD-DA page value PCDDA

The value of the page (ECC, EDC, sector logic page) is PECC. At the time of encoding PCDDA = PCNT, PECC = (PCNT + 3) mod4 At the time of decoding PCDDA = (PCNT + 3) mod4, PECC = PCNT However, PCNT is 0-3.

The page counter of the CD-DA interface circuit is a 2-bit counter which is incremented every block synchronization to generate PCNT. PCDDA and PECC are generated by the decoder in accordance with the encoding / decoding.

The pipeline processing of the I / O buffer page will be described.
The first data is transferred from the host to page 0 of the / O buffer.

Next, a sync pattern, header, and subheader are added to this data by sector logic. Further, the ECC addition / error correction circuit 200 generates an ECC code. Finally, the EDC is added by the EDC addition / error detection circuit 300. Up to this point, pre-encoding has been performed, and serial transfer of WDATA through the CD-DA interface circuit 100 has not yet been performed. Until the pre-encoding is completed, at least another page of write data is transferred to the host. The block synchronization is achieved by the SOE signal received by the CD-DA interface, the page counter is incremented, and the word counter is reset. Then, the data of page 0 is output serially, and the data of page 1 is subjected to HWR (at the time of sector logic processing and writing), ECC (ECC addition /
Error correction circuit processing) and EDC (EDC addition / error detection circuit processing) are performed.

Thereafter, the word counter synchronizes the blocks and repeats the processing.

Next, a sync pattern, a header, and a subheader are added to this data by sector logic. Further, the ECC addition / error correction circuit 200 generates an ECC code. Finally, the EDC is added by the EDC addition / error detection circuit 300. Up to this point, pre-encoding has been performed, and serial transfer of WDATA through the CD-DA interface circuit 100 has not yet been performed. Moreover, until the pre-encoding is completed, keep transferring at least another page of write data to the host. The block synchronization is achieved by the SOE signal received by the CD-DA interface, the page counter is incremented, and the word counter is reset. Then, the data of page 0 is output serially, and the data of page 1 is subjected to HWR (at the time of sector logic processing and writing), ECC (ECC addition /
Error correction circuit processing) and EDC (EDC addition / error detection circuit processing) are performed.

FIGS. 29 and 30 are schematic diagrams showing the above-described processing of the RAM 10 in chronological order. FIG. 29 shows the case of encoding, and FIG. 30 shows the case of decoding. As shown in FIG. 29, at the time of encoding, data is transferred from the host to the I / O buffer 0, for example, every 13 msec in this embodiment, and the header is written, and the ECC and EDC generation processes are performed. During the transfer, data is transferred from the host to the I / O buffer 1. When the write data of the I / O buffer 0 is output serially, the I / O buffer 1 performs a pipeline process so that a header is written and ECC and EDC are generated. FIG.
As indicated by 0, pipeline processing is also performed at the time of decoding. FIGS. 31 to 36 are flowcharts showing the operation of each of the circuits described above. FIG. 31 and FIG.
2 shows the operation of the sector block circuit, FIGS. 33 and 34 show the operation of the EDC addition / error detection circuit, and FIGS. 35 and 36.
Shows the operation of the ECC addition / error correction circuit.

[0243]

As described above, according to the present invention, of the data read from the optical disk, the host C
Blocks need to send the PU is used name rather and the ADPCM such as reproduction is possible transfer to the ADPCM decoder at high speed, ADPCM decoder own is not necessary to have a buffer memory. Further, according to the present invention, the storage means can be used efficiently. Furthermore, while writing and reading to and from an optical disc, reproduction of ADPCM and ADPCM
Encoding is possible, and the range of applications is expanded.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing an overall configuration of a signal processing semiconductor integrated circuit to which the present invention is applied.

FIG. 2 is a block diagram showing an overall configuration of a signal processing semiconductor integrated circuit to which the present invention is applied;

FIG. 3 is a block diagram showing details of a CD-DA interface used in the present invention.

FIG. 4 is a schematic diagram showing a paging mode of an external memory in which the present invention is used.

FIG. 5 is a schematic diagram showing a data format of an IO buffer.

FIG. 6 is a block diagram showing an overall configuration of an ECC addition / error correction circuit used in the present invention.

FIG. 7 is a block diagram showing an ECC signal processing unit used in the present invention.

FIG. 8 is a flowchart showing an error correction operation.

FIG. 9 is a flowchart showing a decoding operation at the time of error correction.

FIG. 10 is a flowchart showing a decoding operation at the time of error correction.

FIG. 11 is a schematic diagram showing assignment of Q word addresses.

FIG. 12 is a schematic diagram showing P word allocation.

FIG. 13 is a schematic diagram showing a Q address to be referred at the time of PECC.

FIG. 14 is a block diagram showing an ECC address generation circuit.

FIG. 15 is an EDC generation circuit of an EDC addition / error detection circuit used in the present invention.

FIG. 16 shows an error detection circuit of the EDC addition / error detection circuit used in the present invention.

FIG. 17 is a block diagram showing an overall configuration of a sector logic circuit used in the present invention.

FIG. 18 is a block diagram showing a circuit for generating and detecting a header.

FIG. 19 is a block diagram showing a circuit for generating and detecting a subheader.

FIG. 20 is a block diagram showing a control unit of the sector logic.

FIG. 21 is a block diagram showing an address generation circuit for generating an address of an EDC and a sector logic circuit used in the present invention.

FIG. 22 is a flowchart showing the operation of the sequencer.

FIG. 23 is a block diagram showing a host interface circuit used in the present invention.

FIG. 24 is a block diagram showing communication function blocks used in the present invention.

FIG. 25 is a general block diagram of a circuit for issuing a request request to an arbitration block circuit used in the present invention.

26 is a timing chart of the block diagram shown in FIG. 25.

FIG. 27 is a specific circuit diagram of an arbitration logic circuit.

FIG. 28 shows a DMA between RAM pages used in the present invention.
FIG. 3 is a block diagram illustrating a logic circuit.

FIG. 29 is a schematic diagram showing the processing of the RAM at the time of encoding in a time-series manner.

FIG. 30 is a schematic diagram showing the processing of the RAM at the time of decoding in chronological order.

FIG. 31 is a flowchart showing an operation of the sector logic circuit.

FIG. 32 is a flowchart showing an operation of the sector logic circuit.

FIG. 33 is a flowchart showing an EDC generation operation.

FIG. 34 is a flowchart showing an EDC generation operation.

FIG. 35 is a flowchart showing an ECC decoding operation.

FIG. 36 is a flowchart showing an ECC decoding operation.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 External RAM 100 CD-DA interface circuit 200 ECC addition / error correction circuit 300 EDC addition / error detection circuit 350 Sequencer 400 Sector logic circuit 450 EDC / sector address generation circuit 500 Syscon interface 600 Host interface circuit 700 Communication function block circuit 800 Arbitration Logic circuit 850 RAM page-to-page DMA logic circuit 900 serial port

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-2-210666 (JP, A) JP-A-58-175187 (JP, A) JP-A-59-35262 (JP, A) JP-A-63-1988 140464 (JP, A) JP-A-2-68778 (JP, A) JP-A-60-201576 (JP, A) JP-A-63-298471 (JP, A) (58) Fields investigated (Int. ⁷ , DB name) G11B 20/10 G11B 20/18 G06F 13/38

Claims (3)

(57) [Claims] 1. A read data read from an optical disk.
Data and write data to be written to the optical disk
A signal processing method for an optical disc to be taken into the means,
Dividing the storage means into a plurality of page units, and
Exchange data with host CPU and optical disk
Buffer page and ADPCM data to perform
Allocate to ADPCM buffer page to be stored, and
The I / O buffer page and the ADPCM buffer page
Data transfer between the I / O buffer
When encoding, data from the external host CPU is used.
Import and transfer from ADPCM buffer page
Holds ADPCM data to be written to the sent optical disk
When decoding data from an optical disc,
To host CPU or ADPCM buffer page
Holds the data to be sent and reads while reading the optical disc.
ADPCM decoding is required while continuing the read operation
Occurs during reading of data for write operation
ADPCM encoded data passed through the host
If you want to write to an optical disk without performing
Between the O buffer page and the ADPCM buffer page.
A signal processing method for a write-once optical disc , comprising transferring data . 2. The one-page area is set wider than the data format specified in the optical disc, and audio flag information for indicating a block to be sent to the host CPU without performing error correction, in an extra area of the page, or 2. The signal processing method of a write-once optical disc according to claim 1, wherein a flag obtained at the time of error correction for a block for performing error correction and used for a next error correction is used as a writing area. 3. An ADPCM buffer for the storage means.
The host CPU reads the signal received by the storage means and writes the write data signal.
2. The signal processing method for a write-once optical disc according to claim 1, wherein the pages are allocated so that the pages can be freely used via an interface with the interface and a serial port.