JPH07230419A - Interruption control system - Google Patents

Abstract

PURPOSE:To efficiently arbitrate many interruption requests from plural peripheral devices by easily specifying the interruption factor of a peripheral device which makes the interruption request. CONSTITUTION:Interruption lines between the respective peripheral devices 2-4 and a main processor 1 are cascaded so that the main processor 1 is on the most upstream side; and the respective peripheral devices 2-4 are provided with shift register circuits 17, 21, and 25 which register the interruption priority levels of their own devices and bit sequences showing whether or not interruption requests are made in their own devices, and output the bits in the order of the priority in synchronism with the peripheral devices and shift control circuits 16, 20, and 24 which compare the bit sequences of their own devices with bit sequences from downstream peripheral devices, bit by bit, in order to detect a bit indicating a difference in priority, and sending the bit sequences of their devices up to the detected bit and the bit sequences of the higher- priority side from the detected bit to upstream sides; and the main processor 1 is provided with an interruption specification part 13 which discriminates whether or not an interruption request is made based on the bit sequences from the peripheral devices 2-4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt process for temporarily stopping a process being executed by a microprocessor and performing another process, and particularly to efficiently arbitrate a large number of interrupt requests. It relates to a preferred interrupt control system.

[0002]

2. Description of the Related Art A conventional technique relating to interrupt processing is disclosed in Japanese Patent Laid-Open No. 5-20234, for example. In this technique, an interrupt control circuit arbitrates each interrupt request for transmission and reception for an interrupt due to transmission / reception of a serial line, and outputs the interrupt request to a microprocessor. The microprocessor inputs the interrupt vector in the acknowledge cycle by the interrupt request.At this time, the communication line control circuit that issued the interrupt request sends the vector of each character for the interrupt request to the bus by the read instruction of the interrupt control circuit. Then, the microprocessor outputs this vector and the vector generated by the interrupt control circuit as an interrupt vector, and recognizes the interrupt factor. In this way, in the interrupt acknowledge cycle of the microprocessor, each character to be transmitted / received and the vector generated by the interrupt control circuit are put together so that the microprocessor can input as one vector. However, this conventional technique does not consider reducing the number of interrupts and dealing with complication of the arbitration circuit when there are many interrupt factors.

[0003]

The problem to be solved is that the conventional technique cannot deal with the reduction of the number of interrupts and the complication of the arbitration circuit when there are many interrupt factors. . An object of the present invention is to solve these problems of the prior art, facilitate identification of a peripheral device requesting an interrupt and an interrupt factor, and efficiently arbitrate a large number of interrupt requests from a plurality of peripheral devices. To provide an interrupt control system.

[0004]

In order to achieve the above object, the interrupt control system of the present invention comprises: (1) the interrupt line between each of the peripheral devices 2 to 4 and the main processing device 1 to Cascade connection with serial signal line as upstream,
Each of the peripheral devices 2 to 4 has a bit (“1”, a position at which a higher-order bit string indicating the priority of an interrupt given to the device itself and the presence / absence of each interrupt request in the device itself are associated with each other).
A shift register circuit 17, 21, 25 for registering a lower bit string indicated by "0") and sequentially outputting one bit at a time from the upper bits in synchronization with the peripheral devices 2 to 4, and the shift register circuit of the own device. The bit string from the and the bit string sent from the peripheral device downstream via the serial signal line are sequentially compared bit by bit from the upper bit, and the first bit indicating the difference in priority of both devices is detected, The shift control circuits 16 and 20 for sending the bit string from the shift register circuit on the device side up to this detection bit and the bit string on the device side having a higher priority from the detection bit upstream through the serial signal line. , 24 are provided, and the main processing unit 1 is provided with a peripheral device that receives an interrupt request and an interrupt request based on a bit string sent from an adjacent peripheral device via a serial signal line. The interrupt identification unit 13 for discriminating the contents
Is provided. (2) In the interrupt control system described in (1) above, each peripheral device 2 to 4
In addition, the priority of each interrupt request generated in the own device is arbitrated and the main processing device 1 and the shift register circuit 1 of the own device are arbitrated.
7, 21, 25 and interrupt request arbitration circuits 15, 19, 23 for notifying the shift control circuit are provided, and the shift control circuit 1
6, 20, and 24 are interrupt request arbitration circuits 15, 19, and 2.
When there is no interrupt request notification from 3, the bit string from the downstream peripheral device is directly sent to the upstream peripheral device without comparing with the bit string of the shift register circuit. (3) In the interrupt control system described in (2) above, each of the peripheral devices 2 to 2 is provided in the main processing unit 1.
4 receives the interrupt occurrence notifications from the interrupt request arbitration circuits 15, 19, and 23 in a wired-OR connection, and then receives the interrupt request arbitration circuits 15, 19, and 23 of each peripheral device to the shift register circuits 17, 21, and 25. It is characterized in that a latch signal generation circuit 11 for generating a latch signal for simultaneously permitting the interrupt request registration is provided. (4) In the interrupt control system described in (1) above, each of the peripheral devices 2 to 4 sends a bit string indicating the priority of its own device received from the upstream to the shift register circuit, and also gives priority to its own device. Of the peripheral device 2 adjacent to the main processing unit 1 is provided with the adder circuits 14, 18 and 22 for generating a bit string indicating the next priority of
It is characterized in that the bit string indicating the highest priority is received from the main processing device when the main processing device is activated. (5) In the interrupt control system described in (1) above, a clock used by the main processing device to synchronize the transmission of a bit string from each shift register circuit of each peripheral device and the comparison operation of each shift control circuit. Is provided, and a shift clock generation circuit 12 for generating and transmitting the signal to each peripheral device is provided.

[0005]

According to the present invention, the peripheral devices cascade-connected with the main processing device as the most upstream device collate while shifting the priority assigned to the own device and the priority of the downstream peripheral device by 1 bit. . Then, until the first bit indicating the difference in priority between the two devices is detected, the bit string on the device side is sent upstream, and after the first bit indicating the difference is detected, the bit on the higher priority side is detected. Send the bit string upstream. The main processing unit decodes the bit string sequentially sent bit by bit from the adjacent peripheral device, and determines the peripheral device that accepts the interrupt request and the interrupt request content. In addition, each peripheral device arbitrates the priority of each interrupt request that occurs in its own device and notifies the main processing device and the shift control circuit of its own device, and in the main processing device, it is particularly urgent to turn off the power. In response to the interrupt request, and in each peripheral device, when there is no interrupt request notification from the interrupt request arbitration circuit, the shift control circuit directly sends the bit string from the downstream peripheral device to the upstream peripheral device. Also, an interrupt request is simultaneously registered in each shift register circuit of each peripheral device by a latch signal from the latch signal generation circuit. In addition, each peripheral device adds, for example, “1” to the bit string indicating the priority of the own device received from the upstream by the adder circuit, and sends the bit string to the downstream so that the peripheral device adjacent to the main processing device has the highest priority. As the degree, the priority of each peripheral device is set. In addition, the shift clock generation circuit performs synchronous control of the transmission of the bit string of the shift register circuit of each peripheral device and synchronous control of the comparison operation of the shift control circuit from the main processing device.

[0006]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a configuration relating to the present invention of an interrupt control system of the present invention. In FIG. 1, reference numeral 1 is a main processing unit that includes a microprocessor and controls the entire system, and 2 to 4 are main processing units 1.
A peripheral device 10 controlled by the CPU arbitrates an interrupt request due to an interrupt factor in the main processing unit 1 and an interrupt request from the peripheral devices 2 to 4, and a microprocessor (CPU: C
A main interrupt request arbitration circuit that generates an interrupt request to the central processing unit), and 11 latches the interrupt request of each peripheral device 2-4 with respect to the interrupt request of each peripheral device 2-4. A latch signal generation circuit for generating a latch signal for causing the interrupt status latched by each of the peripheral devices 2 to 4;
A shift clock generation circuit that generates a shift clock for shifting serial data of the interrupt priority level of each of the peripheral devices 2 to 4, and 13 is an interrupt whose priority (priority) is determined based on the bit string sent from the peripheral device 2. Interrupt identification unit that determines the cause and interrupt priority level,
Reference numerals 14, 18, 22 are adder circuits which are cascade-connected to the main processing unit 1 and which add "1" to the interrupt priority level in each of the peripheral devices 2 to 4 and send it out downstream, 15, 19, 23.
Is an interrupt request arbitration circuit that arbitrates each interrupt request in each peripheral device 2 to 4 and notifies the main processing device 1 of this.
Reference numerals 21 and 25 indicate the interrupt factor in each peripheral device 2 to 4 and the interrupt priority level of each peripheral device 2 to 4 by the latch clock (LUT) by the latch signal generation circuit 11 of the main processing unit 1.
CHCK) and shift clock (SHI
FTCK) shifts the shift register circuit to the shift control circuit, 16, 20, 24 shifts out the data from each shift register circuit 17, 21, 25 to another series connected by a serial signal line. The shift control circuit sequentially compares the shift data of the peripheral device with the shift data of the peripheral device having a high priority. Via the shift control circuits 16, 20, and 24, the interrupt lines between the peripheral devices 2 to 4 and the main processing device 1 are cascade-connected with the main processing device 1 being the most upstream.

The operation of the present embodiment of the interrupt control system having such a configuration will be described below. First, when the power is turned on, a signal of GND (ground) level is input from the main processing unit 1 to the adder circuit 14 of the peripheral unit 2 and the interrupt priority level of the peripheral unit 2 (INTLEV1 = 00).
Will be decided. Next, in the adder circuit 14 of the peripheral device 2, the data “01” obtained by adding “+1” to the interrupt priority level “00” of the peripheral device 2 is input to the adder circuit 18 of the peripheral device 3 and Interrupt priority level (INTLE
V2 = 01) is determined. Similarly, in the adder circuit 18 of the peripheral device 3, the interrupt priority level “0
The data "10" obtained by adding "+1" to "1" is input to the adder circuit 22 of the peripheral device 4, and the interrupt priority level (INTLEV3 = 10) of the peripheral device 4 is determined. In this way, when the power is turned on, the interrupt priority level of each peripheral device 2 to 4 connected in series through the adder circuits 14, 18, and 22 is determined as a higher priority level upstream.

Next, an interrupt request (I
NTREQ 11-18, 21-28, 31-38), in each peripheral device 2-4, the interrupt request arbitration circuit 15, 19, 23 sends an interrupt request signal (INTRQ) to the main processing unit 1. Is output. The interrupt request signals are wired-ORed and input to the interrupt request arbitration circuit 10 and the latch signal generation circuit 11 of the main processing unit 1. In the main processing unit 1, the interrupt request arbitration circuit 10 receives the interrupt request signal (INTRQ) from the peripheral devices 2 to 4.
Then, an OR operation is performed with the interrupt request (IREQ1 to n) in the main processing unit 1 to output the interrupt request to the CPU. Also,
Interrupt request (INTRQ) in the latch signal generation circuit 11
Generates a latch signal of an interrupt factor to the shift register circuits 17 and 2 for each of the peripheral devices 2 to 4.
1 and 25 are interrupt factors in the peripheral devices 2 to 4 and interrupt priority levels (“00”,
"01", "10") are latched. Then, the shift clock generation circuit 12 of the main processing unit 1 gives a shift clock to the shift register circuits 17, 21, and 25 of the peripheral devices 2 to 4, and the shift control circuits 16, 20, and 24
The shift data (SHIFTDT1 to 3) connected in series are sequentially compared for each of the peripheral devices 2 to 4. Details of the processing operation by the shift control circuits 16, 20, and 24 will be described with reference to FIG.

FIG. 2 is an explanatory diagram showing an operation example of the peripheral device in the interrupt control system of FIG. 1 according to the present invention. As shown in FIG. 2, the shift register circuits 17, 21 and 25 of the peripheral devices 2 to 4 have interrupt priority levels,
Latched in the order of interrupt factors. In the present example, the shift register circuit 17 includes “00” as a bit string indicating the interrupt priority level, “0101010001” as a bit string indicating the interrupt factor, and the shift register circuit 2
1 includes interrupt priority level “01” and interrupt factor “10”.
11110 ”, but the shift register circuit 25 stores the interrupt priority level“ 10 ”and the interrupt factor“ 0110110 ”.
1 ”is latched. The interrupt priority level “00” of the shift register circuit 17 indicates the highest priority, and the bit string “0101010001” indicating the interrupt factor indicates to the peripheral device 2 the interrupt request “INTREQ1 in FIG.
2, 14, 18 ”have occurred. Further, the interrupt priority level “01” of the shift register circuit 21 is
The bit string “10111010” indicating the second highest priority next to the peripheral device 2 and indicating the interrupt factor is sent to the peripheral device 3 by the interrupt request “INTREQ 21, 23 to 25, 2 in FIG.
7 ”has occurred. Similarly, the interrupt priority level “10” of the shift register circuit 25 is set to the peripheral device 3
The bit string “01
101101 ”indicates that the interrupt request“ INTREQ 32, 33, 35, 36, 38 ”in FIG. 1 is generated in the peripheral device 4.

In this state, first, the interrupt priority levels ("00", "01", "10") of the peripheral devices 2 to 4 are
The shift clock generation circuit 1 in the main processing unit 1 of FIG.
For each shift clock from 2, shift control circuits 16 and 2
It is sent as shift data to 0 and 24. This shift data is stored in the shift control circuit 1 of each peripheral device 2-4.
6, 20, and 24 are connected in series, and the shift control circuits 16, 20, and 24 sequentially compare the input shift data with the shift data of the peripheral device. If the interrupt priority of its own peripheral device is high, the shift control circuits 16, 20, 24 inhibit the input shift data (output prohibited), and if the interrupt priority of its own peripheral device is low, Inhibit the shift data of the shift register circuit in the peripheral device.

In this way, by shifting the shift data of each peripheral device 2-4, the interrupt priorities are compared,
Only the shift data of the peripheral device with high priority is valid. Then, finally, the shift data having the highest priority, that is, the shift data from the shift register circuit 17 of the peripheral device 2 in this example, is input from the peripheral device 2 to the interrupt identifying unit 13 of the main processing device 1. Will be. Then, the interrupt identifying unit 13 determines the peripheral device that executes the interrupt and the processing content from the received shift data, and the CPU
To notify.

As described above with reference to FIGS. 1 and 2, in the interrupt control system of this embodiment, the main processing unit and a plurality of peripheral units are connected by a serial I / F (interface). However, the main processing unit can grasp, at one time, which peripheral device and what kind of factor the interrupt has occurred with one interrupt request. As a result, it is possible to reduce the number of signal lines between the main processing device and the peripheral device and shorten the interrupt processing time for the interrupt request generated in the peripheral device. In addition, each peripheral device arbitrates the priority of each interrupt request generated in its own device and notifies the main processing device and the shift control circuit of its own device. As a result, the main processing unit can deal with an interrupt request that is particularly urgent, such as power-off. Further, in each peripheral device, the shift control circuit directly sends the bit string from the downstream peripheral device to the upstream peripheral device when there is no interrupt request notification from the interrupt request arbitration circuit, so that the processing speed can be increased. . In addition, each peripheral device causes the adder circuit to add “1” to the bit string indicating the priority of the device itself received from the upstream.
Add and send downstream. This makes it possible to easily set the priority of each peripheral device by setting the peripheral device adjacent to the main processing device as the highest priority.

The present invention is not limited to the embodiment described with reference to FIGS. 1 and 2, and various modifications can be made without departing from the scope of the invention. For example, in the present embodiment, a high priority is assigned in the order of the peripheral devices closest to the main processing device 1 (peripheral device 2 = “00”, peripheral device 3 = “01”, peripheral device 4 = “10”). However, even if the peripheral device 3 is set to “10” and the peripheral device 4 is set to “01”, since the shift data from the peripheral device 4 is sent from the peripheral device 3 to the peripheral device 2, finally the main processing device There is no change in the shift data sent to 1. That is,
In the present invention, since the interrupt factor data of the peripheral device having a high priority is always input to the main processing device, the series connection of shift data and the series connection of the interrupt priority level can be freely combined.

[0014]

According to the present invention, it is easy to identify the peripheral device that is requesting an interrupt and the interrupt factor, the number of interrupts can be reduced, and the arbitration circuit becomes complicated when the number of interrupt factors is large. Therefore, it is possible to efficiently arbitrate a large number of interrupt requests from a plurality of peripheral devices.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a configuration according to the present invention of an interrupt control system of the present invention.

FIG. 2 is an explanatory diagram showing an operation example according to the present invention of a peripheral device in the interrupt control system of FIG.

[Explanation of symbols]

 1 Main Processing Units 2 to 4 Peripheral Devices 10 Main Interrupt Request Arbitration Circuit 11 Latch Signal Generation Circuit 12 Shift Clock Generation Circuit 13 Interrupt Identification Unit 14, 18, 22 Adder Circuits 15, 19, 23 Interrupt Request Arbitration Circuits 17, 21, 25 Shift register circuit 16, 20, 24 Shift control circuit

Claims (5)

[Claims] 1. An information processing apparatus comprising a main processing unit for controlling the entire system by a microprocessor and a plurality of peripheral units for outputting an interrupt request to the main processing unit, wherein each of the peripheral units and the peripheral unit are connected to each other. An interrupt line with the main processing device is cascade-connected with the main processing device as the uppermost stream by a serial signal line, and each peripheral device has an upper bit string indicating the priority of the interrupt given to the own device and the own device. The presence / absence of each interrupt request in the above is registered with the lower bit string indicated by the bit ("1", "0") at the position associated in advance, and the peripheral devices are synchronized with each other in order from the upper bit. The shift register means for outputting one bit at a time, the bit string from the shift register means of its own device, and the bit string sent from the peripheral device downstream via the serial signal line are set up. The first bit indicating the difference in priority between the two devices is detected by sequentially comparing each bit from the most significant bit, and the bit string from the shift register means of the own device is detected up to the detection bit before the detection bit. Is provided with shift control means for sending the high-priority device-side bit string to the upstream through the serial signal line, and the main processing device is sent from the adjacent peripheral device through the serial signal line. An interrupt control system comprising: a peripheral device that receives an interrupt request and an interrupt specifying unit that determines an interrupt request content based on the received bit string. 2. The interrupt control system according to claim 1, wherein each peripheral device arbitrates the priority of each interrupt request generated in its own device and the shift register means of the main processing device and its own device. And an interrupt request arbitration means for notifying the shift control means, and the shift control means, when there is no interrupt request notification from the interrupt request arbitration means, transfers the bit string from the downstream peripheral device to the shift register means. An interrupt control system characterized by sending directly to an upstream peripheral device without comparing with a bit string. 3. The interrupt control system according to claim 2, wherein when the main processing device receives an interrupt occurrence notification from the interrupt request arbitration means of each of the peripheral devices by wired-OR connection and receives the interrupt occurrence notification of each of the peripheral devices. An interrupt control system characterized by comprising latch signal generating means for generating a latch signal for simultaneously permitting registration of an interrupt request from each interrupt request arbitration means to each shift register means. 4. The interrupt control system according to claim 1, wherein each of the peripheral devices sends a bit string indicating the priority of the own device received from the upstream to the shift register means, and the priority of the own device. The adder means for generating a bit string indicating the next priority and sending the bit string to the downstream side is provided, and the adder means of the peripheral device adjacent to the main processing device assigns the bit string indicating the highest priority to the main processing device. An interrupt control system characterized by receiving from the main processing unit at the time of starting. 5. The interrupt control system according to claim 1, wherein the main processing unit is used for synchronization of transmission of a bit string from each shift register means of each peripheral device and synchronization of a comparison operation of each shift control means. An interrupt control system comprising shift clock generation means for generating a clock and sending it to each peripheral device.