JPH06161793A - Coping device in parity error occurrence - Google Patents

Abstract

PURPOSE:To surely decide an error when a data error occurs at a transfer source and to prevent wrong data from changing into normal data by generating a parity error for all data transferred after a parity error is detected in transfer data from the transfer source, and sending the data to a transfer destination. CONSTITUTION:When the data signal read out of a queue buffer B25 for transfer has the parity error, a parity error detecting circuit 1 detects it and holds the output at '1' until all the data are transferred. Therefore, a signal generated by inverting '1' and '0' of the parity signal in the data signal read out of the queue buffer 25 is outputted from an exclusive OR circuit 13 and sent out as the parity signal of the transfer data. Consequently, the parity signal for all data transferred thereafter is sent out as a wrong parity signal and the parity error detecting circuit 25 of a bus interface circuit detects the parity error for all the data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for coping with a case where parity error occurs in transfer data sent from a bus interface circuit for connecting data processing devices with a bus to transfer data.

[0002]

2. Description of the Related Art In a data processing system, a plurality of processing devices are connected via a bus to transfer data between the processing devices. A conventional example of performing data transfer via such a bus will be described with reference to FIGS.

FIG. 5 is a system configuration diagram applied to the present invention and a conventional example. A plurality of processing devices 2-0 to 2-n are connected to a bus via a bus interface circuit 20.
Transfer data. A bus handler 1 arbitrates the use of the bus when transferring data between processing devices.

The bus interface circuit 20 is, as shown in FIG. 6, a data transfer control unit 21 for controlling data transfer, a transfer from the queue buffer A24 to a local bus in the processing device 2 and a transfer to the queue buffer B25. The transmission / reception unit L22 for performing the data transfer, the transmission / reception unit S23 for transferring data into and out of the queue buffers 24 and 25 from the system bus, and the parity error detection circuit 26 for detecting a parity error in the data transferred from the system bus. It

Now, the processing device 2-n is better than the processing device 2-n.
The operation will be described with reference to the operation time chart shown in FIG. Data transfer and data transfer control are performed in synchronization with clock timing (not shown).

First, when a data transfer request is issued from the processor # 0, the bus interface circuit sends a bus use request signal BREQ to the bus handler (FIG. 7).
(A)). The bus handler refers to the bus use request signal issued from the other processing device, and sends the bus use permission signal BGRM to the processing device # 0 based on its priority (FIG. 7 (f)).

In the processor # 0, the bus use permission signal BGR
Upon receiving M, the bus use start signal BS is transmitted (see FIG. 7).
At the same time, the data is sent from the queue buffer B25 to the system bus SYS (FIG. 7 (c)), and the in-data transfer signal BK is sent up to one data before the final data (FIG. 7 (d)).

When the bus use start signal BS is sent from the processor # 0, the bus handler sends a status signal line enable signal BGRS which permits the use of the status line for transferring the status signal to the processor #n ( Figure 7
(G)) Further, the bus handler receives the data transfer signal BK from the processor # 0 and sends the bus use permission signal BGRM which permits the processor # 0 to use the bus also in the next timing period (FIG. 7 (f. )) Do.

The data transferred to the processor #n via the system bus is stored in the queue buffer A24, and the parity error detection circuit 26 determines whether or not the data transferred has a parity error. . For data transfer, as shown in FIG. 7C, the command signal C is first transferred, and then the data signal D is transferred. The parity error detection circuit 26 first detects a parity error in the command signal C, transfers the error occurrence status S _C via the status line STC, and transfers the data signal at each timing. It is determined whether or not there is a parity error in the data signal to be processed, and if even one of the transferred data blocks has a parity error, the error occurrence status S _D is transferred to the processing device # 0.

In the data transfer control unit 21 of the processing device # 0, if the status signal transferred from the processing device #n is a status with an error, the data is re-transferred, and if there is a transfer error every time, the processing device #n is processed. The CPU of # 0 is notified, and the determination of the subsequent processing is entrusted (FIG. 7E).

In the bus handler, when the data transfer signal BK from the processing device # 0 stops (see FIG. 7).
(D)), the transmission of the bus use permission signal BGRM and the status signal line permission signal BGRS is stopped (Fig. 7 (f),
(G)), and the execution of the next transfer process for generating the bus use request signal BREQ (not shown) is started.

[0012]

As described above, in the conventional data transfer between processing devices, the parity error of the transferred data signal is detected, and when the parity error is detected, the transfer source processing device is detected. It was transmitted that there was a parity error, and the data was retransmitted.

Therefore, if the transfer data is stored, the queue buffer B25 of the bus interface circuit is stored.
When the transfer data is sent out, if there is an error in the sent data, or if it is transferred to the transfer destination processing device via the system bus without error, the parity error detection circuit 26 of the transfer destination interface circuit Although a data error can be detected, if an error occurs during data transfer via the system bus due to noise or the like, the parity error detection circuit 26 cannot detect the parity error and will be processed as normal data thereafter.

It is an object of the present invention to provide a coping device when a parity error occurs so that when the transfer data from the transfer source has a parity error, the data transferred at the transfer destination does not change to normal data. And

[0015]

Means adopted by the present invention for solving the above problems will be described with reference to FIG. FIG. 1 shows the principle of the present invention. A device for coping with a parity error in the transfer data from the bus interface circuit, comprising: (a) a parity error detection means (10) for detecting a parity error in the transfer data read from the buffer in the bus interface circuit. (B) When a parity error is detected by the parity error detecting means 10, a parity error notifying means for generating a parity error for all subsequent transfer data and notifying the error to the transfer destination bus interface circuit ( 11), and.

[0016]

The parity error detecting means 10 detects a parity error in the transfer data read from the buffer of the transfer source bus interface circuit. When the parity error detection unit 10 detects a parity error, the parity error notification unit 11 generates a parity error for all subsequent transfer data and notifies the transfer destination bus interface circuit of the parity error.

As described above, when a parity error is detected in the transfer data from the transfer source, a parity error is generated for all the data transferred thereafter and the transfer destination is notified. If there is a data error, it can be surely judged as an error, and it can be prevented that the data is changed to normal data.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIG. FIG. 2 is a configuration diagram (bus interface circuit) of the first embodiment. In FIG. 2, the data transfer control unit 2
1, the transmission / reception units 22 and 23, the queue buffers 24 and 25, and the parity error detection circuit 26 are as described in FIG.

Numeral 12 is a parity error detection circuit,
A parity error in the transfer data read for transfer from the queue buffer B25 is detected. Reference numeral 13 denotes an exclusive OR circuit (EXOR), which is a parity error detection circuit 12
And the parity signal output from the queue buffer 25 are exclusive-ORed and output as a parity value.

Next, the operation of the embodiment will be described. Since the operation during normal data transfer has been described in the conventional example, description thereof is omitted. When there is a parity error in the data signal read from the queue buffer B25 for transfer, the parity error detection circuit 12 detects it, sets the output to "1", and holds it until all the data is transferred.

Therefore, a signal obtained by inverting the parity signal "1" and "0" in the data signal read from the queue buffer 25 is output to the output of the EXOR 13 and sent as the parity signal of the transfer data. For this reason,
When the parity error detection circuit 12 determines that there is a parity error, the parity signals for all the data to be transferred thereafter are sent as a signal having a parity error. Therefore, in the transferred data, the parity error detection circuit 26 of the transfer destination bus interface circuit 20 detects a parity error in all the data. Therefore, even if an error occurs due to noise or the like during data transfer and the parity error is not detected, the parity error is detected in the other data signals, so that it is certain that there is a data error. I can know.

In the embodiment, the exclusive OR of the parity signal of the transfer data is taken, but the exclusive OR of 1 bit in the data signal may be taken. It is also possible to generate and send another data signal that violates the parity rule. As one method in this case, it can be easily obtained by setting the transmitter to a high impedance in a floating state. That is, the logic inside the bus interface circuit is positive and the logic above the system bus is negative, and the number of bits that make up data is usually made up of even bits in units of bytes. When the error detection circuit 12 detects a parity error, the transmission of data from the transmission / reception unit S23 is stopped. Transceiver S
When the transmission of the data from 23 is stopped, all the signals become "1" and the signals generate the parity error.

Next, a second embodiment will be described with reference to FIG. In FIG. 3, the data transfer control unit 21, the transmission / reception units 22 and 23, the queue buffers 24 and 25, and the parity error detection circuit 26 are as described in FIG. 12 is a parity error detection circuit, and 14 is an OR circuit.

When the data signal read from the queue buffer B25 for transfer has a parity error, it is detected by the parity error detection circuit 12 and output to the OR circuit 14.
The OR circuit 14 takes an OR with the bus use start signal BS sent from the data transfer control unit 21.

Therefore, as shown in FIG. 7B, in addition to the transmission of the regular BS signal, the bus use start signal BS is transmitted again in the timing period in which there was a parity error. When this bus use start signal BS is sent again,
Since the bus handler 1 receives a command different from the normal sequence, a command violation occurs, and the transmission of the bus use permission signal BGRM and the status signal line permission signal BGRS is stopped.

When the transmission of the BGRM signal and the BGRS signal is stopped, the transfer of data from the processing device # 0 to #n and the transfer of the status signal from the processing device #n to # 0 are stopped, and the CPU of each processing device is stopped. Notify that an error has occurred and let the subsequent processing be determined. Therefore, if there is a parity error at the transfer source, it is surely processed as a data error, and it does not change to normal data.

Next, a third embodiment will be described with reference to FIG. In FIG. 4, the data transfer control unit 21, the transmission / reception units 22 and 23, the queue buffers 24 and 25, and the parity error detection circuit 26 are as described in FIG. 12 is a parity error detection circuit, and 14 is an OR circuit.

If the data signal read from the queue buffer B25 for transfer has a parity error, it is detected by the parity error detection circuit 12 and output to the OR circuit 14.
The OR circuit 14 takes an OR with the retry signal RTRY sent from the data transfer control unit 21.

Therefore, if there is a parity error at the transfer source, the retry signal RTRY is sent out and the transferred data at the transfer destination is invalidated. However, in this case, the retry signal is not sent from the data transfer control unit, and the data is not retransferred. Therefore, if there is a parity error at the transfer source, it is processed as a data error and does not change to normal data.

[0030]

As described above, according to the present invention, the following effects can be obtained. When a parity error is detected in the transfer data from the transfer source, a parity error is generated for all data that will be transferred thereafter and the transfer destination is notified, so if there is a data error in the transfer source, It is definitely judged as an error,
It can be prevented from changing to normal data.

Further, when a parity error is detected at the transfer source, a bus use start signal is sent to notify, so that a command violation occurs and data transfer is stopped. It is possible to prevent the data from changing to normal data.

When a parity error is detected at the transfer source, a retry signal is sent to notify the transfer error. Therefore, the transferred data is invalidated and data transfer is performed again from the beginning. It is possible to prevent the data from changing to normal data.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of a first embodiment of the present invention.

FIG. 3 is a configuration diagram of a second embodiment of the present invention.

FIG. 4 is a configuration diagram of a third embodiment of the present invention.

FIG. 5 is a system configuration diagram to which the present invention and a conventional example are applied.

FIG. 6 is a configuration diagram of a conventional example of a bus interface circuit.

FIG. 7 is an operation time chart of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Bus handler 2 Processing device 10 Parity erroneous detection means 11 Parity erroneous notification means 12, 26 Parity erroneous detection circuit 13 Exclusive logic circuit 14 OR circuit 21 Data transfer control unit 22, 23 Transmission / reception unit 24, 25 Queue buffer

Claims (4)

[Claims] 1. A device for coping with a parity error in transfer data from a bus interface circuit,
(A) a parity error detecting means (10) for detecting a parity error of the transfer data read from the buffer in the bus interface circuit; and (b) when a parity error is detected by the parity error detecting means 10, And a parity error notifying unit (11) for generating a parity error for all the transfer data and notifying the bus interface circuit of the transfer destination of the error. 2. A parity error occurrence according to claim 1, wherein the parity error notification means (11) notifies the parity error by stopping the bus output and setting the floating state to notify the parity error. Equipment for dealing with time. 3. The source interface circuit instead of the parity error notifying means (11) generating a parity error for all subsequent transfer data and notifying the interface circuit of the transfer destination of the parity error. 2. The apparatus for coping with the occurrence of parity error according to claim 1, wherein the bus use start signal is retransmitted, and a protocol violation is generated and notified. 4. The transfer source interface circuit, instead of the parity error notifying means (11), which generates a parity error for all subsequent transfer data and notifies the transfer destination interface circuit of the parity error. 2. The device for coping with the occurrence of a parity error according to claim 1, wherein a retry signal is further sent to notify.