JPH01112354A - Interruption request signal control system - Google Patents

Abstract

PURPOSE:To output an active interruption request signal successively by a slave device, by holding an interruption request signal by providing an interruption request signal reservation part. CONSTITUTION:An F/F203 constitutes an interruption request signal holding part 230 which holds the interruption request signal to be supplied to a master device 300, and an F/F208 constitutes the interruption request signal reservation part 280 which holds the active interruption request signal when it is delivered from the slave device 100. When the master device 300 completes an interruption processing, a signal held by the interruption request signal reservation part 280 is transferred to the interruption request signal holding part 230. In such a way, the interruption request signal is outputted one by one and it can be held and reserved at the interruption request signal holding part even when plural interruption requests are generated from the slave device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interrupt request signal control method applicable to various computer systems.

[Conventional technology]

FIG. 2 shows a configuration for realizing a conventional interrupt request signal control method. Il to master device 11 such as CPU
When a slave device 12 such as o makes an interrupt request, it is done as follows.

First, the slave device 12 detects that the master device 11 has finished interrupt processing by checking whether the signal line 13 is at the L level, and activates the interrupt request signal (H level) only when the signal line 13 is at the L level. It was output to the signal line 14 as . When an active interrupt request signal arrives from the slave device 12, the interrupt control circuit 15 sets its output to H level and outputs it to the master device 1.
Interrupts 1. When the master device 11 completes the interrupt processing, it supplies a reset signal to the interrupt control circuit 15 via the signal line 16. As a result, the interrupt control circuit 15
returns its output from H level to L level.

[Problem that the invention seeks to solve]

However, when this control method is adopted, if multiple interrupt requests occur in the slave device 12 while the master device 11 processes one interrupt,
It became necessary for the slave device 12 to postpone sending out an active interrupt request signal until the master device 11 completes the interrupt processing.

That is, when the master device 11 is processing an interrupt, the signal line 13 is held at H level, and no matter how many times the slave device 12 outputs an active interrupt request signal, it becomes meaningless. Therefore, in the slave device 11, even if multiple interrupt requests actually occur, the active interrupt request signal cannot be output until the master device 1 finishes interrupt processing, and the slave device 12
Control is required to compensate for the difference between the interrupt request generated in 1 and the output active interrupt request signal, resulting in the problem of complicating the configuration of the slave device 12 and increasing the load.

Therefore, the present invention provides an interrupt request signal control method that allows the slave device to output an active interrupt request signal even if an interrupt request occurs in the slave device while the master device has not finished interrupt processing. The purpose is to

[Means for solving problems]

The interrupt request signal control method according to the present invention includes an interrupt request signal holding section that holds an interrupt request signal to be given to a master device, and an interrupt request signal holding section that holds an active interrupt request signal from a slave device. and at least one interrupt request signal reservation section that holds an active interrupt request signal when it is sent, and when the master device finishes interrupt processing, the interrupt request signal reservation section holds the signal held by the interrupt request signal reservation section. The feature is that the information is transferred to the department.

[Effect]

Since the interrupt request signal control method of the present invention is configured as described above, even if multiple interrupt requests occur in the slave device, the active interrupt request signals are output from the slave device one after another, and the interrupt request signal reservation section until the master device finishes processing the interrupt.
In other words, interrupt requests can be reserved in advance.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to FIG. 1 of the accompanying drawings.

FIG. 1 is a block diagram of a control device that implements an interrupt request signal control method according to the present invention. As shown in the figure, an interrupt request signal is applied from the slave device 100 to OR gates (negative logic AND gates) 202, 206, and 207 via a signal line 201. The output signal of the OR gate 202 is applied to a preset terminal of a flip-flop (hereinafter referred to as F/F) 203. The signal at the output terminal Q of F/F2O3 is sent to the master device 3 via the driver 204.
00 to the interrupt terminal INT, and also to the OR gate 202 and the inverter 205. The output signal of the inverter 205 is given to the OR gate 206,
The output signal of OR gate 206 is provided to the preset terminal of F'/F 208. The data terminal of the F/F 20g is grounded, and the output signal of its output terminal Q is applied to the data terminal of the F/F 20B and the inverter 210 via the driver 209. The output signal of the inverter 210 is given to the OR gate 207, and the OR gate 20
The output signal of 7 is given to the preset terminal of F/F 211. The data terminal of the F/F 211 is grounded, and the output signal BUSY at its output terminal Q is applied to the slave device 100.

A clear pulse is output from the clear terminal CLR of the master device 300 every time the master device 300 finishes interrupt processing, and the F/F 203°208.211
is applied to the clock terminal of

Here, F/F2O3 is master device 300
The F/F2O3 constitutes an interrupt request signal holding unit 230 that holds an interrupt request signal to be given to the slave device 100, and when the interrupt request signal holding unit 230 holds an active (H level) interrupt request signal, the F/F2O3 An interrupt request signal reservation unit 280 is configured to hold an active interrupt request signal when it is sent. Furthermore, F/
The output signal BUSY of F211 is the interrupt request signal reservation section 2.
80 holds an active interrupt request signal and becomes active (H level) when the next interrupt request cannot be reserved.

The operation of the control device configured in this way will be explained below.

First, in the initial state, F/F2O3, 208°211 is in a reset state. When an interrupt request occurs in the slave device 100, the slave device 100 outputs an active interrupt request signal via the signal line 201. As a result, among the OR gates 202, 206, and 207, the output signal of only the OR gate 202 to which an L level signal is given to one input terminal becomes the L level, and the F
/F2O3 is set and an H level signal is output from the output terminal Q of F/F20B. This signal reaches the interrupt terminal INT of the master device 300 via the driver 204, and interrupts the master device 300.

Based on this interrupt, while the master device 300 is processing the interrupt, the slave device 100
Suppose that an interrupt request occurs in Then, the signal line 201
An active interrupt request signal is sent. At this time, the H level is output from the output terminal Q of F/F2O3,
Since it is inverted by the inverter 205 and reaches the OR gate 206, the output signal of the OR gate 206 becomes L level, which is applied to the preset terminal of the F/F2O3, and the F/F2O3 is set.

As a result, an H level signal is output from the output terminal Q of F/F2O3, and this H level signal is transmitted to the driver 209.
The signal is applied to the inverter 210 via the inverter 210, is inverted, and reaches the OR gate 207.

Here, while the active interrupt request signal is arriving at the signal line 201, the inverter 21 is connected to the OR gate 207.
If an element with a delay amount such that an L-level signal is given through 0 is used, an L-level signal is output from the OR gate 207, and the F/F 211 is set. As a result, the slave device 100 is notified by the active busy signal BUSY that no more interrupt requests can be reserved.

On the other hand, the master device 300 continues the interrupt processing, and when the interrupt processing is completed, it outputs a clear pulse from the clear terminal CLR. As a result, F/F2O3,20
8 and 211 take in signals from respective data terminals. At this time, since an H level signal is applied to the data terminal of the F/F 203 from the output terminal Q of the F/F 208 via the driver 209, the F/F 203 is brought into the set state again. That is, master device 30
0 completes the interrupt processing, the interrupt request signal reservation unit 2
It can be seen that the signal held by the interrupt request signal 80 (here, the active interrupt request signal) is transferred to the interrupt request signal holding unit 230. Also, since the data terminal of F/F2O3, 211 is grounded, F/F20g, 2
11 is put into a reset state, and the busy signal BUSY is made inactive and applied to the slave device 100 to notify that it is possible to reserve an interrupt request. Therefore, the slave device 100 can output an interrupt request signal.

In the above explanation, it is assumed that the next interrupt request signal is output while the master device 300 is processing an interrupt. However, if the slave device 100 does not receive an interrupt request until the master device 300 finishes interrupting,
O3, 211 remains in reset state F/F2 O3, 20
A clear pulse is given to the clock terminal of 8,211,
An L level output signal is given from F/F2O3 to the data terminal of F/F2O3, and as a result of the data terminal of F/F2O3゜211 being grounded, F/F2O3, 2
08 and 211 are all reset, and the next time an active interrupt request signal is output, the F/F 203 becomes set.

This embodiment is suitable for a system in which basically about one interrupt request occurs while the master device 300 is performing interrupt processing. In other words, if many interrupt requests occur in the slave device 100 while the master device 300 is processing interrupts, the busy signal B is always activated.
This is because USY is active, making it impossible to reserve an interrupt request.

The present invention is not limited to the above embodiments, and various modifications are possible.

For example, in a system in which many interrupt requests are generated in the slave device while the master device 300 is processing interrupts, the interrupt request signal reservation section is provided in multiple stages depending on the frequency of occurrence of interrupt requests. The active interrupt request signal is stored in order from the first-stage interrupt request signal reservation section to the last-stage interrupt request signal reservation section, and when transferred to the interrupt request signal holding section, the signal in the first-stage interrupt request signal reservation section is stored. At the same time, the signals of each separate request signal reservation section are shifted from the final stage side to the first stage side.

Also, when the number of stages of the interrupt request signal reservation section is increased with sufficient margin compared to the frequency of interrupt requests generated in the slave device during interrupt processing of the master device,
In order to prevent reservation of interrupt requests from becoming impossible, the configuration for providing the busy signal BUSY may be removed.

〔Effect of the invention〕

As explained in detail above, in the present invention, an interrupt request signal reservation section is provided to hold the interrupt request signal, and when the master device finishes interrupt processing, it is given to the master device as an interrupt request signal. Control to compensate for the difference between the generated interrupt request and the output active interrupt request signal is no longer required.
The slave device can output active interrupt request signals one after another, which has the effect of simplifying the configuration of the slave device and reducing the load.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a control device that implements the interrupt request signal control method according to the present invention, and FIG. 2 is a block diagram of a system using the conventional interrupt request signal control method. 100... Slave device, 200... Master device, 230... Interrupt request signal holding unit, 28
0: Interrupt request signal reservation section. Patent applicant: Sumitomo Electric Industries, Ltd.

Claims (1)

[Claims] 1. An interrupt request signal holding unit that holds an interrupt request signal given to the master device, and an active interrupt from a slave device when this interrupt request signal holding unit holds an active interrupt request signal. and at least one interrupt request signal reservation section that holds the request signal when it is sent, and when the master device finishes the interrupt processing, the interrupt request signal reservation section holds the signal held by the interrupt request signal reservation section. An interrupt request signal control method characterized by transmitting the interrupt request signal to the section. 2. The interrupt request signal reservation section has multiple stages, and the active interrupt request signal is stored in order from the first stage interrupt request signal reservation section to the last stage interrupt request signal reservation section, and then to the interrupt request signal holding section. At the time of transfer, the signal of the interrupt request signal reservation section of the first stage is transferred, and the signal of each interrupt request signal reservation section is shifted from the last stage side to the first stage side. Interrupt request signal control method described in . 3. If all of the interrupt request signal reservation units hold active interrupt request signals, activate a busy signal indicating that reservation of an interrupt request is not possible, and in other cases, activate the busy signal. 3. The interrupt request signal control method according to claim 1, wherein the interrupt request signal is provided as inactive to the slave device.