JPH03225458A - Dma control system - Google Patents

Abstract

PURPOSE:To enable DMA control which allows a multichannel conflict by an LSI package having a small number of pins by providing a DMA controller and a DMA request adapter (DREQ adapter) which arbitrates plural DMA request signals and DMA acknowledgement signals. CONSTITUTION:The DMA controller 2 is supplied with the latch timing of a channel code and DMA actuation timing with a DMA actuation signal 12 sent from a DREQ adapter 3. Further, when the DMA controller 2 is ready to receive the DMA actuation signal 12, the DMA controller 2 informs a DREQ adapter 3 by using a DMA ready signal 13. Consequently, the DMA controller 2 which controls the actuation timing of DMA by two signal lines 12 and 13 and receives a DMA channel as a code enables the multi-channel conflict DMA with a small number of pins.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a DMA control method for an information processing apparatus having a DMA function of multiple channels.

[Conventional technology]

In the conventional method, as described in Japanese Unexamined Patent Publication No. 64-59445, signal lines for the number of requesters (DACKI', DACK2') are used to identify multiple requesters from an adapter that processes multiple DMA requests. ...), were written out to memory. This required many pins.

Further, as shown in the above publication, each DMA bus cycle time is synchronized with the DACK signal output from the DMA controller.

[Problem to be solved by the invention]

The above-mentioned conventional technology has a problem in that a large number of pins are required when making an LSI package that controls a large number of IO devices by DMA, and the number of IO devices is limited.

Furthermore, since the DMA bus cycle time is determined by the DACK signal issued from the DMA controller, there is also the problem that requests for extension of the DMA bus cycle time from memory or IO devices cannot be accepted.

A first object of the present invention is to provide a DMA control system with multiple channels and a small number of pins so that a large number of devices can be controlled. A second object is to provide a DMA control method that allows requests for extension of DMA bus cycle time to be accepted.

[Means to solve the problem]

In order to achieve the above first object, the present invention has the following features.

A DREQ adapter that mediates multiple DMA request signals and controls a DMA acknowledge signal is provided between an IO device that makes a DMA request and a DMA controller, and the DMA controller is made to recognize the activated DMA channel as coded information. It is characterized by:

In addition, in order to achieve the second purpose, CP
U, DMA controller, and DREQ adapter,
A bus cycle extension request signal line is provided to notify a request to extend the DMA bus cycle time.

[Effect]

The DMA controller is given channel code latch timing and DMA start timing by a DMA start signal transmitted from the DREQ adapter. Also, DM
If controller A can accept the DMA activation signal,
The DMA controller uses the DMA ready signal to
Notify Q adapter. DMA using these two signal lines
Multi-channel competitive DMA is possible with a small number of pins by using a DMA controller that controls the startup timing of the DMA controller and accepts DMA channels as codes.

In addition, the bus cycle extension request signal issued from the memory delays the rising timing of the DMA start signal issued by the DMA controller, the rising timing of the DMA ready signal issued by the DREQ adapter, and the rising timing of the R/W control signal. It becomes possible to extend the DMA bus cycle time.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS An information processing apparatus which is an embodiment of the present invention will be described below with reference to FIGS. 1 to 5.

FIG. 1 is a system configuration block diagram of an embodiment of the present invention. In the figure, 1 is the CPU, 2 is the DMA controller (
3 is a DMA request adapter (hereinafter referred to as rDREQ adapter) that arbitrates and controls multiple DMA request signals and DMA acknowledge signals; 4 is an address bus; 5 is a data bus; 6 is a memory; is an IO device (group) that makes a DMA transfer request.

In addition, 8 is a DMA request signal (hereinafter abbreviated as DREQ signal) output by the IO device 7, and 9 is a DMA acknowledge signal (hereinafter referred to as DACK signal) that informs the IO device 7 that outputs the DREQ signal 8 that the DMA transfer request has been approved. omitted)
, 10 is the BUSREQ signal from which the DREQ adapter 3 requests the CPU to release the right to use the bus, and 11 is the BUSREQ signal from which the CPU
BUS that conveys approval for the request of USREQ signal 11
ACK signal, 12 is a DMA start signal in which the DREQ adapter 3 requests the DMAC 2 to start a DMA bus cycle;
13 is a DMA ready signal that tells the DREQ adapter 3 that it is ready to accept the DMA activation signal 12; 14 is a channel code signal that encodes and conveys the channel number of the DMA to be activated from the DREQ adapter 3 to the DMAC 2; 15 is a read/write control signal (hereinafter abbreviated as "rR/W control signal") that controls the timing of the read bus cycle and write bus cycle, and 16 is an address valid signal that indicates that the signal output from the address bus 4 is valid. It's a signal. 17, the memory is CPtJ,
This is a bus cycle extension request signal that requests the DMAC1 and DREQ adapters to extend the DMA bus cycle time.

FIG. 2 is a flowchart showing the sequence of DMA activation according to the present invention. 3 is a timing chart of a single DMA cycle according to the present invention, FIG. 4 is a timing chart of a continuous DMA cycle according to the present invention, and FIG.
The figure is a detailed block diagram of the DREQ adapter 3.

DMA activation according to the present invention will be explained based on FIG. 2.

Assume that the initial state is a state in which DMA is possible, that is, the DMA ready signal 13 has already been asserted from the DMAC 2 to the DREQ adapter 3.

First, a DMA request is generated in the IO device 7, and the DREQ signal 8 is asserted. The DREQ adapter 3 is the IO device 7
- When any DREQ signal from 1 to n is detected, the CPU
BUSREQ signal 1 to request release of bus ownership.
Assert 0. CPU1 receives BUSREQ signal 10
After receiving, when the bus right can be released, the BUSACK signal 1 is sent.
Asserted to 1 to indicate release of CPU bus ownership. B.U.
The DREQ adapter 3 that received the SACK signal 11
The DMA channel with the highest priority among the DREQ signals 9-1 to 9-n issued by the O device 7-1-n is determined.

The channel number is encoded and output as a channel code signal 14. At the same time, DREQ adapter 3
A DMA activation signal 12 is sent to C2. Upon receiving the DMA activation signal 12, the DMAC 2 latches the code while the DREQ adapter 3 is sending out the correct channel number from the channel code signal 14, takes it into the code, and starts activating the DMA cycle execution. At the initial timing of activation of the DMAC2, the DMAC2 negates the DMA ready signal 13 and sends the DM to the DREQ adapter 3.
It informs that it is in a state where it cannot accept the A start signal 12. Next, the DMAC 2 sends the DMA transfer address to the address bus 4 and outputs an address valid signal 16. The DREQ adapter 3 that detected the address valid signal 16 is a DAC.
Assert K signal 9 and start a DMA cycle. D.A.
The ■○ device 7 that received the CK signal 9 learns that the DMA request has been accepted and negates the DREQ signal 8.

Specific timings are shown in FIGS. 3 and 4.

Although FIGS. 3 and 4 illustrate a clock synchronization circuit that operates on the rising edge of a single-phase operating clock signal, a system of synchronization using multiphase clocks is also conceivable.

As for starting the DMA cycle, I'm not sure what to do.

Termination control will be described below.

During a DMA cycle, the R/W control signal 15 is necessarily asserted and negated. Taking the necessary timing from the negation timing of the R/W control signal 15, the DREQ adapter 3 negates the BUSREQ signal 10 and DA
The CK signal 9 is negated. In the example of FIG. 3, after the R/W control signal 15 is negated, B
Negate the USREQ signal lO, and after 2 clocks DA
Negate the CK signal 9. Due to this timing, D
From the clock next to the MA cycle, a CPUI access cycle can be started without an idle cycle.

Next, the control when starting the DMA cycle of another channel immediately after the completion of the DMA cycle of one channel will be explained with reference to FIG.

As shown in FIG. 4, according to the present invention, a DMA bus cycle (2) can be executed after a DMA bus cycle (1) without an idle cycle. Although two bus cycles are shown in Figure 4, this does not necessarily mean two bus cycles; a DMA bus cycle (3) may be executed next, and the maximum number of DMA transfers is possible. Continuous execution for several X channels is possible.

What makes such continuous DMA cycle control possible is the timing of the DMA ready signal 13. DM
The A ready signal 13 is negated when the DMA activation signal 12 is received, but as the DMA cycle progresses,
It is reasserted after the required amount of time (controlled by the number of clocks) has elapsed. The DREQ adapter 3 confirms that the DMA ready signal 13 is active and starts DMA in response to an already existing (detected and latched) DMA request (corresponding to the DREQ signal -N(2) in the figure). A signal 12 is sent out. DMAC2 that received the DMA activation signal 12,
During the DMA bus cycle (1), preparatory operations for performing the DMA bus cycle (2) are performed in an overlapping manner.

When a DMA bus cycle time extension request occurs in the memory, the bus cycle extension request signal is sent from the memory to the CPU.
, DMAC, and DREQ adapter.

At this time, by extending the timing at which the DREQ adapter raises the DMA start signal 12, the timing at which the DMAC raises the DMA ready signal 13, and the timing at which the R/W control signal 15 rises, as shown in FIG. , extending the DMA bus cycle.

DR, which is an important part of the present invention that performs the control described above.
A detailed block diagram of the EQ adapter 3 and the DREQ adapter 3 interface section of the DMAC 2 is shown in FIG. Among the numbers assigned to the figures, those in common with those in FIG. 1 indicate the same parts. DREQ signal 8-1~n
is synchronized by the synchronization circuit 51 and used as an internal logic signal. This synchronized DREQ signal is sent to the OR circuit 52.
It becomes the source of the BUSREQ signal 12. On the other hand, it is input to a priority determination circuit 53 and its priority is determined. After determining the priority, the encoder 54
encoded in . Timing control episode! ! 55 and D
The ACK control circuit 56 performs control at the timing described above. DMAC 2 receives the coded channel number at latch 57 and transmits it to control circuit 59 via decoder 58 .

According to this embodiment, there is an effect that multi-channel DMA control can be realized with an LSi package having a small number of pins. Specifically, assuming that the channel number is encoded into n binary digits, for 8 channels, there will be 8,8 DREQ signals and 8 DACK signals.
A total of 16 signals (9.8) are 12 DMA activation signals and DM
There are 13 A ready signals and 14.3 channel code signals, making a total of 5 signals.

When the DMAC2 is built in the same LSi chip as the CPUI, the R/W control signal 15 and the 4° address valid signal 16 can be used in common by the CPUI and the DMAC2.

〔Effect of the invention〕

According to the present invention, there is an effect that multi-channel competition is possible and MA control can be realized with an LSI package with a small number of pins, and multi-channel DMA control can be performed with an inexpensive LSI with a small number of pins. As a result, information processing systems can be provided at low cost.

Furthermore, using an LSi package with the highest number of pins in the current technology has the effect of providing a DMA controller with the highest number of channels in the current technology.

Furthermore, since the DMA bus cycle time can be extended arbitrarily, it is possible to easily respond to changes in the MA bus cycle time if necessary.

[Brief explanation of drawings]

FIG. 1 is a system configuration block diagram of an embodiment of the present invention.
FIG. 2 is a flowchart showing a DMA startup sequence according to the present invention, FIG. 3 is a timing chart of a single DMA cycle according to the present invention, FIG. 4 is a timing chart of continuous DMA cycles according to the present invention, and FIG. 5 is a DRE
3 is a detailed block diagram of the Q adapter 3. FIG. 1... CPU, 2... DMAC5 3... DREQ adapter, 7... ■○ device, 12... DMA start signal. 13...DMA ready signal, 14...Channel code signal. Eye

Claims (1)

[Claims] 1. In an information processing device consisting of a CPU, a plurality of IO devices that make DMA transfer requests, and a memory that serves as the source and destination of data during DMA transfer, a DMA channel to be activated is connected to a signal line. A DMA controller that has the function of receiving code information from
DMA request adapter (DREQ adapter) that arbitrates MA request signal and DMA acknowledge signal
The DMA controller includes a DMA start signal in which the DREQ adapter requests the DMA controller to start a DMA cycle;
a function of controlling the activation of a DMA transfer bus cycle using a DMA ready signal that notifies the DREQ adapter that it is in a state where it can normally accept the DMA activation signal;
It is characterized by having a function of controlling the DMA transfer bus cycle time using an address valid signal, etc., which always changes before the start of the DMA transfer bus cycle, and a read/write control signal line, etc., which always changes before the end of the DMA transfer bus cycle. DMA control method. 2. A DMA controller that has a CPU, multiple IO devices that make DMA transfer requests, and memory that serves as the source and destination of data during DMA transfer, and has the function of receiving the DMA channel to be activated as code information from the signal line. and multiple D
DMA request adapter (DREQ adapter) that arbitrates MA request signal and DMA acknowledge signal
The DMA controller includes a DMA start signal in which the DREQ adapter requests the DMA controller to start a DMA cycle;
a function of controlling the activation of a DMA transfer bus cycle using a DMA ready signal that notifies the DREQ adapter that it is in a state where it can normally accept the DMA activation signal;
The DMA controller controls the DMA transfer bus cycle time using the address valid signal, etc., which always changes before the start of the DMA transfer bus cycle, and the read/write control signal line, etc., which always changes before the end of the DMA transfer bus cycle. An information processing device having a DMA control function, comprising: 3. The DMA control method according to claim 1, further comprising a bus cycle extension request signal line for notifying a DMA bus cycle time extension request from the memory to the CPU, DMA controller, and DREQ adapter; The information processing device according to claim 2. 4. An LSI comprising a pin for inputting an identification code of an IO device to be DMA-controlled, and a DMA controller for DMA-controlling the IO device based on the result of decoding the input identification code. 5. A DREQ adapter that mediates multiple DMA request signals and controls a DMA acknowledge signal is provided between the IO device that makes the DMA request and the DMA controller,
D characterized in that the DMA controller is configured to recognize the DMA channel to be activated as coded information.
MA control method.