JPH0125095B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Applicability] The present invention relates to an interrupt processing method in a computer system, and in particular, in bus vector interrupts, a processor reads a vector output from a peripheral control device. The present invention relates to an interrupt processing method that has a means for arbitrarily controlling timing.

[Prior art]

One of the interrupt methods used in computer systems is the bus vector interrupt method. In the bus vector interrupt method, an interrupt request is sent to the processor from the outside, and when the interrupt request is accepted by the processor, the processor starts an interrupt acknowledge cycle, takes in the vector output by the interrupt side onto the data bus, and responds to the interrupt request. Execute interrupt processing. A vector is used to directly or indirectly specify the start address of an interrupt handling program. Next, a specific example will be explained.

Figure 2 shows one conventional example, where 1 is a processor, 2 is a memory, 3 to 5 are peripheral control devices, 6 is a data bus, 7 is an address bus, 8 is an interrupt signal line, and 9 is an interrupt. The acknowledgment signal line is shown. For simplicity, peripheral control devices 3 to 5 are
It is assumed that priority control is performed using a daisy chain for interrupts from . Therefore, even if an interrupt cause occurs simultaneously in a plurality of peripheral control devices, it depends on the order in which the peripheral control devices are connected in a daisy chain. An interrupt from one higher-level peripheral control device is accepted.

When processor 1 detects an interrupt signal from a peripheral control device, it checks whether or not interrupts are disabled, and if they are not masked, executes an interrupt acknowledge cycle and outputs an interrupt acknowledge signal. do.

FIG. 3a shows an interrupt acknowledge signal output from the processor, and b shows a vector output by the peripheral control device on the interrupt side to the data bus in response to the interrupt acknowledge signal. As shown, the processor can read the vector when it is output from the peripheral controller during the interrupt acknowledge cycle.

[Problem that the invention seeks to solve]

Generally, a processor IC and a peripheral control device IC are designed to have a combined interface as one family. There is no problem when using such a combination of ICs, but the response of the peripheral control device IC used does not match the processor, and in order to output the vector shown in Figure 4b,
As shown in FIG. 4a, there are cases in which, for example, two interrupt acknowledge cycles are required. Previously, if there was a mismatch between the processor IC and the peripheral control device IC, it was necessary to abandon the use of the peripheral control device IC or to add a special adapter circuit for timing alignment. .

[Means for solving problems]

The present invention utilizes the bus cycle re-execution function that the processor normally has when it is not possible to return a vector within the interrupt acknowledge cycle of the processor due to poor compatibility with the peripheral control device. This allows the Noritsu cycle to occur substantially multiple times, making it possible to read the vector. This processor's bus cycle re-execution function is generally activated by a bus error signal sent from a peripheral control device to the processor when a data transfer failure occurs during a certain bus cycle, and is used to re-execute the bus cycle. has been done.

The present invention focuses on the fact that an interrupt acknowledge cycle is a bus cycle for reading a vector on a data bus, and uses a bus error signal to re-execute a bus cycle as a bus cycle re-execution command signal for the necessary number of times, i.e. The processor and the peripheral control device are easily connected by generating pseudo vectors as many times as possible to read the vector.
Equipped with a processor and a peripheral control device that have a vector interrupt function and a bus cycle re-execution function.The processor can read a vector in one bus cycle, but the peripheral control device requires multiple bus cycles. In a computer system, when a processor starts a bus cycle and issues an interrupt acknowledge signal in response to an interrupt signal from a peripheral control device, the peripheral control device responds with a bus cycle re-execution command signal and instructs the processor to restart the bus cycle. The method is characterized in that the process of execution is repeated a plurality of times.

〔Example〕

The details of the present invention will be explained below with reference to Examples.

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 5 is an operation timing chart thereof.

In FIG. 1, 1 is a processor, 3 is a peripheral control device, 10 is an interrupt control circuit, 11 is a vector address register, 12 is an interrupt acknowledge flag, 13 is a timer, and 14 is a vector generation circuit. Further, a is an interrupt acknowledge signal, b is a vector, and c is a bus cycle re-execution command signal, and these signals a, b, and c correspond to signal waveforms a, b, and c in FIG. 5, respectively.

When the interrupt control circuit 10 in the processor 1 receives an interrupt signal from the peripheral control device 3, it sets the interrupt acknowledge signal a to "L". As a result, the interrupt acknowledge flag 12 in the peripheral control device 3 becomes "L". When this flag 12 becomes "L", the timer 13 is started and the output is set to "L" after a predetermined time. The output of the timer 13 is notified to the interrupt control circuit 10 as a bus cycle re-execution command signal c.

When the interrupt control circuit 10 identifies the bus cycle re-execution command signal c, it sets the interrupt acknowledge signal to "H" and immediately re-executes the bus cycle. As a result, the interrupt acknowledge signal a becomes "L" again. At this point, the vector generation circuit 14 is ready to output vector b, and the output vector b is read into the vector address register 11 of the processor 1 and used to address the corresponding interrupt processing program. be done.

[Effects of the Invention] As described above, according to the present invention, the processor IC
Even if the interface using the bus vector interrupt method between the computer and the peripheral control device IC is inconsistent in terms of vector read timing, the timing can be easily aligned using an extremely simple method that uses the bus cycle re-execution function. This allows for increased flexibility in system configuration.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of a conventional example, FIG. 3 is an operation timing diagram of vector reading when the processor and peripheral control device are matched, and FIG. The figure is an operation timing diagram of vector reading when the peripheral control device requires a plurality of interrupt acknowledge cycles, and FIG. 5 is an operation timing diagram of the embodiment of FIG. 1. In the figure, 1 is a processor, 3 is a peripheral control device, 1
0 is an interrupt control circuit, 11 is a vector address register, 12 is an interrupt acknowledge flag,
13 is a timer, and 14 is a vector generation circuit.

Claims (1)

[Claims] 1 Equipped with a processor and a peripheral control device that have a bus vector interrupt function and a bus cycle re-execution function.The processor can read a vector in one bus cycle, but the peripheral control device can read a vector in multiple bus cycles. In the required computer system, when the processor starts a bus cycle and issues an interrupt acknowledge signal in response to an interrupt signal from a peripheral control device, the peripheral control device responds with a bus cycle re-execution command signal and An interrupt processing method characterized in that the process of re-executing a cycle is repeated a plurality of times.