JPH0421149A - Dma data transmitting equipment - Google Patents

Abstract

PURPOSE:To reduce the load of a CPU by providing the DMA data transmitting equipment with a data coincidence deciding means, deciding whether data to be written in a memory coincide with stored data or not and informing the decided result to the CPU. CONSTITUTION:When an address signal 21 and a data signal 22 are sent from a DMA circuit 12, the signals 21, 22 are respectively temporarily stored in an address register 14 and a data register 15. A timing control part 16 instructs timing for reading/writing the data contents of the registers 14, 15 from/in a dual port RAM 11. The data coincidence deciding part 17 decides whether the data to be written coincide with the data precedently stored in the RAM 11 or not and informs a signal indicating the decided result to a CPU 13. At the time of receiving a discrepancy signal, the CPU 13 writes only the signal. When the received data coincide with the preceding data of the RAM 11, the processing of the CPU 13 can be omitted. Thereby, the load of the CPU 13 is reduced.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention relates to an MA data transmission device suitable for relatively high-speed data transmission using a DMA method, and particularly relates to an MA data transmission device suitable for performing data transmission at a relatively high speed using a DMA method. The present invention relates to a DMA data transmission device with added technology to reduce burden.

(Prior Art) Conventionally, DMA (DirectMem) is often used to transfer data at high speed between memory and input/output devices.
oryAccess) method is used.

A conventional data transmission device using the DMA method will be described below with reference to FIGS. 5 and 6.

First, Figure 5 shows a D M using a single port RAM.
It is a figure showing an example of A data transmission device. This data transmission device is provided with a single-baud RAMI, and this single-port RAMI includes an address bus 2 and a data bus 3.
A DMA circuit 5 and a CPU 6 are connected via a control line 4 and an address signal and a control signal are input from the DMA circuit 5 and CPU 6 to a single port RAM 1 through an address bus 2 and a control line 4, and a data signal to the DMA circuit 5 is input. writing and reading. 7 is a DMA control signal sent from the DMA circuit 5 to the CPU 6.

In this device, when the DMA circuit 5 operates, the CPU 6 is basically stopped by sending out the DMA control signal 7. After that, the DMA transferred data is written to the single-port RAMI, and then transferred from the DMA circuit 5 to the DMA
A completion signal is sent, and upon receiving this signal, the CPU 6 processes the data each time, even if the written data is the same as the previous data.

Next, FIG. 6 shows an example of a DMA data transmission device using a dual port RAM. In this data transmission device, a DMA circuit 5 is connected to the A port side of the dual port RAM 8, and a CPU 6 is connected to the B port side. Therefore, since the DMA circuit 5 and the CPU 6 operate independently of each other, the single port R shown in FIG.
Data can be written and read more efficiently than AM1, and data can be transferred at high speed. However, after writing the DMA-transmitted data to the dual port RAM 8, the CPU 6 receives the DMA completion signal as in the case of FIG. Perform data processing.

(Problem to be Solved by the Invention) Therefore, as described above, by using the dual port RAM 8 from the single port RAMI, the data transmission speed increases, and the processing of the CPU 6 increases accordingly. As described above, since the same data is processed for each received DMA completion signal, there is a problem that the burden becomes increasingly heavy. .

The present invention has been made in view of the above-mentioned circumstances.
To provide a DMA data transmission device capable of reducing the load on a CPU by omitting CPU processing for received data and previously stored data when the data is the same at the time of transfer.

F Configuration of the Invention] (Means for Solving the Problems) In order to solve the above problems, a DMA data transmission device according to the present invention includes a memory configured with a plurality of ports, and an address signal and a data signal to the memory. a timing control unit that instructs read/write timing to these registers and the memory; and a timing control unit that determines whether the data to be written to the memory matches the previous data stored in the memory. The data matching determining means notifies the CPU of the signal of the determination result, and the CPU is configured to perform data processing based on the signal of the determination result.

(Function) Therefore, by taking the above-described measures, the present invention compares the data to be written into the memory using the DMA method and the previous data read from the memory, and when both data match, sends a DMA completion signal to the CPU. stop sending out the
This reduces the load on the CPU by not processing the same data.

(Example) Examples of the present invention will be described below with reference to FIGS. 1 to 4. FIG. 1 is a block diagram showing an embodiment of the apparatus of the present invention. In this device, A port and B port
It has a dual port RAM II with a Dλ4 port from the B port side via the address bus 21.
A circuit 12 and CPolB are connected. This D
The address bus 21 derived from the MA circuit 12 and the CPU 13 is connected to the RAMI via the address register 14 and the dual port memory address bus 21, a.
It is connected to the A port side of 1. Further, a data bus 22 and a control line 23 are derived from the DMA circuit 12 and the CPU 13, and the data bus 22 is connected to the A port side of the RAMI 1 via a data register 15 and a dual port memory data bus 22a. R is also connected to the control line 23 via the timing control section 16 and the dual port memory control line 23a.
A-B port side of AMI 1 and each register 14
．． 150 is connected to the control terminal side.

In addition, the data bus 22 and the dual port RAMI
A data match determining unit 17 is provided between the data bus 22b for dual port memory derived from the B port side of the data bus 22b, which determines whether both data are the same. It is connected to the DMA completion signal control section 18. This DMA completion signal control section 18
Signal 2 for data writing from A circuit 12 to RAMII
4 and receives the data match/data match signal 25 from the data match determination unit 17, especially when receiving the data match signal 25, the DMA completion signal 26 is sent to the CPU 1.
It has a function to send to 3. 19 is dual po)
This is a bus buffer that outputs data read from the RAMI 1 to the DMA circuit 12 and CPU 13 according to instructions from the timing control section 16. 27 is a DMA control signal.

Next, the operation of the embodiment configured as above will be explained using the timing chart shown in FIG. 2. Second
The figure shows writing from the DMA circuit 12 to the dual port RAM 11, and from the dual port RAM 11 to the CPU 1B.
FIG. 3 is a diagram showing the timing of reading. First, D
When address signals and data signals are sent from MA circuit 12, these signals are temporarily stored in address register 14 and data register 15 via address bus 21 and data node 22, respectively. At this time, DM
When a write signal, which is a control signal, is sent from the A circuit 12 via the control line 23, the timing control unit 16 receives the write signal and controls the dual port RAMI 1.
The A port and each register 14.15 are put into write mode, and a read signal is supplied as a control signal to the B port side of the dual port RAM 11 through the control line 23b.

Incidentally, when writing data "11" to address O, the address signal to the A port side is stored in the address register 14, the data signal is stored in the data register 15, and when writing to address 0 for the first time, the address signal for the dual port memory is stored. A write signal is not supplied to the A port side through the control line 23a.

On the other hand, on the B port side, a data signal is output from the data bus 22b in response to the read signal, and the data match determination unit 1
Sent to 7. The data match determining unit 17 compares the data signal read from the dual port RAMI 1 with the write-sequence data sent to the data bus 22, and outputs a match detection signal when they match. When writing to the next address 1, the data "11" for the address 0 previously stored in the data register 15 is transferred to the data bus 22a based on the address signal and the write signal.
A data signal is written from. The data bus 22 is connected to the B port side by the read signal for address 1.
Data signal "12" is output through b. The content of this data signal "12" and the content of the write data signal "12" are compared in the same manner as the previous time by the data match determination unit 17, or because they match, a match detection signal is sent. Output. At this time, the address signal and data signal from the DMA circuit 12 are respectively sent to the address register 14. The data is stored in the data register 15. D.M.A.
When the completion signal control unit 18 receives the coincidence detection signal, D
The MA completion signal 26 cannot be sent to the CPU 13, and the CPU 13
The load on the CPU 13 is reduced by not processing "12", which is the content of the read data signal. In general, dual-port RAM II allows high-speed writing because the collision prevention circuit does not work when the addresses of both ports do not match. This is because efficiency is improved because no busy signal is used to avoid collisions.

On the other hand, regarding reading of the DMA circuit]2, since the B port of the dual port RAMI 1 is used, the operation is the same as that of a general memory. In the case of this embodiment, since the bus of the DMA circuit 12 and the bus of the CPU 1B are each commonly connected, only one of the DMA circuit 12 and the CPU 13 operates.

Next, FIG. 3 is a block diagram showing another embodiment of the apparatus of the present invention. In this example, dual port RAMI
The CPU 13T is connected to the B port side of No. 1, and the other configurations are almost the same as those of the above embodiment. A particular difference is that a switching circuit 30 is newly provided, and the control signal from the timing control section 16 and the control signal from the CPU 1B are switched and supplied to the control terminal of the dual port RAMI 1.

FIG. 4 is a configuration diagram showing yet another embodiment. In this embodiment, a triple port RAM 11' is used as the memory, and the address signals 31. Data signal 32. The configuration is such that the control signal 33 is input to the C port side.

With such a configuration, the bus of the CPU 1B and the bus of the DMA circuit 12 can be separated, and the bus of the CPU 13 and the DMA circuit 1 can be separated.
2 can be operated simultaneously.

Therefore, according to the configuration of the embodiment as described above, the RAMI
1.11' When the write data and the read data are the same, the DMA completion signal control unit 18 does not send the received DMA completion signal to the CPU 3, so the CPU 1B determines that the data does not need to be processed and does not process it. The burden on the CPU 13 can be reduced accordingly. Moreover,
A comparison check of the two data as described above is done using normal DM.
It can be done in A cycle. Furthermore, by using the triple-port RAMI 1', it becomes possible to perform the operations of the DMA circuit 12 and the CPU 13 independently of each other, and more efficient data processing becomes possible.

[Effects of the Invention] As explained above, according to the present invention, when the received data and the previous data in the memory are the same during reception DMA transfer, the CPU processing for this data can be omitted.
The load on the CPU can be significantly reduced.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIG.
Timing charts for the device shown in Figures 3 and 4.
The figures are block diagrams showing other embodiments of the apparatus of the present invention, and FIGS. 5 and 6 are block diagrams of data transmission apparatus using the conventional DMA system, respectively. 11... Dualport) RAM, 12... DMA
Circuit, 13...CPU, 14...Address register,
15... Data register, 16... Timing control section, 17... Data coincidence determination section, 18. DMA completion signal control section, 19... Bus buffer, 3o... Switching circuit.

Claims (1)

[Claims] A memory configured with a plurality of ports, a register for storing address signals and data signals to the memory, and a timing control section for instructing read/write timings to these registers and the memory. , determine whether the data to be written into the memory matches the previous data stored in the memory, and send the signal of the determination result to C.
1. A DMA data transmission device, comprising: data matching determining means for notifying a PU, wherein the CPU performs data processing based on a signal resulting from the determination.