JPH04362761A - Bus configuration system - Google Patents

Abstract

PURPOSE:To improve information transfer efficiency to the utmost even when the number of connected device is increased and a common bus becomes large regarding a bus configuration system in an information processing system connecting plural devices by the common bus. CONSTITUTION:A bus extension means 300 performing cascade connection of plural common buses 200 connecting devices 100 of less than a prescribed number, respectively is provided. The bus extension means is constituted by combining two units of bus extension control circuit, for instance. When the means receives the information transmitted from a device connected with one common bus for which the cascade connection is performed to a device connected with the other common bus, the means is constituted so that it may transfer the receiving information to the other common bus, return a response signal for the receiving information to one of the common bus and release one of the common bus.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus configuration method in an information processing system in which a plurality of devices are connected via a common bus.

0002

2. Description of the Related Art FIG. 4 is a diagram showing an example of a conventional information processing system, and FIG. 5 is a diagram showing an example of an information transfer process in FIG. 4.

In FIG. 4, a processor (CPU) 1 and a plurality of input/output devices (I/O devices) constituting an information processing system are shown.
O) 2, 3, and 4 are interconnected by a system bus 5, and a system bus handler (SBH) 6 manages the right to use the system bus 5.

For example, when a processor (CPU) 1 transfers a command e to an input/output device (IO) 4, it first sends a bus request signal to the system bus 5 in order to acquire the right to use the system bus 5. Send a.

The system bus handler (SBH) 6 receives the bus request signal a sent to the system bus 5, and when it enters the request signal acceptance state b, analyzes the usage state of the system bus 5 and makes it available for use. If so, a bus request permission signal c indicating that the right to use the system bus 5 has been granted is sent back via the system bus 5 to the processor (CPU) 1 from which the bus request signal a was sent.

When the processor (CPU) 1 receives the bus request permission signal c sent to the system bus 5 and enters the permission signal acceptance state d, the processor (CPU) 1 transmits the command e addressed to the input/output device (IO) 4 to the system bus 5. Send to.

The input/output device (IO) 4 is connected to a system bus 5.
When the destination of the command e sent to is analyzed and it is identified as the command e addressed to the own input/output device (IO) 4, the command e is received and the command reception process f is entered, and the command e is sent to the command e.
A response signal g confirming the reception of the command e is sent back via the system bus 5 to the processor (CPU) 1 from which the command e was sent.

When the processor (CPU) 1 receives the response signal g sent to the system bus 5, it confirms that the command e has been normally received by the destination input/output device (IO) 4, and confirms the normality. The state becomes h.

On the other hand, when the system bus handler (SBH) 6 also detects that the response signal g has been sent to the system bus 5, it confirms that the processor (CPU) 1 has finished using the system bus 5 normally. It enters the state of normality check i, regains the usage right granted to the processor (CPU) 1, and prepares for the next bus usage request.

0010

As is clear from the above description, in a conventional information processing system, a processor (CPU) 1 sends a command e to an input/output device (IO) 4.
After the processor (CPU) 1 sends the bus request signal a, the system bus handler (SBH)
The system bus 5 is in the state of normality check i.
will be occupied by the processor (CPU) 1, but the occupation time of the system bus 5 is mainly due to the bus request signal a sent by the processor (CPU) 1 being transferred to the system bus handler (SBH) 6 and the request signal being A transfer delay time until the state is in reception b, a transfer delay time until the command e sent by the processor (CPU) 1 is transferred to the input/output device (IO) 4 and the state is in command reception processing f,
It also depends on the transfer delay time until the response signal g sent by the input/output device (IO) 4 is transferred to the system bus handler (SBH) 6 and enters the normality confirmation state i.

The transfer delay time of the bus request signal a, command e, and response signal g is determined by the transfer delay time of the processor (CPU) 1 and input/output device (IO) connected to the system bus 5.
As the number of devices such as 2, 3, and 4 increases and the system bus 5 becomes longer and larger, there is a problem that the information transfer efficiency of the system bus 5 decreases.

An object of the present invention is to improve the information transfer efficiency of the common bus as much as possible even when the number of devices connected to the common bus increases and the common bus becomes long.

[0013]

Means for Solving the Problems FIG. 1 is a diagram showing the principle of the present invention. In FIG. 1, 100 is a plurality of devices forming an information processing system, and 200 is a common bus connecting the plurality of devices 100.

300 is a bus extension means provided according to the present invention.

[0015]

[Operation] The bus extension means 300 cascades a plurality of common buses 200 each connecting a predetermined number or less of devices 100, and the bus extension means 300 cascades a plurality of common buses 200 each connecting a predetermined number or less of devices 100. When information addressed to the device 100 connected to the bus 200 is received, the received information is transferred to the other common bus 200, and a response signal to the received information is returned to the one common bus 200,
One common bus 200 is released.

The bus extension means 300 is constructed by combining two sets of bus extension control circuits that terminate each common bus 200 connected in series, and each bus extension control circuit is connected to the common bus 200 that terminates. When the other bus extension control circuit sends out information addressed to the device 100 connected to the terminal common bus 200, the received information is transmitted to the other bus extension control circuit and the terminal is terminated. It is contemplated that a response signal to the information may be returned to the common bus 200, and the information transmitted from the other bus extension control circuit may be sent to the terminating common bus 200.

[0017] Therefore, the number of devices connected to a set of common buses is limited, and the common bus is prevented from becoming long, so the information transfer delay time on each common bus is shortened, and as a result, each common bus Information transfer efficiency on the bus is improved.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing an information processing system according to an embodiment of the present invention, and FIG. 3 is a diagram showing an example of the bus extension control circuit in FIG. 2. Note that the same reference numerals indicate the same objects throughout the figures.

In FIG. 2, the apparatus 100 in FIG.
and as the common bus 200, as in FIG.
Although a processor (CPU) 1, input/output devices (IO) 2, 3, and 4, and a system bus 5 are shown, in FIG. )2 system bus 51 connecting
and a system bus 52 that connects input/output devices (IO) 3 and 4, and are terminated by bus extension control circuits (BEX) 71 and 72, respectively.

Each bus extension control circuit (BEX) 71 and 72 is connected to each other by a cross bus 8.
It constitutes the bus extension means 300 in FIG. Each bus extension control circuit (BEX) 7 has a configuration as shown in FIG.

The information transfer process on each system bus 51 and 52 is similar to that illustrated in FIG. 5. 2, 3, and 5, for example, a processor (C
When the PU) 1 transfers a command e to the input/output device (IO) 4, it first sends a bus request signal a to the system bus 51.

The system bus handler (SBH) 61 receives the bus request signal a sent to the system bus 51, and when it enters the request signal acceptance state b, the system bus handler (SBH) 61
1 is analyzed, and if it is in a usable state, a bus request permission signal c indicating that the right to use the system bus 51 has been granted is sent back to the processor (CPU) 1 via the system bus 51.

When the processor (CPU) 1 receives the bus request permission signal c sent to the system bus 51, the processor (CPU) 1 performs (
When the permission signal is accepted (d), the input/output device (IO)
4 is sent to the system bus 51.

After the bus extension control circuit (BEX) 71 stores the command e sent to the system bus 51 in the system bus receive buffer (SBB) 751, the internal processing unit (IPU) 773 analyzes the destination of the command e. and input/output devices (I/O) connected to the system bus 52.
O) When the command e is identified as being addressed to 4, the command e is received and the command reception process f is entered, and a response signal g confirming the reception of the command e is sent to the response signal transmitter (ANS) 7.
72, returns the command e to the processor (CPU) 1 via the system bus 51, and stores the command e in the system bus receive buffer (SBB) 751.
Bus extension control circuit (BEX) 72 via crossing bus 8
Transfer to.

When the processor (CPU) 1 receives the response signal g sent to the system bus 51, it confirms that the command e has been normally received by the destination input/output device (IO) 4, and confirms the normality. The state becomes h.

On the other hand, the system bus handler (SBH) 61
When the processor (CPU) 1 detects that the response signal g has been sent to the system bus 51, it confirms that the processor (CPU) 1 has finished using the system bus 51 normally and enters the state of normality check i. ) regains the usage rights granted to 1 and prepares for the next bus usage request.

On the other hand, the bus extension control circuit (BEX) 72 stores the command e transferred from the bus extension control circuit (BEX) 71 via the cross bus 8 in the cross bus reception buffer (XBB) 761, and then internally Processing unit (IPU)
773, the destination of the command e is analyzed, and when the command e is identified as being addressed to the input/output device (IO) 4 connected to the system bus 52, a bus request signal a is sent to the system bus 52.

The system bus handler (SBH) 62 receives the bus request signal a sent to the system bus 52, and when it enters the request signal acceptance state b, the system bus handler (SBH) 62
Analyzes the usage status of the bus 52, and if it is available, sends a bus request permission signal c indicating that the right to use the system bus 52 has been granted, via the system bus 52, which is the source of the bus request signal a. Bus extension control circuit (BEX) 72
send it back to

The bus extension control circuit (BEX) 72 receives the bus request permission signal c sent to the system bus 52 , and when the permission signal is accepted d, the bus extension control circuit (BEX) 72 receives the bus request permission signal c sent from the bus extension control circuit (BEX) 71 . Input/output device (IO)
4 is sent to the system bus 52.

The input/output device (IO) 4 is connected to the system bus 5.
2 Analyzes the destination of the command e sent to IO and identifies it as the command e addressed to the own input/output device (IO) 4, receives the command e, enters the command reception process f, and confirms the reception of the command e. The response signal g is sent to the system bus 52.
via the bus extension control circuit that sends the command e (
BEX) 72.

When the bus extension control circuit (BEX) 72 receives the response signal g sent to the system bus 52, the command e transferred from the bus extension control circuit (BEX) 71 is sent to the destination input/output device (IO). 4, it is confirmed that it has been received normally, and the state becomes normality confirmation h.

On the other hand, the system bus handler (SBH) 62
When detecting that the response signal g has been sent to the system bus 52, the bus extension control circuit (BEX) 72 confirms that the system bus 52 has been used normally and enters the normality check state. Bus extension control circuit (BE
X) Recover the usage rights granted to 72 and prepare for the next bus usage request.

As is clear from the above description, according to this embodiment, the system bus 51 includes a processor (CPU).
1. Input/output device (IO) 2 and bus extension control circuit (B
EX) 71 is connected, and the system bus 52 has a bus extension control circuit (BEX) 72 and an input/output device (IO
)3 and 4 are connected, each system bus 51
The number of devices connected to system buses 51 and 52 is reduced compared to the number of devices connected to system bus 5 illustrated in FIG. Therefore, the transfer delay time of the bus request signal a, command e, and response signal g transferred on each system bus 51 and 52 is the same as the transfer delay time of the bus request signal a, command e, and response signal g transferred on the system bus 5 illustrated in FIG. This means that the signal is shortened compared to similar signals, and the information transfer efficiency on each system bus 51 and 52 is improved compared to the information transfer efficiency on system bus 5 illustrated in FIG.

It should be noted that FIGS. 2 and 3 are only one embodiment of the present invention, and for example, the bus extension means 300 connects the illustrated bus extension control circuits (BEX) 71 and 72 by a cross bus 8. is not limited to,
Although many other modifications may be considered, the effects of the present invention remain the same in any case. Furthermore, the information processing system that is the object of the present invention is not limited to what is shown in the diagram.
Many other modifications may be considered, such as cascading three or more sets of system buses 5 using two or more sets of bus extension means 300, but the effects of the present invention do not change in any case.

[0035]

As described above, according to the present invention, in the information processing system, the number of devices connected to a set of common buses is limited, and the common bus is prevented from becoming long. Information transfer delay time on the bus is reduced,
As a result, information transfer efficiency on each common bus is improved.

[Brief explanation of the drawing]

[Figure 1] Diagram showing the principle of the present invention

[Fig. 2] A diagram showing an information processing system according to an embodiment of the present invention.

[Figure 3] Diagram showing an example of the bus extension control circuit in Figure 2

[Figure 4] Diagram showing an example of a conventional information processing system

[Figure 5] Diagram showing an example of the information transfer process in Figure 4

[Explanation of symbols]

1 Processor (CPU) 2, 3, 4 Input/output device (IO) 5 System bus 6 System bus handler (SBH) 7 Bus extension control circuit (BEX) 8 Cross bus 71 System bus interface section (SBI) 72
System bus fault monitoring section (SBS) 73 Cross bus interface section (XBI) 74 Cross bus fault monitoring section (XBS) 75, 76 Reception buffer section 77 Internal control register section 100 Device 200 Common bus 300 Bus extension means 751 System bus reception buffer (SBB)752
System bus receive buffer control unit (SBC) 761
Cross bus reception buffer (XBB) 762 Cross bus reception buffer control unit (XBC) 771 Control register unit (CRG) 772 Response signal transmission unit (ANS) 773 Internal processing unit (IPU)

Claims (2)

[Claims] Claim 1: A plurality of devices (100) are connected to a common bus (2
00) and in which the devices (100) mutually transmit and receive information via the common bus (200), each of the plurality of common devices (100) each connecting a predetermined number or less A bus extension means (300) is provided for connecting buses (200) in cascade, and the bus extension means (300) is connected to one common bus (200) connected in cascade.
0), the received information is sent from the device (100) connected to the other common bus (200). A bus configuration method characterized in that the received information is transferred to the common bus (200), and a response signal for the received information is returned to the one common bus (200) to release the one common bus (200). 2. The bus extension means (300) is configured by combining two sets of bus extension control circuits that terminate each common bus (200) connected in cascade, and each of the bus extension control circuits received information addressed to the device (100) connected to the common bus (200) that is terminated by the other bus extension control circuit and sent from the device (100) connected to the common bus (200). transmitting the received information to the other bus extension control circuit;
The common bus (200) returns a response signal to the information to the common bus (200) that terminates, and the common bus (200) that terminates the information transmitted from the other bus extension control circuit.
2. The bus configuration system according to claim 1, wherein the bus configuration method is configured to transmit data to a bus.