JPS60178571A - Data transfer system - Google Patents

Abstract

PURPOSE:To recognize the occurrence of an error in its early stage to handle it by sending an error detection signal out of a reception-side information processor to a data transfer controller side before a request to send data from the reception-side information processor is ceased. CONSTITUTION:The bus between the data transfer controller 50 and the 1st information processor 1 is constituted by using a data error signal line 2a and a bus 2, and the bus between the data transfer controller 50 and the 2nd information processor 3 is composed of a data error signal line 4a and a bus 4. The data transfer controller 50 is provided with an error processing circuit 51. The error detection signal is sent out of a reception-side information processor to the data transfer controller 50 before the request to send data from the reception- side information processor is ceased, and the error processing circuit 51 performs error processing.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to a data transfer method, and in particular, in a data transfer method that transfers data in a handshake mode (or handshake method), the present invention relates to a bus configuration. It is easy to use and can be used quickly if a transfer error occurs on the lotus.
The present invention relates to a data transfer method that can perform error processing on tJf.

C. Prior Art and its Problems] FIG. 1 is a block diagram showing a conventional data transfer system that transfers data in handshake mode.

1.3 are respectively the 1st. As a second information processing device, the first information processing device 1 is connected to a data transfer control device 5 via a bus 2, and the second information processing device 3 is similarly connected via a lotus 4. has been done. Data exchange between the first information processing device 1 and the second information processing device 3 is performed via this data transfer control device 5.

Suppose now that data is transmitted from the first information processing device 1 to the second information processing device 3, the information processing device 1 of 111 sends out the data to be transferred and controls the data transfer. The device 5 receives this data and notifies the second information processing device 3 that there is a data transfer request.

The second information processing device 3 that has received the notification issues a data transmission request to the data transfer control device 5 at a predetermined timing, and transfers the predetermined data sent from the data transfer control device 5 to the bus 4. It is taken from.

Here, the data transfer control device 5 plays the role of a buffer between the bus 2 and the bus 4, and has registers and RAM.
Storage devices such as magnetic disk devices are used.

As an example of this data transfer, a sequence in which data is transferred from the data transfer control device 5 to the second information processing device 3 in handshake mode will be explained based on FIG. 2.

(2) The second information processing device 3 outputs a data transmission request signal 6 to the data transfer control device 5, which is a slave of the bus 4, on its control line.

■When the data transfer control device 5 receives the data transmission request signal 6, it transmits the corresponding data 8 onto the data line of the bus 4, and simultaneously outputs a response signal 7 indicating that the data 8 has been transmitted onto the control line. .

■The second information processing device 3 receives the response signal 7 on the control line sent together with the data 8, takes in the data on the data line of the bus 4, and when the data taking is finished, sends a data sending request signal 6. Terminate the output of .

(2) The data transfer control device 5 detects that the data sending request signal 6 on the bus 40 control line is no longer output, and ends outputting the data 8 and the response signal 7.

In this data transfer sequence, for example, even if the data transfer control device 5 sends the error-free data 8 onto the bus 4 in step (2), noise etc. may occur on the bus 4. or for some other reason, an error may occur, and the second information processing device 3 on the receiving side may receive the data with the error.

Therefore, an error is detected in the data 8 received by the second information processing device 3, but in this case, even if an error is detected, if the data is transferred in the handshake mode like this, In this case, it is not possible to immediately notify the data transfer control device 5 or the first information processing device 1, which is the sending side, of the error.

Therefore, conventionally, an information processing device that detects such an error on the bus (or a transfer error) sends a notification to other information processing devices or data transfer control devices that an error has been detected. , a method has been adopted in which a special bus for communication is provided between these devices in addition to the bus for data transfer.

However, in such traditional methods, data transfer is
Since it is necessary to provide a separate bus, not only does the circuit become complicated, but as shown in FIG. .3) When exchanging data in systems that are both connected via a data transfer control device, it is important to recognize which information processing device is currently the target of data transfer. Therefore, there is a drawback that it is necessary to provide various circuits for making such judgments in each information processing device.

[Purpose of the invention]

The present invention has been made in view of the shortcomings of the prior art. In addition to solving these shortcomings, there is no need to provide a special bus for error notification in the handshake mode, and the bus configuration can be improved. The object of the present invention is to provide a data transfer method that is simple and allows early error handling when a transfer error occurs on the bus.

[Key points of the invention]

A feature of the present invention for achieving such an object is that a plurality of information processing devices are connected to a data transfer control device,
In a system where data is exchanged in handshake mode between each information processing device via a data transfer control device, an error detection signal is sent from the receiving information processing device to the data transmission device before the receiving information processing device no longer requests data transmission. By sending the information to the transfer control device side, the occurrence of an error can be recognized as quickly as possible, and predetermined error processing can be carried out quickly.

The configuration is such that, in a data transfer method in which multiple information processing devices are connected to a bus via a data transfer control device and data is transferred in handshake mode, predetermined error processing is performed in response to an error detection signal. An error processing circuit is provided in the data transfer control device, and when the information processing device on the receiving side among the plurality of information processing devices detects an error in data, etc., it sends an error detection signal before ending the data transmission request. is sent to the error processing circuit.

With this configuration, it is possible to send an error detection signal to the data transfer control device before dropping the data transmission request, so the data transfer control device can immediately recognize the occurrence of the error in the transfer sequence in which the transfer error occurs. .

As a result, it becomes possible to perform error processing at an early stage, and the transmitting side information processing device can learn of the error through the data transfer control device. Therefore, there is no need to provide a bus specifically for error notification etc. between the information processing devices.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 4 is a block diagram of an embodiment of a data transfer system to which the present invention is applied, in which a plurality of information processing devices transfer data via a data transfer control device. Components that are the same as those shown in FIG. 1 are designated by the same reference numerals.

2a and 4a are data error signal lines provided in addition to the bus 2 or the bus 4, respectively, and these data error signal lines 2a and the bus 2 are used to control the data transfer control device 5.
0 and the first information processing device 1, the data error signal line 4a and the bus 4 constitute a data transfer control device 5.
0 and the second information processing device 3. The data transfer control device 50 is provided with an error processing circuit 51.

Here, the data error signal lines 2a and 4a transmit data transferred between the data transfer control device 50 and the first information processing device 1 or between the data transfer control device 50 and the second information processing device 3, respectively. This is a line for transmitting error signals for.

Here, to explain the process of transferring data from the first information processing device 1 to the second information processing device 3 as an example, first, the data transferred by the first information processing bag w1 is controlled by data transfer control. The data is sent to the device 50. Then, the data transfer control device 50 notifies the second information processing device 3 that there is a data transfer request.

Upon receiving this notification, the second information processing device 3 transmits the information to the data transfer control device 50 at a predetermined timing.
Make a request to send data to , and in huntshake mode,
Receives data transfer from the data transfer control device 50.

The second information processing device 3 then performs error detection on the received data. As a result, if no error is detected in the received data, processing is performed in the same sequence as the conventional one shown in FIG.

Meanwhile, in the process of transferring this data, the second information processing device 3
When an error is detected in the received data, an error detection signal 11 is sent to the data transfer control device 50 via the error signal line 4a according to the sequence shown in FIG.

The sequence is as follows: (1) The second information processing device 3 outputs the data transmission request signal 6 onto the control line of the bus 4 to the data transfer control device 50, which is a slave of the bus 4.

■When the data transfer control device 50 receives the data sending request signal 6, it sends the corresponding data 8 to the data line ``2'' of the bus 4, and at the same time sends the response signal 7 indicating that the data 8 has been sent to the control line. Output.

■The second information processing device 3 receives the response signal 7 on the control line sent together with the data 8, takes in the data on the data line of the bus 4, detects an error in the data, and sends the error detection signal 11 to the data. It is sent to the data transfer control device 50 via the error signal line 4a.

(2) After sending out the error detection signal 11, the second information processing device 3 finishes outputting the data sending request signal 6 after a certain period of time T.

■The data transfer control device 50 detects that the data transmission request signal 6 on the control line of the bus 4 is no longer output, and
At the same time as the output of the data 8 and the response signal 7 is finished, the error detection signal 11 is received by the error processing circuit 51 before the data transmission request signal 6 falls, and it is known that the data transfer is abnormal. Then, predetermined error handling is performed.

(2) The second information processing device 3 detects that the reception of the response signal 7 is completed and ends outputting the error detection signal 11.

Processing is performed according to the above sequence, but ■
The fixed time T is the period when the data transfer request signal 6 is transmitted in the data transfer control device 50 on the receiving side of the error detection signal
This is to ensure that the error detection signal 11 is determined before the reception of the error detection signal 11 is completed, and specifically,
Variations in bus 4 signal line propagation time, driver,
This is to compensate for variations in delay time of elements such as receivers.

Here, the error processing of the error processing circuit 51 involves storing error information and making it accessible in response to an error reference command signal from the first information processing device 1 on the transmitting side. If the error occurs in the first information processing device
Or, when the data transfer control device 50 retransmits the transferred data or a block of data and an error occurs again, the data transfer control device 50 sends the transferred data to the first information processing device l on the sending side. The first information processing device 1 on the transmitting side is immediately notified that an error has occurred via the data error signal line 2a, or when an error occurs without performing such retransmission processing. It's like giving a notification. Note that if the error can be recovered by retransmission processing, the error processing can be handled more quickly.

In the above, the second information processing device 3 is connected to the data transfer control device 5.
In the case where data is transferred from the second information processing device 3 to the first information processing device 1, the first information processing device 1 receives data from the data transfer control device 50. The same applies when receiving a transfer. In such a case, the error signal 11 is transmitted to the data transfer control device 5 via the data error signal line 2a.
0, and the second information processing device 3 on the transmitting side is notified of the error via the data error signal line 4a.

Next, a specific circuit for performing such processing will be explained.

FIG. 6 is a block diagram of a specific example of the error determination processing circuit of the second information processing device 3 for realizing the sequence shown in FIG. 5, and FIG. 5 is a block diagram of a specific example of a circuit 51. FIG. Note that the first information processing device 1 also includes a processing circuit that performs similar error determination, so a description thereof will be omitted.

In FIG. 6, reference numeral 12 denotes a data input section of the second information processing device 3, which receives transfer data 8 (see FIG. 5) sent to a data bus 8b of the bus 4. An error determination circuit 13 is connected to this data bus 8b, and performs an error determination on the data sent from the data transfer control device 50 on the data bus 8b by, for example, a parity check.

Here, when outputting a data transmission request, first
A control signal is output from the bus mask control circuit 18 of the information processing device 3, and the data transmission request flip-flop 19
cent. As a result, a data transmission request signal 6 (see FIG. 5) is outputted to one line 6b of the control lines of the bus 4. Then, the error determination circuit 13 receives the response signal 7 outputted from the data transfer control device 50 via one of the control lines 7b. Here, error determination circuit 1
3 takes in data 8 and checks it. If an error is detected in the data 8, the data error detection flip-flop 14 is set and the error detection signal 11 is output onto the error signal line 11b.

On the other hand, the response signal 7 is further input to a state change detection circuit 15 and an error determination delay circuit 16, respectively.

The error determination delay circuit 16 is for securing time until the error determination circuit 13 obtains the result of whether or not there is an error in the data. , error detection signal] is ANDed with the inverted signal of 1, the data sending request Flinopf L top 19 is reset, the output of the data sending request signal 6 is dropped, and the process is terminated. On the other hand, if an error is detected, the error detection signal is sent via the delay circuit 17 for compensating the data error detection signal after a certain delay time (corresponding to the certain time T in step 2 of the sequence in FIG. 5). 11, the data sending request flip-flop 19 is reset, the output of the data sending request 6 is dropped, and the process ends.

The state change detection circuit 15 detects the falling (or rising) state of the response signal 7 to detect that the response signal 7 has been dropped, and detects a data error when the response signal 7 has fallen. The flip-flop 14 is reset, and the output of the error detection signal 11 on the error signal line 11b is ended.

As a result of the above, processing accompanied by error detection is performed in the sequence shown in FIG.

Next, one specific example of the error processing circuit 51 in the data transfer control device 50 will be described with reference to FIG.

First, upon receiving the data transmission request signal 6 via one line 6b of the control signal lines on the bus 4, the pass slave control circuit 22 sends a response signal 7 and data 8 to one line 7b of the control signal lines. A process of outputting the data to the data line 8b via the data output unit 24 is performed. Here, the data sending request signal 6 is also supplied to the state change detection circuit 20b for the data sending request signal via the control signal line 6b.

The state change detection circuit 20b detects the falling (or rising) state of the data transmission request signal 6 to detect that the data request signal 6 has been dropped. Using this detection signal as a gate signal, the error detection signal 11 on the error signal line 11b is sent to the error information register 23b as error information via the AND circuit 21b according to the AND condition. moreover,
The state change detection circuit 20b inputs its output to the path slave control circuit 22, and notifies the path slave control circuit 22 that reception of the data transmission request signal 6 has been completed. As a result, in the hash slave control circuit 22,
The output of the response signal 7 and data 8 is finished.

Here, if the data error detection signal 11 is not output, error information is not set in the error information register 23b, but if the data error detection signal 11 is not output, error information is set in the error information register 23b. 1-, and predetermined error processing is performed.

Incidentally, the error signal line +1a is for the first information processing device 1, and the control lines 6a and 7a also correspond to the first information processing device. Further, the state change detection circuit 20a and the error information register 23a also correspond to the first information processing device I, and these are connected to the error signal line 11b.

These are similar to the control lines 6b and 7b, the state change detection circuits 12 & 20b, and the error information register 23b. Therefore, a description of its operation will be omitted.

Here, the error processing circuit 51 is connected to the state change detection circuit 20.
a, 20b, AND circuit 2] a, 21b.

It is composed of error information registers 23a and 23b, and may further include an error processing means.

With the above configuration, data is transferred between the data transfer control device 50 and the second information processing device 3, and between the data transfer control device 50 and the first information processing device 1, on the bus connecting them. Error signal 1j14a, 2a
By providing this, it is possible to immediately notify the error to the data transfer control device 50 that operates as a slave, and by writing the information to the error information register 23b or 23a, the first information on the transmitting side can be transmitted as necessary. It becomes possible to notify the processing device 1 or the second information processing device 3 of the error.

FIG. 8 is a block diagram of a data transfer method in which several information processing devices transfer data through one data transfer control device.

In the figure, 30, 31, 32, and 33 are information processing devices, respectively, and constitute a data transfer system that transfers data via the data transfer control device 50. and,
The information processing device 30.31 is connected to the data transfer control device 50 via the bus 9, and the information processing device 32.3
3 is connected to a data transfer control device 50 via a bus 10.

Here, the data error signal IJI9 includes a data error detection line 9a and a data error notification 1*9b,
The data error signal line lO is the data error detection line 10a.
and a data error notification line 10b. and,
The data transfer control device 50 is provided with an error processing circuit 51.

Now, to explain the data transfer operation with the information processing devices 30 and 31 as the sending side and the information processing devices 32 and 33 as the receiving side, the information processing device 32 or the information processing device 3
If an error is detected in the received data in step 3,
An error signal is sent to the data transfer control device 50 via the data error detection line 10a, and the data transfer control device 50
This is notified via the error processing circuit 5 to the corresponding one of the transmitting side information processing devices 30 and 3 via the data error notification line 9b.

FIG. 9 shows a block diagram of the error notification processing portion of the error processing circuit 51 when error information is notified to the information processing device on the sending side. Components that are the same as those shown in FIG. 7 are indicated by the same reference numerals.

In FIG. 9, 25 is a flag storage register provided corresponding to the information processing device number, and the error detection signal 11 sent to the error information register 23b via the data error detection line 10a and the flag storage register 25 are By sending the signal A to the AND circuit group 26,
Corresponding data error notification line 9bl of ND circuit group 26,
....

Error information is output to one of the data error notification lines 9bi, .

Note that when the information processing device 31 or 32 on the sending side performs data transfer, it sets the flag at the corresponding position of the flag storage register 26 to 1'' in accordance with its unique number (device address). It is something.

By doing this, the error information register 23b
In the transfer sequence in which the error occurred, the data error notification line 9b (
9b1. . . , 9bi, . . . , 9bn), the error can be notified to the corresponding information processing device.

By providing a data error notification line and providing direct notification in this manner, each information processing device can immediately receive information when an error occurs.

As described above, according to the present invention, errors during transfer can be stored in the data transfer control device, so that they can be referenced as needed. In particular, in the embodiment shown in FIG. 8, an information processing device that is not involved in the data transfer accesses the error information register to determine whether or not the data transfer of another information processing device has been performed normally. It is something that can be determined.

Further, in the embodiment, the error signal line is configured to be incorporated into the bus that connects the data transfer control device and the information processing device, but the error signal line is limited to being incorporated into the bus in this way. isn't it. Furthermore, the object of error detection is not limited to data.

Incidentally, the error notification to the information processing device on the transmitting side can also be performed by interrupt processing or the like via the lotus 4, for example, without using the dedicated data error notification line. Furthermore, the error detection line may be used bidirectionally.

Furthermore, when several information processing devices are connected to a data transfer control device, error information can be notified without providing individual error information notification lines as shown in FIG.
A corresponding information processing device may be notified by carrying a corresponding address signal on the address bus.

〔Effect of the invention〕

As described above, the present invention sends an error detection signal from the receiving information processing device to the data transfer control device before the receiving information processing device no longer requests data transmission, thereby preventing the occurrence of an error as soon as possible. Since the error is recognized and predetermined error processing can be carried out at an early stage, the data transfer control device can immediately recognize #12 that the error occurred in the transfer sequence in which the transfer error occurred.

As a result, it becomes possible to perform error processing at an early stage, and the transmitting side information processing device can learn of the error through the data transfer control device. Therefore, there is no need to provide a bus specifically for error notification etc. between the information processing devices.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional data transfer system that transfers data in handshake mode, and FIG.
Explanatory diagram of the handshake mode sequence, Part 3
The figure is an explanatory diagram of a conventional system in which a number of information processing devices exchange data together via a data transfer control device, and FIG. FIG. 5 is a block diagram of an embodiment of a data transfer system to which the present invention is applied. FIG. 5 is an explanatory diagram of the handshake mode sequence, and FIG. 6 is a second information processing that implements the sequence of FIG. FIG. 7 is a block diagram of a specific example of the error determination processing circuit of the device.
FIG. 4 is a block diagram of a specific example of an error processing circuit in a data transfer control device, and FIG. 8 is a block diagram of a specific example of an error processing circuit in a data transfer control device. FIG. 9 is a block diagram of the data transfer system in this case, and is a block diagram of the error notification processing portion of the error processing circuit. 1- first information processing device, 2. 4- Bus. 2a, 4a - data error signal lines. 3- second information processing device, 5.5 (1- data transfer control device, 51- error processing circuit; 6- data transmission request signal; 7- response signal; 8- data signal; 11- error detection signal. Patent Applicant Fuji Electric Manufacturing Co., Ltd. Fuji Facom Control Co., Ltd. Agent Patent Attorneys Tetsuya Mori, Patent Attorney Yoshiaki Naito, Patent Attorney Masaru Shimizu, Patent Attorney Nobuteru Kajiyama Figure 1 Figure 2 Figure 4 Figure 6 Figure 2 9 Eyes 25 23b

Claims (2)

[Claims] (1) In a data transfer method in which multiple information processing devices are connected to a bus via a data transfer control device and data is transferred in handshake mode, an error processing circuit that receives an error detection signal and performs predetermined error processing is provided. provided in the data transfer control device, and when an information processing device on the receiving side among the plurality of information processing devices detects an error in data, the error detection signal is transmitted to the error detection signal before terminating the data transmission request. A data transfer method characterized by sending data to a processing circuit. (2) Data transfer is performed with one of the multiple information processing devices acting as a mask and the data transfer control device acting as a slave, and the error detection signal is transmitted to one of the signal lines of the lotus that transfers data in handshake mode. 2. The data transfer method according to claim 1, wherein the data transfer method is transmitted via two channels.