JPS60134367A - Communication system between plural processors - Google Patents

Abstract

PURPOSE:To decrease invalid communication between processors by transmitting communication order re-request order for the processor which transmits the communication order to the self device. CONSTITUTION:Communication orders from order processors are received, and it is decided that they are the communication orders for the self device by a matching circuit 12. Then, the transmitter number is duted by a dute circuit 14, and an AND circuit 17 which corresponds to the transmission processor is conducted by the output of the dute circuit 14 and a busy tone 16. The orders are stored in a flip-flop 18. When a main control part 15 terminates the processing of the communication orders in processing, the output of an OR circuit 19 is tested, when it turns on, an output 20 is tested, and the number of the transmitter is discriminated. Then, an operation part 21 is operated, a bus format is formed, and the communication order re-request orders for communication order retransmission are transmitted.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a communication method between a plurality of processing devices, and more specifically, a method for reducing invalid communication between processing devices with fewer interface lines between the processing devices. It relates to a communication method between multiple processing devices.

[Background of the invention]

FIG. 1 is a diagram showing an example of a plurality of processing devices, and FIG. 2 is an explanatory diagram showing a conventional communication method in the plurality of processing devices shown in FIG. In FIG. 1, 1, 2.3 indicate processing devices, and A.

B indicates a communication order. Figure 2 shows communication order A,
An example of the timing when B is output from the processing device 1.2 to the processing device 3 is shown.
A case is shown in which communication order B is output from processing device 2 to processing device 3. In this case, since the processing device 3 is processing the communication order A, it returns a busy indication C to the processing device 2. Processing device 2 receives busy indication C and outputs communication order B again, but since processing device 3 is still processing communication order A, it receives busy indication Cf again. Then, when the processing device 6 outputs the communication order Ef again, it is accepted by the processing device 3 because the processing of the communication order A in the processing device 3 has been completed at this point.

As explained above, in the conventional communication method between multiple processing devices, if the processing time of the processing device 3 is long, the processing time of the processing device 2
This has the drawback that the same communication order is issued many times, resulting in a large amount of bus reservation between processing units.

In addition, in such a case, a method has been proposed in which the processing device 3 displays a processing in progress display to the processing device 2 to eliminate contention between the processing devices 1 and 2. When this happens, the disadvantage is that the number of interface lines between processing devices increases.

The above-mentioned drawbacks become more serious as the amount of sand in the processing equipment increases.

[Purpose of the invention]

The purpose of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and without increasing the number of interface lines between processing devices.
It is an object of the present invention to provide a more efficient and economical communication method between processing devices that reduces invalid communication between processing devices.

[Summary of the Invention] The communication method between a plurality of processing devices of the present invention is a communication method between a plurality of processing devices that sends and receives arbitrary communication orders to and from each other, and each processing device only sends and receives communication orders addressed to its own device. a first means for storing the reception of the communication order for each processing device that received and sent the communication order during the processing operation, and sending the communication order to the own device based on the storage result of the first means after the processing operation is completed. The present invention is characterized by comprising a second means for sending a communication order re-request order to the processing device.

[Embodiments of the invention]

The present invention will be explained in more detail below with reference to embodiments shown in the accompanying drawings.

FIG. 3 is a block diagram showing an example of a processing device implementing the communication method between a plurality of processing devices of the present invention. In FIG. 3, 11 is a common bus connecting between processing devices;
2 is a match circuit that detects a match between the receiving device number of the communication order from the common bus 1 and its own device number; 15 is a match signal output from the match circuit 12; here,
A communication order has a bus format as shown in FIG. 4, for example. 14 is a date circuit that dates the transmitter number when the coincidence signal 13 is output; 15;
is the main control circuit of the processing device, and is realized using a known microprogram control method. 16 is a busy signal output while the processing device is processing a communication order. 1
7, when a communication order from another processing device is received while the busy signal 16 is being output, and the match circuit 12 determines that the communication order is for the own device, the output of the dual circuit 14 is output. This is an AND circuit for identifying the processing device that received and output the communication order. Reference numeral 18 denotes a flip-flop which receives the output of the AND circuit 17 and stores the processing device that sent the communication order received during the busy period.

Here, the AND circuit 17 and the 7-lip flop 18 are as follows.

There are as many processing devices as there are processing devices that transmit communication orders to the own device. Reference numeral 19 denotes an OR circuit which performs the logical sum of the outputs of the flip-flop 18, and when it receives a communication order from SH1 while it is busy, it notifies the main control section 15 that the communication order has been received.

The output 2o of the flip-frog 18 is the main controller 1
5 is entered. The main control unit 15 outputs a busy signal 16 while processing a communication order, turns off the busy signal 16 when processing is completed, tests the output of the OR circuit 19, and tests the output 20 when it determines that a communication order has been received. This is used to identify the sending device number of the communication order. Further, 22 is a buffer register used when transmitting a communication order from the device composed of the arithmetic unit 21.

In the above configuration, when a communication order is received from another processing device and the match circuit 12 determines that the communication order is for the own device, the transmitting device number is dated in the date circuit 14 and the output of the dual circuit 14 is determined. AND circuit 1 corresponding to the busy signal 16 transmission processing device
7 becomes conductive and is stored in the flip-flop 18. When the main control unit 15 finishes processing the communication order that was being processed, the main control unit 15 tests the output of the OR circuit 19, and if it is on, tests the output 20 to identify the transmitting device number, and then 21 to create the bus format shown in FIG. 4, and transmit a communication order re-request order for retransmission of the communication order. As a result, the processing device corresponding to the booming transmitting device number sends out the communication order sent last time again.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the number of times of bus hold, which is a disadvantage of the conventional technology, can be reduced to two times: the communication order re-request order and the communication order that is sent again, thereby significantly reducing invalid communication. It is possible to reduce the amount of time the bus is held inactive, and to realize an efficient communication system between a plurality of processing devices. Furthermore, since signal lines such as busy signals are not required in this case, there is no need to increase the number of interface lines between processing devices, and a more economical communication system between a plurality of processing devices can be realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a system including a plurality of processing devices, FIG. 2 is an explanatory diagram showing a conventional communication method in the system including a plurality of processing devices shown in FIG. 1, and FIG. FIG. 4 is a block diagram showing an example of a processing device implementing the communication method between processing devices, and FIG. 4 is an explanatory diagram showing an example of a bus format of a communication order. 1+ 213...Processing device 11...Common bus 12
...Match circuit 14...Date circuit 15...
Main control circuit 16... Busy signal 17... AND circuit 18... Flip-flop 19... OR circuit
21... Arithmetic unit 22... Buffer register agent Akio Takahashi Figure 3, Figure 4 (2nd - Soto) (Zbij/卜)

Claims (1)

[Scope of Claims] A communication method between a plurality of processing devices that mutually sends and receives arbitrary communication orders, wherein each processing device transmits and receives arbitrary communication orders to and from each other. a first means for receiving only a communication order addressed to the own device during a processing operation and storing the reception of the communication order for each processing device that sent the communication; A communication method between a plurality of processing devices, characterized in that the communication method includes a second means for sending a communication order re-request order to the processing device that sent the communication order to the device.