JPS59114662A - Message transmitting device - Google Patents

Abstract

PURPOSE:To attain the broadcast communication with high efficiency and reliability for a composite processor system by confirming whether the reception signals corresponding to the number of processors of the reception side are counted. CONSTITUTION:When a processor 42 is incapable of receiving messages, a ready flag 304 of an adaptor 32 of the processor 42 is reset. The message transmitted from a processor 41 is not set to a reception register 302 of the adaptor 32, and no reception signal is produced from a reception signal generator 305. The processor 41 senses for a fixed period a reception counter circuit 306 of an adaptor 31 and detects the failure of transmission of messages. Therefore the processor 41 clears the circuit 306 of the adaptor 31 to transmit the message again. In this message transmission state, the message is sent again also to a processor 43 which received the message in a normal way.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a message transmitting device in a multiprocessor system. .

In recent years, so-called composite processor systems have been developed in various places, which combine multiple processors at low cost to realize a computer system with excellent reliability and high speed, and have achieved great results.

Such a complex processor requires a so-called broadcast communication function that allows one processor to simultaneously transmit the same data to all other processors. In other words, when a plurality of processors cooperate with each other to execute one job or task, synchronization among the processors is an essential condition.

Conventionally, this type of method involves transmitting data from one processor to all other processors once or several times, or transmitting data from one processor to each of the other processors one by one. There is a way to send a message while creating a link and confirming that the message has been sent.

In the former example, since the receiving state of the destination processor must be checked frequently, there is a high risk that the message may not be received or the message may be destroyed. Furthermore, the latter example has the disadvantage that the single feed efficiency is extremely poor.

SUMMARY OF THE INVENTION In view of the various drawbacks mentioned above, it is an object of the present invention to provide a message transmitting device that realizes an efficient and highly reliable broadcast communication means.

The details of the apparatus of the present invention will be explained below with reference to the drawings.

FIG. 1 is a block diagram of a message transmitting device showing an embodiment of the device of the present invention. The processors 41-4N are connected in parallel via respective adapters 31-3N, a data bus 10 for transmitting and receiving messages, and a control bus 20 for transferring control signals.

FIG. 2 is a diagram showing the configuration of an adapter constituting the message transmitting device. The adapter 30 has a transmission register 301,
It is composed of a reception register 302, a ready flag 304, a reception signal generator 305, a reception counter circuit 306, and a decoder 303. The transmission register 302 is a register for temporarily storing transmitted messages, and the reception register 302 is for storing transmitted data. The ready flag 304 is a flag indicating the data receivable state of the processor, and when the processor is in the receivable state, it is set by a ready flag set command from the processor, and when the processor is in the receivable state, it is set by a ready flag reset command from the processor. It is reset by

When the processor is in the reception state, the reception signal generator 305
When a message is sent while the ready flag 304 is reset, a reception signal is output to the control bus 20. After a processor transmits a message, the reception counting circuit 306 controls the control bus 20 when the receiving processor receives the message (i).
It processes the received signals sent through the .

The reception counting circuit 306 is capable of counting for a certain period of time after a message is sent, and the processor that sent the message checks the number of received signals corresponding to the destination processor. Furthermore, the decoder 803 decodes each scale command from the processor and generates various control signals for controlling each device in the adapter 1. Next, to explain the operation of the device of the present invention, the processor 41
An example is shown in which the same message is sent (i) to the processor 42 and the processor 43.

The processor 41 sets a transmission message in the transmission register 301 of the adapter 31, and further outputs a message transmission command. The message transmission command is subcoded by the decoder 303 of the adapter 31, and its control signal outputs the response of the transmission register 301 to the data bus 10 a:'1. If the processor 43 is ready to receive data, the ready flags 304 of the adapters 32 and 33 are set, and the message sent from the processor 41 is set in the reception register 302 of each adapter of the processors 42 and 43. be done. Accordingly, processor 42 and processor 43 receive messages from their respective receiving registers 30z in response to message input commands. On the other hand, the processor 41 that sent the message senses the reception counting circuit 306 of the adapter 31 for a certain period of time, checks whether the reception signal corresponding to the number of processors at the reception destination has been counted, and ends the message transmission. -) Mashi Processor 4
If the message is correctly transmitted from 1 to the processors 42 and 43, the reception counting circuit 306 in the adapter 33 of the processor 41 will indicate 2.

Next, a case will be described in which the processor 42 cannot receive signals in the example described above. In this case adapter 3 of processor 42
The ready flag 304 of No. 2 is reset, and when the message is sent from the processing device 41, the message is not stored in the receiving register 302 of the adapter 32 of the processing device 42, and the receiving signal is not sent from the receiving signal generator 305. Does not occur. The processor 41 is the reception counting circuit 3 of the adapter 31.
06 for a certain period of time to detect failure in message transmission.

Therefore, the processor 41 is connected to the reception counting circuit 3 of the adapter 31.
Clear 06 and send the message again. In this manner, the processor 42 is in a receivable state, and the above-described sea fencing is repeated as many times as necessary until the message is reliably received, and the message is transmitted from the processor 41. Note that in the message sending state, the message is normally sent again to the processor 43 that received the message.

In this case, the processor 43 receives the message from the processor 41 and executes the process instructed by the message.

Therefore, when the message is transferred to the processor 43 again, the processor 43 repeats the same process. This idea means synchronizing the processors.

In the above explanation, an example of one-to-two broadcast communication was shown between three processors, but one-to-two broadcast communication between N processors is
The same applies to the example of broadcast communication for pair (N-1).

Note that although the above explanation was limited to message transmission, there is no problem in using command information such as a control signal to replace the message.

Furthermore, when two or more processors perform broadcast communication as described above, message transmission is not completed. In this case, the transmitting processor itself may become the receiving processor after transmitting the message for a certain period of time.

Although the present invention does not describe a deadlock processing mechanism for the data bus 10, it is a matter of course that it is added in an actual device.

As described above, the present invention provides a message transmitting device that can realize efficient and highly reliable broadcast communication in data communication in a multiprocessor system, and is extremely effective in practical use.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a message transmitting apparatus according to the present invention, and FIG. 2 is a block diagram showing an adapter constituting the message transmitting apparatus according to the present invention. In the figure, 10... data bus, 20...
...Control bus, 31~3N...7
p-7' evening, 41-4N---processor, 30
1... Transmission data register, 302...
・Reception register, 303... Decoder, 304
... Ready flag, 305 ... Unauthorized signal generator, 306 ... Reception counting circuit. Figure 1 Figure 2

Claims (1)

[Claims] A plurality of processors are connected in parallel to a first bus for transferring information and a second bus for transferring control signals, and the plurality of processors are configured to send messages to each other via the first bus. The processor that has received the message transmitted via the first bus has the function of sending and receiving the message and the function of transmitting a reception signal to the processor that has transmitted the message via the second bus, and the processor When the same message is sent from one of the processors to all the other processors, the received signals from all the other processors are counted, and if the received signals are less than the number of processors, the same message is sent again. A message transmitting device whose characteristic is to continue transmitting the message until it receives the same number of reception signals as the number of message reception processors.