JPS62219056A - Data transmitter - Google Patents

Abstract

PURPOSE:To obtain a highly efficient device with high reliability by providing a transmitting and receiving part exchanging data between other processors through the 1st bus, an approval signal generation part transmitting an approval signal through the 2nd bus and an approval signal counting part and keeping transmitting data until the number of approval signals the same as processors is received. CONSTITUTION:Data transmitted from the 1st processor 41 is set to the reception registers (corresponding to a symbol 312) of adapters 32 and 33 in the 2nd and 3rd processors 42 and 43, and an adapter control part (corresponding to a symbol 313) checks the normalcy of the data. After the normalcy of the data is checked, the adapter control part generates a data reception interruption signal to the processors 42 and 43, and an approval signal generator (corresponding to a symbol 315) in each adapter transmits the approval signal to the 1st adapter 31 in the 1st processor 41 through a control bus 20. The approval signal counter 316 of the 1st adapter 31 in the 1st processor 41 counts the approval signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transmission device in a multiprocessor system.

In recent years, the development of so-called "compound processor systems", which combine multiple low-cost processors to realize a computer system with excellent reliability and high speed, has been carried out in various places, and has achieved great results.

Such a composite processor requires a so-called "broadcast communication function" that allows one processor to simultaneously transmit the same data to all other processors. In other words, when a plurality of processors cooperate with each other to execute one job or task, it is essential to synchronize each processor.

[Conventional technology]

Conventionally, this type of data communication method involves transmitting data from one processor to all other processors once or several times, or transmitting data from one processor to each of the other processors one by one. There is a method of creating a link for data transmission and confirming the data transmission while transmitting the data.

[Problem to be solved by the invention 3 In the former example where data is sent from one processor to all other processors, the reception status of the destination processor is not checked, so there is a high risk of data reception failure etc. was there. Furthermore, the latter example in which a transmission link is formed for each processor has the disadvantage that data transfer efficiency is extremely low.

An object of the present invention is to provide a data transmitting device that realizes a highly reliable broadcast communication means with good transfer efficiency.

[Means for solving problems]

The present invention includes a plurality of processing devices each connected in parallel to a first bus for transferring information and a second bus for transferring control signals, and each processing device is connected to a first bus for transferring information and a second bus for transferring control signals. a transmitting/receiving unit that exchanges data between other processing devices; and upon receiving data transmitted via the first bus, sends an approval signal to the processing device that transmitted the data via the second bus; an approval signal generating section for transmitting an approval signal; and an approval signal counting section for counting approval signals from all other processing devices when the same data is transmitted to all other processing devices; If the count in the unit is less than the acceptance signals of all the other processing units, it transmits the same data again and continues to transmit the data until it receives the approval signals of all the other processing units. It is characterized by continuous transmission.

〔Example〕

Hereinafter, details of the device of the present invention will be explained with reference to the drawings.

FIG. 1 is a configuration diagram of a data transmitting device showing an embodiment of the device of the present invention. In FIG. 1, N processors 41 to 4N (N is an integer of 2 or more) are connected to respective adapters 31 to 3.
A data bus (first
bus) 10 and a control bus (second bus) 20 for transferring control signals.

FIG. 2 is a configuration diagram of an adapter forming a part of the data transmitting device. For simplicity, only the first adapter 31 is illustrated, and the configurations of the other adapters are assumed to be the same. The first adapter 31 has a transmit register 313 . Reception register 31z, ready flag 314. Approval signal generator 316. Approval signal counter 31° and adapter control unit 31
Consisting of 3.

The transmission register 3L is a register for temporarily storing transmission data, and the reception register 312 is for storing reception data. The ready flag 314 is a flag indicating a data receivable state of the processor, and is set by a ready flag set command from the processor, and is reset by a ready flag reset command from the processor when data cannot be received. Approval signal generator 31
．． has a function of outputting an approval signal to the control bus 20 when the processor is ready to receive data, that is, when data is normally received with the ready flag 314 set. The acknowledgment signal counter 316 counts the number of acknowledgment signals sent from the receiving processor via the control bus 20 after transmitting data.

Next, in order to explain the operation of the device of the present invention, an example will be shown in which the same data is transmitted from the r-th processor 41 to the second processor 42 and the third processor 43.

The first processor 41 transmits the transmit register 31 . of the first adapter 31 . Sets the transmission data to , and outputs a data transmission command. The data transmission command is issued by the adapter control unit 31.
3, and the control signal is sent to the transmit register 3.
11 is output to the data bus 10. A second processor 42 and a third processor are connected in parallel to this data bus 10.
If the processor 43 is in a state where data can be received, the ready flags (corresponding to 314) of the second adapter 32 and the third adapter 33 are set, and the data transmitted from the first processor 41 is 2 processors 42
and the respective adapters 32 and 3 of the third processor 43
3 (corresponding to 31□), and the validity of the data is checked by each adapter control unit (corresponding to 31). Once the validity of the data has been checked, each adapter control section issues a data reception interrupt signal to each processor 42 and processor 43, and at the same time, an acknowledgment signal generator (corresponding to 31) in each adapter. An approval signal is then transmitted to the first adapter 31 of the first processor 41 via the control bus 20 . The approval signal counter 31b of the first adapter 31 of the first processor 41 is connected to the second processor 42 and the third processor 41.
The approval signals of the processors 43 are counted. The number of destination processors is set in advance in the approval signal counter 316, and when a predetermined value is counted, the first processor 4
1, a transmission completion interrupt signal is issued. This transmission completion interrupt signal causes the first processor 41 to interrupt the second processor 42.
Then, it is confirmed that the data has been transmitted normally to the third processor 43.

Next, a case will be described in which the second processor 42 cannot receive data from the first processor 41 in the above-described example. This means that the ready flag (corresponding to 314) of the second adapter 32 of the second processor 42 has been reset.
Or, the data sent from the first processor 41 fails the data validity check in the receiving register of the adapter 32 of the second processor 42. In this case, when data is transmitted from the first processor 41, the approval signal generator (corresponding to 31°) of the second adapter 32 of the second processor 42 does not generate an approval signal.
The approval signal counter 316 of the adapter 31 of the first processor 41 receives a count of only the approval signal from the third processor 43 . The approval signal counter 31 of this first adapter 31. If a predetermined acknowledgment signal is not returned for a certain period of time, it issues a data reception failure interrupt signal to the first processor 41. The first processor 41, which received the data reception failure interrupt signal, learns that the data transmission was unsuccessful and transmits data to the second processor 42 and the third processor 43 again. In this way, as many approval signals as the number of destination processors are returned. Continue to send data until

In the above explanation, there is a 1:2 ratio between the three processors 41 to 43.
Although an example of broadcast communication has been shown, an example of one pair (N-1) broadcast communication between N processors is also possible.

Although the above explanation was limited to data transmission, command information such as a control signal may be used instead of data. Furthermore, when two or more processors perform broadcast communication as described above, data transmission is not completed.

In this case, the transmitting processor itself may become the receiving processor after transmitting data for a certain period of time.

Note that in the present invention, the data bus 10 and the control bus 2
Although the 0 bus adjustment mechanism was not mentioned, it is a matter of course that it is added in an actual device.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to provide a data transmission device that can realize efficient and highly reliable broadcast communication in data communication in a multiprocessor system, and is extremely effective in practical use. It is.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a data transmission device according to the present invention, and FIG. 2 is a configuration diagram of an adapter that constitutes the data transmission device according to the present invention. 10...Data bus 20...Control bus 31-3N...Adapter 41-4N...Processor 31, , 31□...Register 313...Adapter control unit 314...Ready flag 31% ...Approval signal generator 31, ...Approval signal counter Patent attorney Yoshiyuki Iwasa -0
−2−”

Claims (1)

[Claims] (1) A plurality of processing devices are each connected in parallel to a first bus for transferring information and a second bus for transferring control signals, and each processing device is connected to a second bus for transferring control signals. a transmitting/receiving unit that exchanges data between the processing devices;
an acknowledgment signal generator that, upon receiving the data transmitted via the first bus, transmits an acknowledgment signal to the processing device that transmitted the data via the second bus, and to all other processing devices; and an approval signal counting section that counts approval signals from all of the other processing devices when the same data is transmitted, and the counting by the approval signal counting section is equal to or greater than the number of all of the other processing devices. A data transmitting device characterized in that if the approval signal is not met, the same data is transmitted again, and the data transmission device continues to transmit the data until the approval signals of all the other processing devices are received.