JPS6124739B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transmitting device in a complex processor system.

In recent years, so-called composite processor systems, which combine a plurality of inexpensive processors to realize a highly reliable and high-speed computer system, have been developed in various places, and the results are expected.

Such a complex processor requires a so-called broadcast communication function for simultaneously transmitting the same data from one processor to all other processors. In other words, when a plurality of processors cooperate with each other to execute a single job or task, synchronization among the processors is an essential condition.

Conventionally, this type of method involves transmitting data from one processor to all other processors once or several times, or transmitting data from one processor to each of the other processors one by one. There is a method to send data while creating a link for the purpose and confirming the data transmission.

The former example does not check the reception status of the destination processor, so there is a high risk of data reception failure, and the latter example has the disadvantage of extremely low transfer efficiency.

SUMMARY OF THE INVENTION An object of the present invention has been made in view of the various drawbacks mentioned above, and it is an object of the present invention to provide a data transmitting device that realizes an efficient and highly reliable broadcast communication means.

The details of the apparatus of the present invention will be explained below with reference to the drawings.

FIG. 1 is a configuration diagram of a data transmitting device showing an embodiment of the device of the present invention.

The processors 41 to 4N are connected to each adapter 31 to 4N.
3N, a data bus 10 for transmitting data, and a control bus 20 for transmitting control signals, each connected in parallel.

FIG. 2 is a configuration diagram of an adapter constituting the data transmitting device.

The adapter 31 includes a transmitting register 30 ₁ , a receiving register 30 ₂ , a ready flag 30 ₄ , an unacknowledged signal generator 30 ₅ , an unacknowledged signal register 30 ₆ , and a decoder 30 ₃ . The transmission register ₃₀₁ is a register for temporarily storing transmission data, and the reception register ₃₀₂ is for storing transmitted data. The ready flag ₃₀₄ is a flag indicating the data receivable state of the processor. When the processor is in a receivable state, it is set by a ready flag set command from the processor, and when it is in a receivable state, it is set by a ready flag reset command from the processor. It will be reset.

The unacknowledged signal generator ₃₀₅ outputs an unacknowledged signal to the control bus 20 when data is transmitted and the processor is in an unreceivable state, that is, when the ready flag ₃₀₄ is reset. The unacknowledged signal register ₃₀₆ is a register for storing an unacknowledged signal sent via the control bus 20 when data is not received after being transmitted. This unauthorized signal register ₃₀₆ can only be set for a certain period of time after data transmission, only for the unauthorized signal register ₃₀₆ included in the adapter of the processor that transmitted the data. Furthermore, the decoder ₃₀₃ decodes various commands from the processor and generates various control signals for controlling each device within the adapter.

Next, in order to explain the operation of the device of the present invention, the processors 41 to 42 and 43 will be described.
An example of transmitting the same data is shown below.

Processor 41 sets transmission data in transmission register ₃₀₁ of adapter 31, and further outputs a data transmission command. Data transmission command is from adapter 3
The control signal outputs the contents of _{the transmission register 301 to} the data bus 10. If the processor 42 and processor 43 are in a state where they can receive data, the adapter 3
The ready flags ₃₀₄ of the processor 2 and the adapter 33 are set, and the data transmitted from the processor 41 is set in the receive register ₃₀₂ of the adapter 42 and the processor 43, respectively. Therefore, the processors 42 and 43 input the respective receiving registers 30 _{to 2} according to the data input command.
Import data from. On the other hand, the processor 41 that sent the data senses the unauthorized signal register ₃₀₆ of the adapter 31 for a certain period of time to confirm completion of the data transmission.

Next, a case will be described in which the processor 42 cannot receive data in the example described above. In this case processor 4
The ready flag ₃₀₄ of the second adapter 32 has been reset, and when data is transmitted from the processor 41, the data is not set in the reception register ₃₀₂ of the adapter 32 of the processor 42, and an unauthorized signal generator ₃₀₅ sends an unapproved signal. A signal is output. This unacknowledged signal is returned to the adapter 31 of the processor 41 via the control bus 20 and sets the unacknowledged register ₃₀₆ of the adapter 31. The processor 41 uses the unapproved register 30 of the adapter 31.
₆ for a certain period of time to detect failure of data transmission.

Therefore, the processor 41 clears the unauthorized register ₃₀₆ of the adapter 31 and transmits the data again. In this manner, the processor 42 becomes ready to receive data, and the above sequence is repeated as many times as necessary until data is transmitted from the processor 41.

In this data transmission state, the data is normally transmitted again to the processor 43 that received the data. In this case, processor 43 receives data from processor 41 and executes processing instructed by the data.

Therefore, when data is transferred to the processor 43 again, the processor 43 repeats the same process. In other words, this idea means synchronizing the processors.

In the above description, an example of one-to-two broadcast communication between three processors has been shown, but the same applies to an example of one-pair (N-1) broadcast communication between N processors.

Note that although the above explanation was limited to the transmission of data, there is no problem in using command information such as a control signal instead of data.

Furthermore, when two or more processors perform broadcast communication as described above, data transmission is not completed. In this case, after transmitting data for a certain period of time, the transmitting processor itself becomes the receiving processor.

Although the deadlock processing mechanism for the data bus 10 has not been described in this explanation, it is a matter of course that it is added in an actual device.

As described above, the present invention provides a data transmitting device that can realize efficient and highly reliable broadcast communication in data communications in a complex processor system, and is extremely effective in practical use.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a data transmitting apparatus according to the present invention, and FIG. 2 is a block diagram showing an adapter constituting the data transmitting apparatus according to the present invention. In the figure, 10 is a data bus, 20 is a control bus, 31 to 3N are adapters, and 41 to 4N are
is a processor, 30 ₁ is a transmission data register, 3
0 ₂ is reception register, 30 ₃ is decoder, 30 ₄
is ready flag, 30 ₅ is unauthorized signal generator, 3
₀₆ is the unacknowledged signal register.

Claims (1)

[Claims] 1 A first bus that transfers information is connected in parallel to a second bus that transfers control signals through adapters connected to each of the plurality of processors, and each of the adapters has a transmission register that temporarily stores transmission data. A receiving register for storing transmitted data, a ready flag indicating a data receivable state of the processor, and an unacknowledged generator that returns an unacknowledged signal when data is transmitted when the ready flag is in an unreceivable state; When the same data is sent from the adapter to all the other processors, if one or more of the other adapters returns the unacknowledged signal, the same data is sent again and the unacknowledged signal is returned. A data transmitting device characterized in that the data continues to be transmitted until the data is used up.