JPS62219057A - Data transmitter - Google Patents

Abstract

PURPOSE:To obtain a highly efficient device with high reliability by providing plural processors connected to the 1st bus transmitting information and to the 2nd bus transmitting a control signal in parallel, returning a name inherent to the processor if transmitted data cannot be received and retransmitting the same data to the processor that returns its inherent name. CONSTITUTION:Data transmitted from the 1st processor 41 is set to the reception parts (corresponding to a symbol 311) of adapters 32 and 33 in the 2nd and 3rd processors 42 and 43 which fetch data on the reception part (corresponding to a symbol 311). If the 2nd processor 42 cannot receives the data, a decision part (corresponding to a symbol 315) checks the contents of the reception part (corresponding to the symbol 311) of the adapter 32, and outputs the name inherent to the 2nd processor 42 from a processor name transmission part (corresponding to a symbol 314) to a control bus 20. The 1st processor 41 senses a processor name register 313 in an adapter 31 and detects the failure of data transmission.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transmission device in a multiprocessor system.

In recent years, the development of so-called "compound processor systems", which combine multiple low-cost processors to realize a computer system with excellent reliability and high speed, has been carried out in various places, and has achieved great results.

Such a composite processor requires a so-called "broadcast communication function" that allows one processor to simultaneously transmit the same data to all other processors. In other words, when a plurality of processors cooperate with each other to execute one job or task, it is essential to synchronize each processor.

[Conventional technology]

Conventionally, this type of data communication method involves transmitting data from one processor to all other processors once or several times, or transmitting data from one processor to each of the other processors one by one. There is a method of creating a link for data transmission and confirming the data transmission while transmitting the data.

[Problem to be solved by the invention 3 In the former example where data is sent from one processor to all other processors, the reception status of the destination processor is not checked, so there is a high risk of data reception failure etc. was there.

Furthermore, the latter example in which a transmission link is formed for each processor has the disadvantage that data transfer efficiency is extremely low.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data transmitting device that realizes broadcast communication means with high transfer efficiency and high reliability.

[Means for solving problems]

The present invention includes a plurality of processing devices each connected in parallel to a first bus for transmitting information and a second bus for transmitting control signals, and each processing device is connected to a first bus for transmitting information and a second bus for transmitting control signals. a transmitting/receiving unit that exchanges data between other processing devices, and a processing device that transmits data via the second bus if the data sent via the first bus cannot be received; When the name transmitter sends a unique name and the same data is sent to all other processing devices,
a receiving unit that receives one or more names unique to the processing device sent back from all the other processing devices, and when the name unique to the processing device is returned, the name unique to the processing device is The method is characterized in that the same data is retransmitted to the processing device that sent it back, and the data continues to be sent until the name unique to the processing device is no longer returned.

〔Example〕

Hereinafter, details of the apparatus of the present invention will be explained with reference to the drawings.

FIG. 1 is a configuration diagram of a data transmitting device showing an embodiment of the device of the present invention. In FIG. 1, N processors 41 to 4N (N is an integer of 2 or more) are connected to respective adapters 31 to 4N.
3N, a data bus (first bus) 10 for transmitting and receiving data, and a control bus (second bus) 20 for transferring control signals.

FIG. 2 is a configuration diagram of an adapter forming a part of the data transmitting device. For simplicity, the first adapter 31
Only one adapter is shown in the figure, and the configurations of other adapters are assumed to be the same.

The first adapter 31 includes a receiving section 3t+, a transmitting section 31□, a processor name register 313, a processor name transmitting section 314. and determination unit 31. Consisted of.

Receiving section 31. is a register for storing transmitted data, and the transmitter 31. is a register that temporarily stores transmission data. Processor name register 313
stores the processor name sent from the processor that could not receive data, and stores multiple processor names in a stack structure. When the processor name transmitter 314 cannot receive data transmitted from another processor, it transmits a unique processor name to the destination processor. The determining unit 31° controls the entire adapter, that is, transmits and receives data.

It controls reception of processor names, transmission of processor names, etc.

Next, in order to explain the operation of the device of the present invention, the first processor 41 to the second processor 42 and the processor 4 will be described.
3 shows an example of transmitting the same data.

The first processor 41 sets transmission data in the transmission section 3b of the adapter 31, and further outputs a data transmission command. The data transmission command is issued by the determination unit 31 of this adapter 31.
The control signal outputs the contents of the transmitter 312 to the data bus 1◇ shown in FIG. On the other hand, if the second processor 42 and the third processor 43 are in a state in which data can be received, the reception units (corresponding to 311) of the second adapter 32 and the third adapter 33 are in a ready state, The data transmitted from the first processor 41 is set in the receiving section (corresponding to 311) of the adapter 32, 33 of each of the second processor 42 and the third processor 43.

Each receiving section 31. When the data is sent to each of the second . A data reception interrupt signal is generated to the third processors 42 and 43, and each processor 42, 43 receives data from the receiving section (corresponding to 311) of each adapter 32, 33 in response to the interrupt signal. On the other hand, the first processor 41 that sent the data
is the processor name register 31 of the first adapter 31
3 for a certain period of time to confirm the completion of data transmission, and clear the contents of the transmitter 31□.

Next, a case will be described in which the second processor 42 cannot receive data in the example described above. In this case, the processor name register (corresponding to 313) of the adapter 32 of the second processor 42 is cleared, and when data is transmitted from the first processor 41, the receiving section (corresponding to 311) of the adapter 32 of the second processor 42 A determining unit (corresponding to 31) checks the contents of the processor name, and a unique name of the second processor 42 is output to the control bus 20 from a processor name transmitting unit (corresponding to 314). This control bus 20
The processor name of the second processor 42 sent via the processor name is set in the processor name register 313 in the first adapter 31 of the first processor 41. The first processor 41 senses the processor name register 313 in the adapter 31 to detect failure in data transmission.

The first processor 41 detects failure of data transmission.
A data retransmission command is output to the first adapter 31. The data retransmission command of the first processor 41 is sent to the first adapter 31.
Determination unit 31. It is decoded by the determination unit 31. is processor name register 31. The contents are sent to the transmitter 31□ and outputted to the data bus 10, and a data retransmission signal is outputted to the control bus 20, respectively. In other words, data bus 1
0 contains the data of the content sent last time and the second processor 42.
The processor name will be output. Second processor 42
The determining section (corresponding to 315) of the second adapter 32 receives the data retransmission signal, and the receiving section (corresponding to 315) of the second adapter 32 receives the data retransmission signal.
, etc.) to verify the processor name and check the validity of the received data. If normal, the second adapter 32
generates a data reception interrupt signal to the second processor 42 as described above. In this way, the above-described sequence operation is repeated any number of times until the second processor 42 is in a receivable state and reliably receives data.

In the above explanation, there is a 1:2 ratio between the three processors 41 to 43.
Although an example of broadcast communication has been shown, an example of one pair (N-1) broadcast communication between N processors is also possible.

Note that although the above explanation was limited to data transmission, there is no problem in using command information such as a control signal instead of data. In addition, when broadcast communication as described above is performed from two or more processors,
Data transmission is not completed. In this case, the transmitting processor itself may become the receiving processor after transmitting data for a certain period of time.

Note that in the present invention, the data bus 10 and the control bus 2
Although the 0 bus adjustment mechanism was not mentioned, it is a matter of course that it is added in an actual device.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to provide a data transmitting device that can realize efficient and highly reliable broadcast communication in data communication in a multiprocessor system, and is extremely effective in practical use. be.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a data transmission device according to the present invention, and FIG. 2 is a configuration diagram of an adapter that constitutes the data transmission device according to the present invention. 10... Data bus 20... Control bus 31-3N... Adapter 41-4N... Processor 31,... Receiving section 312... Transmitting section 313... Processor name register 314... Processor name transmission section 31s...determination section

Claims (1)

[Claims] (1) A plurality of processing devices each connected in parallel to a first bus for transmitting information and a second bus for transmitting control signals; a transmitting/receiving unit that exchanges data between the processing devices;
If the data sent via the second bus cannot be received, a name transmitting unit sends a name unique to the processing device to the processing device that sent the data via the second bus, and to all other processing devices. a receiving unit that receives one or more names unique to the processing device returned from all the other processing devices when the same data is transmitted, and when the name unique to the processing device is returned, , a data transmitting device characterized in that the same data is retransmitted to the processing device that has returned the name unique to the processing device, and the data transmission device continues to transmit the data until the name unique to the processing device is no longer returned.