JPH0253816B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interprocessor communication system in a multiprocessor system.

For example, the conventional inter-processor communication method is
Only the bus connected between the processors allows
The communication was taking place.

In this case, when a processor to communicate occupies the bus, other processors have to temporarily suspend their processing until the bus becomes free.

Therefore, since the number of processors that can communicate with the system as a whole is limited, the processing capacity decreases.Also, since the sending processor determines the memory address of the receiving processor,
If the processor on the transmitting side was abnormal, there was a risk that the memory contents of the processor on the receiving side would be destroyed.

SUMMARY OF THE INVENTION An object of the present invention is to provide an inter-processor communication method that eliminates the drawbacks of the prior art described above, does not reduce processing performance, and does not adversely affect the processor and memory on the receiving side. It is in.

A feature of the present invention is that a communication mediating means, so-called handshake device, is provided between the processors constituting the multiprocessor, and its autonomous operation receives address information of the data to be transferred from the transfer destination processor, and based on this, the transfer destination The present invention is an inter-processor communication system that identifies a processor, takes in the data from the transfer source processor or its memory, and transfers the data to the transfer destination processor or its memory at a corresponding address.

In detail, by providing a handshake device for each processor, connecting each processor with an address and data bus, and connecting each handshake device with a data bus for transmission and reception. , each processor sends only a transfer request when transferring data, and thereafter allows each handshake device to autonomously transmit and receive data between the desired processors.

Embodiments of the present invention will be described below based on the drawings.

First, FIG. 1 is a system configuration diagram of an embodiment of the interprocessor communication method according to the present invention, and is for a multiprocessor system with a hierarchical structure.

Here, 1 is a main processor related to the processors constituting the multiprocessor, 2 is an attached main memory, 3 is a handshake device on the main processor side, and 4-1 to 4-n are the same. Handshake devices 5-1 to 5-n on each local processor side are local processors 6-n related to processors constituting a multiprocessor.
1 to 6-n are their attached local memories;
7 is a main address bus; 8 is a main data bus; 9 is a data bus for transmission and reception between the handshake devices on the main processor side and the local processor side; 10-1 to 10-n are local address buses; 11-1 to 11-n are local data buses, 12-1 to 12-n are transfer signal lines related to data transfer from the main processor side to the local processor side, and 13-1 to 13-n are Transfer permission signal lines 14-1 to 14-n are transfer signal lines related to data transfer from the local processor side to the main processor side, and 15-1 to 15-n are
This is the same transfer permission signal line.

The main processor 1 controls each local processor 5-1 to 5-n and causes them to execute a predetermined job.

In this case, it is necessary to send and receive data related to the job, and this is performed via the handshake devices 3 and 4-1 to 4-n.

First, a case will be described in which data is transferred from the main processor 1 to the local processors 5-1 to 5-n.

The main processor 1 sends the address information in the main memory 2 of the data to be transferred to the handshake device 3 via the main address bus 7, and immediately proceeds to execute other necessary jobs.

This address information is stored in each local processor 5.
-1 to 5-n are assigned unique values.

The handshake device 3 uses this address information to identify the local processor 5 to which data should be transferred.
-1 to 5-n are identified, and the relevant data is taken in from the main memory 2 via the main data bus 8.

Note that when a response to an interrupt request (details will be described later) to the local processors 5-1 to 5-n can be obtained immediately and the waiting time is short, the data to be transferred is not stored in the main memory 2. Alternatively, in parallel with this, the main processor 1 may directly send the data to the handshake device 3.

Here, for example, if the address information corresponds to the local processor 5-1, the handshake device 3 corresponds to the local processor 5-1.
For the handshake device 4-1 corresponding to 1,
A transfer signal is sent through the transfer signal line 12-1.

As a result, the handshake device 4-1 issues an interrupt request to the local processor 5-1, and when an interrupt response signal is returned, a transfer permission signal is sent to the handshake device 3 via the transfer permission signal line 13-1. send out a line.

When the handshake device 3 receives this signal, the handshake device 4 transfers the acquired data to be transferred via the transmission/reception data bus 9.
Send to 1.

The handshake device 4-1 identifies a physical address in the local memory 6-1 where the data should be stored from a part of the received data (for example, the first part thereof), and transfers the address information to the local address bus 10-1. local processor 5-1 via
The remaining data is designated as local memory 6-1 and stored therein via local data bus 11-1.

When the local processor 5-1 completes the job being executed, the local processor 5-1 stores the above data in the local memory 6-1.
1 and execute a predetermined job based on this.

In this way, the main processor 1 immediately moves on to executing another job after making a data transfer request, and the local processor 5-1 completes the job currently being executed before transferring data. job execution based on the data.

That is, data transfer from the main processor 1 is performed autonomously by the handshake devices 3 and 4-1, and the main processor 1 and local processor 5-1 are not bothered by the data transfer. , processing capacity will not decrease.

Note that other local processors 5-2 to 5-n
It can be easily understood from the above description that the same is true for both.

Further, when data is transferred from the local processors 5-1 to 5-n to the main processor 1, the same operation as described above can be performed in the opposite direction.

Next, FIG. 2 is a block diagram of an embodiment of each handshake device in FIG.
5-n shows data transfer to 5-n.

Here, 31 is an address decoder of the handshake device 3, 32 is a memory control circuit of the same, and 33
is the same transmission register, 34 is the data transmission circuit,
35 is the same interrupt circuit, 36-1 to 36-n are the same transfer control circuits, 41 is each handshake device 4
-1 to 4-n transfer signal receiving circuits, 42 is the same interrupt circuit, 43 is the address decoder, 44 is the same data receiving circuit, 45 is the same receiving register, 46
is the same memory control circuit, and other symbols are the same as those in FIG.

In the following, data transfer related to inter-processor communication will be explained in more detail.

The main processor 1 sends out a drive signal E and also outputs a drive signal E to the local processors 5-1 to 5-n.
The address information in the main memory 2 of the data to be transferred to (for example, 5-1) is sent onto the main address bus 7.

In the handshake device 3, the address decoder 31 is activated by the drive signal E, which takes in address information from the main address bus 7 and decodes it.

As a result, the memory control start signal MS is sent out to start up the memory control circuit 32, which causes the memory drive signal ME to be sent out to start up the main memory 2.

Further, the memory control circuit 32 takes in address information from the main address bus, thereby transmitting the data from the main memory 2 to the transmission register 33.
to be taken into.

On the other hand, transfer control circuit 3 corresponding to address information
A transfer start signal TS is sent to 6-1 to 36-n (for example, 36-1).

As a result, flip-flop FF1 of the transfer control circuit 36-1 is set, its output Q becomes a transfer signal indicating a transfer request, and the transfer signal line 12-1 is set.
The data is input to the transfer reception circuit 41 of the corresponding handshake device 4-1.

Furthermore, this transfer signal is input to the interrupt circuit 42, held there, and sent to the local processor 5-1.
Sends an interrupt signal INT to.

When the interrupt response signal INTAK is returned, the interrupt signal INT is stopped after a predetermined time period required by the local processor 5-1.

In response to the interrupt request, the local processor 5-1 sends a drive signal E to activate the address decoder 43 of the handshake device 4-1, and transfers the address information for accepting data to the local address bus 10-1. and send it to this.

The address decoder 43 decodes this,
Identifies that the transfer is allowed, thereby
In the transfer reception circuit 41, flip-flop FF2
is set, and a transfer permission signal is created by ANDing its output Q and the transfer signal, and is input to the transfer control circuit 36-1 of the handshake device 3 via the transfer permission signal line 13-1.

As a result, the gate of the data transmitting circuit 34 is opened, and the data in the transmitting register 33 is sent onto the transmitting/receiving data bus 9.

On the other hand, this transfer permission signal is transmitted to the transfer control circuit 36.
-1 delay circuit DL allows time for the data on the transmission/reception data bus 9 to stabilize, becomes a set signal through the cable driver DR of the data transmission circuit 4, is received by the cable receiver REC of the data reception circuit 44, and is sent to the reception register. 45.

Furthermore, the delay circuit DL takes a longer time and resets the flip-flop FF1.
Transfer signal is stopped.

The activated reception register 45 can now take in the data on the transmission/reception data bus 9 and temporarily store it.

On the other hand, the above set signal is the memory control activation signal.
MS, the memory control circuit 46 is also activated, and the drive signal ME is sent to activate the local memory 6-1, and at the same time, a part of the data input to the reception register 45 (for example, a predetermined bit at the beginning)
This is taken in and sent onto the local address bus 10-1 as address information in which the transfer data should be stored.

The memory control circuit 46 controls the reception register 45 to take in and send out the remaining data.

Thereby, the reception register 45 takes in predetermined data and sends it onto the local data bus 11-1.

As a result, the transferred data is transferred to the local memory 6.
-1 is stored at a predetermined address.

The transmission register 33 and the reception register 45 each have a predetermined number of bits, and transmit and receive the transfer data once or by dividing it into two or more times.

Since this is determined in advance, the memory control circuits 32 and 46 identify this and input the transfer end signal TE to the interrupt circuits 35 and 42, respectively, and the main processor 1 and the local processor 5- 1 to signal that the data transfer is complete.

In this case, the interrupt circuit 35 takes in the transfer permission signals corresponding to the local processors 5-1 to 5-n, and
Local processor 5-1 related to data transfer
The device number 5-n is sent onto the main data bus 8, and the main processor 1 is made aware of this.

The above has described the transfer of data from the main processor 1 side to the local processors 5-1 to 5-n, but the data transfer in the opposite direction can be performed in the same way using a similar circuit (not shown). It can be carried out.

In this case, address decoders 31, 43, memory control circuits 32, 46, and interrupt circuits 35, 42
etc., the same thing can be used for sending and receiving.

As described in detail above, according to the present invention, inter-processor communication can be performed autonomously using a handshake device without reducing the processing capacity of the processor due to the bus network.
In addition, by specifying the data storage address in the receiving processor using the address information in the transferred data, it is possible to prevent memory contents from being destroyed due to abnormal communication, improving the processing performance and reliability of multiprocessor systems. It has a remarkable effect on improving sexual performance.

[Brief explanation of the drawing]

FIG. 1 is a system configuration diagram of an embodiment of the inter-processor communication system according to the present invention, and FIG. 2 is a block diagram of an embodiment of each handshake device in FIG. 1. 1...Main processor, 2...Main memory, 3, 4-1 to 4-n...Handshake device, 5-1 to 5-n...Local processor, 6
-1 to 6-n... Local memory, 7... Main address bus, 8... Main data bus, 9...
Transmission/reception data bus, 10-1 to 10-n...Local address bus, 11-1 to 11-n...Local data bus, 12-1 to 12-n and 1
4-1 to 14-n...Transfer signal line, 13-1 to 1
3-n and 15-1 to 15-n...transfer permission signal line, 31...address decoder, 32...memory control device, 33...transmission register, 34...data transmission circuit, 35...interrupt circuit , 36-1~3
6-n...Transfer control circuit, 41...Transfer signal receiving circuit, 42...Interrupt circuit, 43...Address decoder, 44...Data receiving circuit, 45...Receiving register, 46...Memory control circuit.

Claims (1)

[Scope of Claims] 1. In an inter-processor communication method for a multiprocessor system in which data is transferred via a handshake device provided for each processor, each processor has a memory connected to its own processor via a bus, and the data transfer Each handshake device has means for sending address information of its own memory in which transfer data including the address of the memory of the previous other processor is stored and a transfer request signal to a handshake device corresponding to its own processor. , is connected to other handshake devices by a handshake signal line and a data bus, and has means for checking whether data can be transmitted and received with other handshake devices, and means for starting and stopping the transmission register and reception register based on the handshake signal. , a means for identifying the transfer destination processor based on the address information of the transfer data, a means for fetching the transfer data from the memory connected to itself into the transmission register, and a means for transferring the transfer data based on the transfer data received in the reception register. means for identifying the address of the previous memory; means for setting the address of the memory where the received transfer data is to be stored; interrupt means having a timing adjustment circuit for interrupts to the processor; and a transmission register for checking whether or not data transfer is possible. and a means for repeating the data transmission/reception sequence including activation/stopping of reception registers and timing adjustment of interrupts to the processor without intervention of the transfer requesting processor; 1. An inter-processor communication system characterized in that data transmission and reception between desired processors is performed without intervention from a processor requesting transfer.