JPS63181070A - Bus switching system - Google Patents

Abstract

PURPOSE:To rapidly switch a bus and to prevent the centralization of a bus switching completion signal by providing a means for previously storing delay information in a processor and a means for delaying the transmission of the bus switching completion signal based on the delay information stored when the bus switching is completed. CONSTITUTION:A bus switching signal is transferred to a bus switching control part 32 according to a signal split function and when the bus switching control part 32 receives the switching signal, it transmits a control signal to a bus switching part 31 to switch the bus. Then, the contents of a register 36 are read and when a time determined by the value elapses, the bus switching completion signal is transmitted to the bus 20 through a signal transmitting part 34 and the bus switching part 31. At this time, since the control signal for switching the bus has already transmitted to the bus switching part 31, the bus switching completion signal is switched and transmitted to a bus switching controller 10 through the currently used bus. Thereby, a receiving buffer 11 is prevented from being completely full to receive a receiving completion signal.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical field to which the invention pertains The present invention relates to a system in which a plurality of processing devices are connected via a plurality of buses. This invention relates to a bus switching method that implements a bus switching method.

(2) Prior Art FIG. 5 shows an example of the configuration of a system consisting of a bus switching control device that performs this type of bus switching and a plurality of processing devices, where 10 is a bus switching control device, 20 is a bus, and 30 is a The processing device 1) is a receiving buffer that receives the bus switching completion signal. In the conventional case.

The bus switching control device 10 sends a bus switching signal to the plurality of processing devices 30 all at once to instruct bus switching, and after the processing device 30 side performs bus switching, a bus switching completion signal is sent to the bus switching control device. By sending the data back to 10, the bus is switched. In this conventional method,
When a bus switching signal is sent, bus switching completion signals may be sent from multiple processing devices 30 all at once, resulting in a case where the reception buffer 1) of the bus switching control device 10 cannot receive all the bus switching completion signals. . For this reason, receiving buffers must be provided on multiple sides, which has the disadvantage of increasing the amount of hardware. Alternatively, in order to compensate for this drawback, methods are being considered in which the processing device 30 retransmits the bus switching completion signal, or the bus switching control device 1O retransmits the bus switching No. 13, but in either case, the processing becomes complicated. (3) Purpose of the Invention The present invention provides a bus switching method in which bus switching signals are sent all at once and bus switching is confirmed by a bus switching completion signal. An object of the present invention is to provide a bus switching means that prevents concentration of completion signals.

(4) Structure of the invention (4-1) Differences between the characteristics of the invention and the conventional technology The present invention has the following features:
A bus switching method is adopted in which the processing device receives a bus switching signal and performs bus switching, and then delays the transmission of a bus switching completion signal using delay information.The first embodiment uses delay information for advance processing. A storage means is provided for each device, and the second embodiment uses address information determined for each processing device as delay information, and the third embodiment uses delay information included in the bus switching signal. .

Conventional bus switching methods do not have a means to delay and send out the bus switching completion signal, and the bus switching completion signal is sent immediately after the bus switching is completed, so it is possible for the bus switching completion signal to concentrate on the bus switching control device. However, in the present invention.

The difference is that the bus switching completion signals are not concentrated because the bus switching completion signals are delayed and sent out based on delay information that differs for each processing device.

(4-2) Embodiment FIG. 1 shows a configuration example for explaining the first embodiment of the present invention (configuration corresponding to claim (1)). An example of a configuration is shown in which there are two buses, one of which is used for current use and the other one is used as a backup, and the bus switching signal is transferred using the same bus as one normal signal. In FIG. 1, a plurality of processing devices 30 and a bus switching control device 10 are connected by a bus 20. As shown in FIG. 31 is a bus switching section, 32 is a bus switching control section, 3G is a register for storing delay information, and 35 is a processing section. The register 36 stores delay information having different values for each processing device. Reference numeral 33 denotes a signal receiving section which has the functions of distinguishing between a normal signal and a bus switching signal and distributing the signal to the bus switching control section 32 and the processing section 35, and 34 is a signal transmitting section. The bus switching unit 31 is 1i
Normally, a signal is received from either of the two buses, and the received signal is transferred to the signal receiving section 33, and the signal from the signal transmitting section 34 is transferred to the signal specified by the control signal from the bus switching control section 32. It is sent to the bus 20 on the side.

Further, upon receiving the bus disconnection control signal from the bus switching control unit 32, the bus switching unit 31 receives only the signal from the designated bus and transfers the signal to the signal receiving unit 33, and also transfers the signal to the signal transmitting unit 34. The signal from the bus switching control unit 3
2 to the specified bus. Further, the bus switching section 31 enters a normal connection mode in which it receives a signal from either of the two buses and transfers the signal to the signal receiving section 33 in response to a control signal from the bus switching control section 32 .

Next, the operation when transmitting and receiving normal signals using this configuration will be explained. The normal signal from the bus 20 is transferred to the A3 receiving section 33 by the function of the bus switching section 31, and the signal distribution of the signal receiving section 33 is transferred to the processing section 35 by the function. Further, the normal signal transmitted from the processing section 35 is sent via the signal transmitting section 34 to the bus designated by the bus switching control section 32 by the function of the bus switching section 31.

Next, the operation when a bus switching signal is received will be explained. The bus switching signal received from the bus 20 is transferred to the signal receiving section 33 by the function of the bus switching section 31 no matter which bus it is received from. The bus switching signal is transferred from the signal receiving section 33 to the bus switching control section 32 by a function. When the bus switching control unit 32 receives the bus switching signal, it sends a control signal to the bus switching unit 31 to switch the bus, and reads the contents of the register 36.

When the time determined from the value has elapsed, a bus switching completion signal is sent to the bus 20 via the signal transmitting section 34 and the bus switching section 31. At this time, since the control signal for switching the bus has already been sent to the bus switching unit 31, the bus switching completion signal is sent to the bus switching control correction device 10 through the switched bus that is now in use. In addition, the normal signal from the processing unit 35 also receives the bus switching signal, and from the time when the bus switching control unit 32 sends the bus switching control signal to the bus switching unit 31, the bus switching signal is switched to the current bus. The signal is sent to the bus switching control device 10 through the bus switching control device 10.

Because it operates in this way, when the bus switching signal is sent from the bus switching control device 10, the bus switching is performed immediately, and the bus switching completion signal is delayed based on delay information that differs for each processing device. Therefore, it is possible to prevent bus switching completion signals from reaching the bus switching control device O in a concentrated manner, causing the reception buffer 1) to become full and making it impossible to receive reception completion signals.

Even when there are three or more buses and the bus switching signal is transferred using a bus different from the 3 normal No. 13 buses, the bus switching control unit 32 has a similar configuration to transfer the bus switching function for transferring the bus switching signal. By providing this in the bus switching unit 31, the bus for normal signal transfer and the bus for bus switching signals can be quickly connected and the bus switching completion signal S can reach the bus switching control device IO in a concentrated manner. It is possible to switch the bus without being unable to receive the bus switching completion signal.

FIG. 2 shows a configuration example for explaining the second embodiment of the present invention (configuration corresponding to claim (2)), in which there are two buses and the A configuration example is shown in which one is used as a current signal and the other one is used as a pre-zero signal, and the bus switching signal is transferred using the same bus as the normal signal.

The difference from the embodiment shown in FIG. 1 is that a register 36 for storing delay information is not provided, and the bus switching control section 32
After receiving a bus switching signal from 3 and sending a control signal to the bus switching unit 31, the signal receiving unit 33 reads the address, which is different for each processing device, and when a predetermined period of time has elapsed. , to send a bus switching completion signal to the bus 20 through the signal transmitting section 34 and the bus switching section 31.

With this configuration, normal signals can be transmitted and received similarly to the configuration shown in the drawing. That is, the normal signal from the bus 20 is transferred to the signal receiving section 33 by the function of the bus switching section 31, and the signal distribution of the signal receiving section 33 is determined by the function.
The data is transferred to the processing unit 35. Further, the normal signal transmitted from the processing section 35 is sent via the signal transmitting section 34 to the bus specified by the bus switching control section 32 by the function of the bus switching section 31.

When a bus switching signal is received, the bus switching signal received from the bus 20 is transferred to the signal receiving section 33 by the function of the bus switching section 31, regardless of which bus it is received from. The bus switching signal is transferred from the signal receiving section 33 to the bus switching control section 32 by a function. When the bus switching control section 32 receives the bus switching signal, it sends a control signal to the bus switching section 31 to switch the bus, reads out the address of the processing device existing in the signal receiving section 33, and reads out the address of the processing device existing in the signal receiving section 33. When the time determined from the value has elapsed, a bus switching completion signal is sent to the bus 20 via the signal transmitting section 34 and the bus switching section 31.
Send to. At this time, since a control signal for switching the bus has been sent to the bus switching unit 31, the bus switching completion signal is sent to the bus switching control device 10 through the switched bus that is now in use. In addition, the normal signal from the processing unit 35 also receives the bus switching signal, and from the time when the bus switching control unit 32 sends the bus switching control signal to the bus switching unit 31, the bus switching signal is switched to the current bus. The signal is sent to the bus switching control device 10 through the bus switching control device 10.

Because it operates in this way, when the bus switching signal is sent from the bus switching control device 10, the bus switching is performed immediately, and the bus switching completion signal is delayed based on delay information that differs for each processing device. Therefore, it is possible to prevent bus switching completion signals from reaching the bus switching control device 10 in a concentrated manner, causing the reception buffer 1) to become full and making it impossible to receive reception completion signals.

Even when there are three or more buses and the bus switching signal is transferred using two normal signals and a separate bus, the bus switching control unit 32 and the bus switching function for transferring the bus switching signal can be configured in a similar manner. By providing the bus switching section 31,
A bus for normal signal transfer and a bus for bus switching signals.
Switching can be performed quickly and without the bus switching completion signal reaching the bus switching control '2Tl 10 in a concentrated manner and making it impossible to receive the bus switching completion signal.

FIG. 3 is a configuration example of a bus switching signal in the third embodiment of the present invention (configuration corresponding to the description in claim (3)), in which one bus switching signal is transmitted by all processing devices. This shows an example of a configuration for receiving data and performing bus switching. The bus switching signal 4o has the device numbers and delay information of all the processing devices as data, and the delay sensitivity is configured to be different for each processing device.

FIG. 4 shows a configuration example for explaining the third embodiment, in which there are two buses, one of which is used for current use and the other one for use as a backup.

A configuration example is shown in which a bus switching signal is transferred using the same bus as nine normal signals.

The difference from the embodiments of the configuration shown in FIG. 1 and the configuration shown in FIG. 2 is that the processing device 130 does not have delay information.

The bus switching 'III control section 32 receives the bus switching signal 40.
When the bus switching signal is transferred from the signal receiving unit 33 to the bus switching unit 31, the bus switching control unit 32 reads delay information that matches the number of its own processing device from the data within the bus switching signal 4°, and transfers the delay information to the bus switching unit 31. After transmitting the bus switching signal J'1) 43, a bus switching completion signal is sent to the signal transmitting unit 34 when a time determined from the delay information read from the bus switching signal 4o has elapsed.
and the bus switching unit 3I to the bus 2o.

With this configuration, one normal signal can be transmitted and received similarly to the configuration shown in FIG. Further, when a bus switching signal is received, the bus switching signal received from the bus 2o is transferred to the signal receiving section 33 by the function of the bus switching section 31, regardless of which bus it is received from. The bus switching signal is transferred from the signal receiving section 33 to the bus switching control section 32 by a function.

When the bus switching control unit 32 receives the bus switching signal.

Sends a control signal to the bus switching unit 3I to switch the bus, reads delay information that matches the number of the own processing device from the data in the bus switching signal 4o,
When the time determined from the delay information has elapsed, a bus switching completion signal is sent to the bus switching side 2 via the signal transmitter 34 and the bus switching unit 31 through the bus 20 that has been switched and is now in use.
1) Sent to 1 device 1°. Further, the normal signals from the processing unit 35 are also switched from the time when the bus switching signal is received and the bus switching control unit 32 sends the bus switching control signal to the bus switching unit 31. It is sent to the bus switching control device 1o through the bus.

Because it operates in this way, when the bus switching signal is sent from the bus switching control device 10, bus switching is performed immediately, and the bus switching completion signal contains delay information that differs for each processing device in the bus switching signal. Based on this, the bus switching completion signal is delayed and sent out from the processing device 3o, so the bus switching complete signal reaches the bus switching control device 10 in a concentrated manner and is received by the bus switching control device 10.
(5) As described in detail of the invention, according to the present invention, the bus switching signal is sent from the bus switching control device to the processing device. 3 buses are quickly switched, and the bus switching completion signals from the plurality of processing devices are delayed by different times for each processing device and sent to the bus switching control device. This has the advantage that it is possible to realize a bus switching method that prevents bus switching completion signals from being concentrated on the bus control device, ensures that the bus switching completion signals are received, and ensures confirmation of bus switching with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a configuration example for explaining the first embodiment. FIG. 2 is a configuration example for explaining the second embodiment,
FIG. 3 is a configuration example of a bus switching signal for explaining the third embodiment, FIG. 4 is a configuration example for explaining the third embodiment, and FIG. An example of a system configuration in which switching control devices are connected via a bus is shown. lO... Bus switching side '4TB device, 1)... Reception buffer. 20...Bus, 30...Processing uU, 3t...Bus switching unit. 32... Bus switching control section, 33... Signal receiving section, 3
4... Signal transmission section, 35... Processing section, 36... Register. 40...Bus switching signal.

Claims (3)

[Claims] (1) Install multiple buses that connect multiple processing devices, provide a bus switching control device that controls switching of these buses, and send bus switching signals to multiple processing devices simultaneously from the bus switching control device. and when the processing device receives a bus switching signal, switches the connected bus, sends a bus switching completion signal to the bus switching control device, and receives the bus switching completion signal from all of the processing devices. In the bus switching method, the bus switching is completed by a means for storing delay information in the processing device in advance, and when the bus switching is completed, sending out a bus switching completion signal based on the stored delay information. 1. A bus switching method characterized by comprising: delaying means. (2) The bus according to claim (1), wherein address information determined for each processing device is used as the delay information of the processing device, and the bus switching completion signal is delayed based on the delay information. Switching method. (3) As the delay information of the processing device, the bus switching signal includes delay information as data, and the processing device is provided with means for reading the data, and the bus switching completion signal is delayed based on the data. A bus switching system according to claim (1).