JPS6155139B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information transmission device that transmits information to a plurality of information processing devices connected to a common bus, and particularly to a broadcast device that simultaneously transmits the same information to a plurality of information processing devices.

In information processing systems, it is often necessary to send the processing results of one information processing device to many other information processing devices. Particularly in a multiprocessor system including a plurality of processors, it is extremely important to report the status and processing results of each processor to an unspecified number of other processors. To achieve this, broadcast devices have been used to transmit the same information to an unspecified number of people who need it at once. However, conventional broadcasting devices have the following drawbacks.

1. Since the recipients of information are many and unspecified, the information transmitting side does not have a means to check whether the information has been received by all recipients.

2. Therefore, important communications that require confirmation that the information has been received by the recipient should be sent by means other than broadcast, or
Alternatively, it is necessary to provide a device that always receives broadcast communications with priority over all other communications.

In addition, in order to compensate for the shortcomings of this broadcast device, it is possible to implement a method in which the broadcast cycle does not end until all transmission targets have completed reception; During this time, the communication bus remains exclusive, and the operation of information transfer devices not related to broadcasting is also hindered.

Therefore, it is possible to simultaneously transmit information to an unspecified number of information processing devices, which are the target of transmission.
Moreover, the transmission source can detect whether or not all the targets have received the information, and if the information is not received by all the targets, it is possible to detect whether or not the information has been received by the target at the next opportunity. A broadcast device is required that is controlled so that only those who have not yet received the information receive it.

An object of the present invention is to simultaneously transmit the same information to an unspecified number of information processing devices to be transmitted, and to obtain a response from the transmission source as to whether or not the information processing device to be transmitted has received the information. It is an object of the present invention to provide an information transfer device that enables the information processing device to perform the above-mentioned information processing and that does not receive the same information twice even if the information is repeatedly transmitted until all the target information processing devices complete receiving the information.

According to the present invention, in an information transfer device including a common bus and a plurality of transmitting/receiving circuits connected between the common bus and an information processing device, each of the plurality of information transmitting/receiving circuits transmits the contents of the address bus when receiving information. The common bus includes an address bus, a transmission signal line, and a response signal line in addition to a data bus, and the receiving section of the transmitting/receiving circuit normally keeps the response signal line at a low level. When the transmitting signal line is energized by the transmitting section of the transmitting/receiving circuit, the address on the common bus and the contents of the address register of the own circuit match, or they do not match and the information connected to the own circuit is determined. An information transfer device is obtained which controls the response signal line to stop being held at a low level only when the processing device is capable of receiving information.

In the device according to the present invention, all data is assigned an address as an identifier, and information is transferred in pairs of data and address.

Now, when the receiving section detects that the transmission signal line goes low and broadcasting has started, it detects a mismatch between the contents of the address bus and the contents of the address register in its own circuit, and only when it is ready to receive the address. It sets the contents of the bus in the address register, receives the data, and then attempts to drive the response signal line high. However, the response signal line on the bus becomes high level only when all receivers connected to the bus set their response signal lines to high level. Therefore, when the response signal line becomes high level, the transmitter knows that all transmitter/receivers to which information is to be transmitted have finished receiving data and have finished setting the address registers, and ends information transmission. I can do it. If the response signal line does not become high level, it is known that there is a transmitting/receiving device to which reception has not been completed, and the same data is retransmitted with the same address. However, in this case, in the transmitter/receiver that has already received the data, the contents of the address bus and the contents of the address register in its own circuit match when retransmitting, so the data is not received and the same information is duplicated. It will never be received.

In this way, the transmitting side can finally complete the broadcast to all targets by repeatedly transmitting the same data with the same address until the transmission signal line becomes high level as a result of the transmission.

This operation is performed by setting the address that is sent as an identifier along with the data in the address register in the own device during broadcast reception, and checking whether the data that is being sent one after another has already been received. and when the response signal line cannot be received (at the time of negative response).
By energizing the signal to a low level, it is possible to notify the transmission source of the existence of a transmission target that cannot receive broadcast broadcast.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration of a composite processor system using the present invention.

Information transmitting/receiving circuit 1 connected to common bus 100
0 ₁ to 10 _o are information transfer devices according to the present invention,
A processor 2 is connected to each information transmitting/receiving circuit 10 via an internal bus 200.

The information transmitting/receiving circuit 10 includes a transmitting section 1 that operates independently.
_0A and a receiving section _10B .

Next, the operation when the information transmitting/receiving circuit ₁₀₁ broadcasts information distinguished by address "1" to ₁₀₂ to _10o will be described in detail with reference to FIGS. 2 to 4.

FIG. 2 shows a block diagram of the transmitting section _10A of the information transmitting/receiving circuit 10. When a transmission request is transmitted from the information processing device 2 through the transmission line 205 to the transmission control circuit 17 of the transmission unit _10A , the transmission control circuit 17
First, the gate signal control line 120 is energized and the transmission gate control circuit 20 is set. The control circuit 2
The output of 0 energizes the gate control line 123, opens the transmit data gate 18 and the transmit address gate 19, and puts the signals on the internal data bus 201 and the internal address bus 202 onto the data bus 101 and the address bus 102. At this time, it is assumed that the contents of the internal address bus 202 indicate an address used as an identifier for data to be broadcast, that is, "1". Next, the transmission control circuit 17 connects the address signal control line 12
1 and set the address signal circuit 21,
Its output forces address signal line 105 low for one bus cycle.

When the address signal line 105 becomes low level, the comparator 11 of the receiving section _10B shown in FIG. 3 compares the contents of the address bus 102 and the contents of the address register 24 of the receiving section _10B , and if they match, The selection signal line 111 is activated and the reception data gate 14 is activated.
to the internal data bus 201.

Now, the transmission control circuit 17 shown in FIG. 2 then energizes the transmission signal control line 122, sets the transmission signal control circuit 22, and similarly energizes the transmission signal line 103 to a low level only during the relevant bus cycle. do.
Mismatch response circuit 12 of the receiving section _10B shown in FIG.
When the transmission signal line 103 becomes low level,
The inverted output of the selection signal line 111 is sent to the non-selection response control line 112. In other words, if the receiving unit 10
When the content of the address register 24 of _B is already 1, the non-selection response control line 112 is activated, and the response circuit 13 is passed through the OR circuit 16 and the response control line 113.
Set. The inverted output of the response circuit 13 is connected to the response signal line 104 through an open collector gate, and in this case, the inverted output is as shown in FIG.
04, the response signal line 104 is set to high level. However, when the response circuit 13 of the other receiver _10B connected to the response signal line 104 is reset, the actual signal on the response signal line 104 is still at a low level as shown in FIG. 4 1104. .

If the address register 2 of the receiving section _10B is
When the content of 4 is not 1, the non-selection control line 112 is not activated, and the state of the response control line 113, which is the output of the OR circuit 16, depends on the end response control line 114. In other words, the confirmation response circuit 15
11 and the ready line 203 are both energized, the write line 204 is energized by energizing the transmission signal line 103 to a low level, and the information processing device 2
The contents of the internal data bus 201 are written to the internal data bus 201, the contents of the address bus 102 are written to the address register 24, and at the same time the end response signal line 11 is written to the address register 24.
energize 4. The response signal line 113 is thereby energized, the response circuit 13 is set, and the inverted output attempts to drive the response signal line 104 to a high level as shown at 3104 in FIG.

Now, when all the response circuits 13 connected to the common bus 100 are set in this way, the response signal line 104 becomes high level for the first time as shown in _FIG. It is known that the transmitting/receiving circuit that is the transmission target has completed reception.

At the end of each bus cycle, the transmit gate control circuit 2
0, the address signal control circuit 21 and the transmission signal control circuit 22 are reset, the gate control line 123 is energized, and the address signal line 105 and the transmission signal line 103 are
to a high level, and thus the response control line 113
is de-energized, the response circuit 13 is reset, and the response signal line 104 is held at a low level, ending the transmission of information.

If the bus cycle ends, response signal line 1
If 04 is still at a low level, the transmitter 10
_A transmits the same data and the same address again in the next bus cycle.

As described above, according to the present invention, even though it is a broadcast, it is possible to confirm that all transmitting and receiving circuits targeted for information transmission have received the information, and if not all targets receive the information, This makes it possible to realize an information transfer device that repeatedly transmits the same data on subsequent occasions until all targets have finished receiving it, and in which the receiving side does not receive the same data more than once.

This is particularly effective in distributed control multiprocessor systems.

[Brief explanation of the drawing]

FIG. 1 is an overall block diagram of an embodiment of the present invention, FIG. 2 is a detailed block diagram of the transmitting section of the transmitting/receiving circuit, FIG. 3 is a detailed block diagram of the receiving section of the transmitting/receiving circuit, and FIG. 4 is a detailed block diagram of the receiving section of the transmitting/receiving circuit. An example of a signal waveform is shown. In the figure, 1 is an information transfer device, 2 is an information processing device, 10 is an information transmitting/receiving circuit, 10 _A is a transmitter,
10 _B is a receiving section, 11 is a comparator, 12 is a mismatch response circuit, 13 is a response circuit, 14 is a reception data gate, 15 is an acknowledgment circuit, 16 is an OR circuit, 17
is a transmission control circuit, 18 is a transmission data gate, 19
is a transmission address gate, 20 is a transmission gate control circuit, 21 is an address signal control circuit, 22 is a transmission signal control circuit, 24 is an address register, 100 is a common bus, 101 is a data bus, 102 is an address bus, 103 is a transmission signal 104 is a response signal line, 105 is an address signal line, 111 is a selection signal line, 112 is a non-selection response control line, 113 is a response control line, 114 is a termination response control line, 120 is a gate signal control line, 121 is a Address signal control line, 12
2 is a transmission signal control line, 123 is a gate control line, 2
00 is an internal bus, 201 is an internal data bus, 20
2 is an internal address bus, 203 is a ready line, 20
4 indicates a write line, and 205 indicates a transmission line.

Claims (1)

[Claims] 1. In an information transfer device consisting of a common bus and a plurality of transmitting/receiving circuits connected between the common bus and an information processing device, each of the plurality of information transmitting/receiving circuits has an address to which the contents of the address bus are set when receiving information. The common bus includes an address bus, a transmission signal line, and a response signal line in addition to a data bus, and the reception section of the transmission/reception circuit normally keeps the response signal line at a low level, and the transmission/reception circuit When the transmission signal line is energized by the transmitter of the circuit, the address on the common bus and the contents of the address register of the own circuit match, or they do not match and the information processing device connected to the own circuit transmits the information. An information transfer device characterized by controlling the response signal line so as to stop keeping it at a low level only when reception is possible.