JPH01108660A - Data transmission equipment - Google Patents

Abstract

PURPOSE:To realize fast transmission and an arbitration mechanism with high reliability by performing arbitration at an arbitration control part corresponding to the delivery of a transmission permission signal from a data transmission path at an output side. CONSTITUTION:An arbitration control means 80 which performs the arbitration of a data transmission means having a contention detecting part 70 in sequence of the arrival order of data and so as to relax the residence of the data to the best when it occurs, and transmits the data in series to a transmission path at the output side is provided. The arbitration of plural transmission means having the contention detecting parts 70 is performed in sequence of arrival order of the data and so as to relax the residence of the data to the best when it occurs corresponding to the delivery of a transmission permission signal from a transmission path 100 at an output side. In such a way, it is possible to receive the data sent from a corresponding transmission path to the limit of the physical housing capacity of the transmission path, and to eliminate a delay time required for arbitration control, and to transmit the data sequentially to the transmission path at the output side within a transfer time proper to the transmission path.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a data transmission device, and particularly to a data transmission device that serially transfers data transmitted via a plurality of parallel input transmission paths to an output transmission path. This invention relates to improvements in data transmission devices.

<Prior Art> In a data processing device using an electronic computer or the like, a plurality of processing devices are coupled through communication using digital signals. When data processing is distributed and processed by multiple processing devices, the results obtained by each processing device are sent to a second processing device that is different from the group of processing devices, and this second processing device Now, we will execute the process using the multiple received results. For example, there is a device disclosed in Japanese Patent Application No. 61-17543.

<Problems to be Solved by the Invention> In each of the above-mentioned processing devices, the time required to process distributed data varies depending on the received data and the processing content required of the device, and As a result, data groups are not always transmitted in the same order and at the same time intervals. However, if the transmission path itself can have a buffer function that minimizes the retention of transmitted data groups caused by variations in processing time in the second processing device, the amount of hardware in the processing device can be reduced. be able to.

Therefore, the main object of the present invention is to be able to accept data transmitted through a plurality of parallel input transmission lines up to the capacity limit of the transmission line, and to output data in the order in which the transmitted data groups arrive. It is an object of the present invention to provide a data transmission device which can transmit data to a side transmission line, perform output arbitration when a group of transmission data is retained, and transmit the data to an output side transmission line.

<Means for Solving the Problems> The data transmission device according to the present invention can receive a plurality of parallel data up to the limit of the physical capacity of the transmission path. In addition, the data can be serially transmitted to the output transmission line in the order in which the data arrives, and if the data is accumulated, the accumulation can be alleviated as much as possible;
A data transmission means having a conflict detection function provided corresponding to each of two arbitrary sets of a plurality of parallel transmission lines, and a data transmission means having a conflict detection function provided corresponding to each of two arbitrary sets of a plurality of parallel transmission lines; It consists of a data transmission means having a detection function, and an arbitration control means for controlling the order in which data arrives, and when data is accumulated, performing arbitration to alleviate the accumulation as much as possible, and serially transmitting the data to the output side transmission line. Ru.

Function> The data transmission device according to the present invention controls a plurality of transmission means having a conflict detection function in response to a transmission permission signal sent from an output transmission path, in order to determine the order of data arrival and the data retention. In this case, arbitration is performed to alleviate the accumulation as much as possible, and data sent from the corresponding transmission line is accepted up to the limit of the physical capacity of the transmission line, and there is no delay time required for arbitration control. , can be sequentially transmitted to the output side transmission line within the transfer time specific to the transmission line.

<Example> FIG. 1 is a schematic block diagram of an embodiment of the present invention.

In the embodiment shown in FIG. 1, two data transmission paths +0
．． 20, 30, 40, and 50°60 are provided in parallel, and a conflict detection unit 70 detects whether the arrival time difference of data 2 and data 2, which are input to the data transmission paths 10 and 40, is within a certain time difference. If it is outside the range of a certain time difference, no time adjustment is performed, and if it is within the range of a certain time difference, time adjustment is performed. Pause until the In response to the transmission permission signal sent from the data transmission line +00, which is the output side transmission line, the arbitration control unit 80 arbitrates the output order according to the congestion of data on each of the parallel input side transmission lines. Output to transmission line +00.

Next, the specific operation of the embodiment shown in FIG. 1 will be explained. In the initial state, data transmission path 1 on the output side
00 is a state in which data can be received, and the ACK signal A
K100 is returned to the arbitration control unit 80. The arbitration control unit 80 receives AC from the data transmission line 100 on the output side.
Upon receiving the K signal AK100, the data transmission lines 30 and 60
ACK signals AK80 and AK60 are output to.

The ACK signals AK80 and AK60 are not allowed to be sent to the data transmission path 100 at the same time, but one of them is allowed to be sent to the data transmission path 100. In this embodiment, for example, consider a state in which the data transmission path 60 is permitted and the data transmission path 30 is prohibited.

When data arrives on the data transmission path 10, the data and transmission signal CIO are transmitted to the data transmission path 30 via the data transmission path 20, and the transmission signal CIO is also transmitted to the arbitration control section 80.

The arbitration control unit 80 confirms that there is no data on the data transmission path 60, and if there is no data, it allows the data transmission path 30 to transmit data to the data transmission path 100, and also allows the data transmission path 60 to transmit data. , data transmission line 100
Prohibit data transmission to. The data transmission path 30 transmits data to the data transmission path 100 because it is permitted to transmit data to the data transmission path 100 . Then, the data transmission line 10
0, an ACK signal AK30 is transmitted from the data transmission path 100 to the data transmission path 3 via the arbitration control section 80.
0 to permit data transmission from the data transmission path 30 to the data transmission path 60.

Next, when the data arrives on the data transmission path 40, the data and the transmission signal C20 are transmitted through the data transmission path 50,
While being transmitted to the data transmission path 60, the transmission signal C20 is also transmitted to the arbitration control section 80. In the arbitration control unit 80,
Confirm that there is no data on the data transmission path 30, and if there is no data, send the data transmission path 1 to the data transmission path 60.
00 is permitted, and the data transmission path 30 is prohibited from transmitting data to the data transmission path 100. The data transmission path 60 transmits data to the data transmission path 100 because it is permitted to transmit data to the data transmission path 100 . When the data passes through the data transmission path 100, an ACK signal AK60 is sent back from the data transmission path +00 to the data transmission path 60 via the arbitration control section 80, permitting data transmission from the data transmission path 60.

Next, a case where data 2 is input a little later than data 1 will be explained. When data arrives on the data transmission path 10, the transmission signal CIO is sent to the data transmission path 20.
The contention detection unit 7o temporarily stops the data 2 on the data transmission path 5o when data exists on the data transmission path 40 within a certain time difference, and the data 2 is sent to the contention detection unit 70. When passing through the data transmission path 2o, the data 2 that had been stopped on the data transmission path 50 starts moving. In this manner, the conflict detection unit 70 detects the degree of conflict between data 1 and data 2, and temporarily stops data arriving late on the data transmission path 20 or the data transmission path 50.
This prevents malfunctions in the arbitration control unit 8o.

FIG. 2 is a specific circuit diagram of an embodiment for arbitrating two independent data. First, the configuration will be explained with reference to FIG. The data transmission lines 10 to 30 and 40 to 60 in FIG. 1 are respectively composed of transfer control units 11 to 31 and 41 to 61 and data holding means I2 to 32 and 42 to 62. Transfer control units 11 and 21
, 81.4+.

51 and 61 each perform handshake transfer control by one transmission signal input, one transmission permission signal input, one transmission signal output, and one transmission permission signal output. However, the transfer control units 21 and 51 have an added function of forcibly prohibiting independent transfer control and not transmitting a transmission signal by inputting a transmission prohibition signal. Further, the transfer control unit 101 has a built-in function to perform a logical sum on two different transmission signal inputs, and the transfer control unit z
, at, 4+ and 61. FIG. 3 shows a detailed circuit of the transfer control sections II, 31, 41 and 61, FIG. 4 shows a detailed circuit of the transfer control sections 21 and 51, and FIG. 5 shows a detailed circuit of the transfer control section 101. The contention detection section 70 is composed of D-type flip-flops 71 and 72, inverters 73 and 74, and "AND" gates 75 and 76. The arbitration control unit 80
NAND' gates 81, 82, 88 and 84 and 'AND' gates 85 and 86 and D type flip-flop 8
7 and 88 and "Noah" gates 89 and 90.

Next, the operation of the embodiment shown in FIG. 2 will be explained.

In the initial state, the reset signal is transmitted to the transfer control unit 11.2.
1, 3], 4], 51.6+ and +01 and “and”
Gates 75, 76, 85 and 86 and "Nand" gates 82 and 83 are provided. As a result, the transfer control units 11, 21°3'l, 41, 5] and 61 are initialized, and their Q1 outputs are set to "H".
level, and the Q2 output also becomes "H" level. When the transfer control unit 101 is reset, the Q1 output becomes "H" level and the Q2 output becomes "L". The transfer control units 21 and 51 can inhibit data transmission to the next stage using an inhibit signal. Also, "Nando" Gate 82
The output becomes "H" due to the reset signal, and is input to the "NAND" gate 81 forming a flip-flop. The remaining inputs of the "NAND" gate 81 are all "H" since the transfer control unit 2, 31, 51 and 61 have been reset, and the output of the "NAND" gate 81 is "L".
++, and the previous flip-flop composed of "NAND" gates 81 and 82 becomes stable. The subsequent flip-flop consisting of "NAND" gates 83 and 84 receives the output of the previous stage, and the reset signal is input to the "NAND" gate 83, so the "NAND" gate 83
The output of the "NAND" gate 84 becomes "L", and the flip-flop at the subsequent stage also becomes stable. Since the output of the "NAND" gate 83 is given to the input of the "Noah" gate 89, the output of the "Noah" gate 89 is "L".
” and data transmission to the transmission line +00 is prohibited. Since the output of the “NAND” gate 84 is given to the input of the “Noah” gate 90, the output of the “Noah” gate becomes “
H” and enables data transmission to the transmission line 100.

In this state, when the data l is given to the data holding means 12 and the pulse signal CIO is given to the transfer control section 11, the transfer control section 11 changes the Q2 output of the transfer control section 21 to "
Since it is HI3, the Q1 output is set to “L” level,
The Q1 output of the transfer control section 11 is transmitted to the transfer control section 21 and becomes a clock pulse of the data holding means 12, and outputs the contents of data to Qi of the data holding means 12.

Since the Q2 output of the transfer control unit 31 is “H”, the transfer control unit 21 sets its Q1 output to the “L” level, and the Q1 output of the transfer control unit 21 is transmitted to the transfer control unit 31, and the data holding unit 22 clock pulses and outputs the contents of Qi of the data holding means 12 to Qi of the data holding means 22. In addition, the 01 output of the transfer control unit 21 and the Q2 output of the transfer control unit 31 become inputs to the NAND J gate 81, which changes the output of the NAND gate 81 from “H” to “L”. ” Gates 82 and 83
becomes the input. [NAND] Gate 82 has an input of "'L"
As a result, the output becomes "H" and stabilizes the flip-flop in the previous stage. Further, the output of the "NAND" gate 83 is changed from "H" to "L", and this output becomes the input of the "NAND" gate 84. Since the input of the "NAND" gate 84 becomes "LI+", the output becomes "H" and stabilizes the subsequent flip-flop.The "L" output of the "NAND" gate 83 becomes the input of the "NOR" gate 89, and transfers By activating the transmission permission signal from the control section 101, the Ql output of the transfer control section 31 is set to "L" level and is transmitted to the transfer control section 101. If the transmission permission signal AK is "'H", the transfer control section 101 Q1 output is “L”
At the same time, it becomes a clock pulse of the data holding means 102, and the contents of Di of the data holding means 102 are outputted to Qi.

During the period when the transfer control unit 31 is outputting to the transfer control unit 101, the output “H” of the NAND J gate 84 is held as the output of the subsequent flip-flop, and the “NOR” gate 9
0, so the output of the "Noah" gate 90 is IIL
” is held, and the output from the transfer control unit 61 to the transfer control unit 101 is prohibited, and the output of the D type flip-flop 88 is set to “L” by the output of the transfer control unit 31, so that the output of the data holding means 62 is Qi is set to high impedance so as not to collide with the Qi output of the data holding means 32.

Next, when the data 2 is given to the data holding means 42 and the pulse signal C20 is given to the transfer control section 41, the explanation of the operation accompanying the input of the data 1 described above is completely the same, so a description thereof will be omitted.

Next, a case will be described in which data 2 is input a little later than data lK after the initial state.

Data 1 is given to the data holding means 12, pulse signal CIO is given to the transfer control unit 11 and also given to the inverter 73, and the pulse signal CIO changes from "L" to "H".
”, data 2 inputted a little later than data 1 is given to the data holding means 42, and when the pulse signal C20 is given to the transfer control section 41, the D input of the D type flip-flop 72 becomes "L". Therefore, when the pulse signal CIO returns from "'L" to "H" again, the Q output is "
When the Q1 output of the transfer control section 11 is transmitted to the transfer control section 21, the pulse transmitted to the transfer control section 51 is stopped at the transfer control section 51 without being sent to the transfer control section 61. The output becomes "L 11" and sets the Q output of the D type Furinopunrosop 72, and the pulse that was stopped by the transfer control section 51 is allowed to transfer again and is transmitted to the transfer control section 61. Data 1 becomes data 2. The explanation will be omitted because the same explanation can be given for the case where the data is input a little later than the "NAND" gates 81 and 82 and the "NAND" gates. Flip-flops at gates 83 and 84 suspend late input data.

As described above, according to this embodiment, the transmission line 1 on the output side
When 00 is empty, if only data 1 exists and data 2 does not exist, data 1 is output sequentially,
If only data 2 exists and data 1 does not exist, data 2 is output sequentially. Furthermore, when data 1 and data 2 are transmitted at the maximum transfer capacity of the data transmission path, the data transmission path 100 cannot process them, so the data transmission paths 80, 20 and 10, and the data transmission path 60.
Data stays at 50 and 40. In this case, the data transmission path 30 and the data transmission path 60 alternately transmit data on each transmission path to the data transmission path 100.

<Effects of the Invention> As described above, according to the present invention, even when data on a plurality of parallel transmission paths is transmitted at arbitrary time intervals and asynchronously with each other, the transmission from the data transmission path on the output side is By performing arbitration in the control unit in response to the permission signal being sent, it is possible to accept up to the limit of the physical capacity of the transmission line, and the output side transmission line is completely free of the delay time required for arbitration control. can be transmitted sequentially. Therefore, a highly reliable arbitration mechanism can be realized along with high-speed transmission.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of an embodiment of the present invention. FIG. 2 is a detailed circuit diagram of an example in which data sent from two data transmission paths is transmitted to an output data transmission path. FIGS. 3, 4, and 5 are circuit diagrams of one embodiment of the transfer control section. In the figure, 10, 20, 30, 40, 50°60.1
00 is a data transmission path, 70 is a conflict detection section, 80 is an arbitration control section, 11, 21, 31, 41, 51゜61.101 is a transfer control section, 12, 22, 32゜42.52, 62, 1
02 is a data holding means, 71° 72.87.88 is a D type flip-flop, 73.74 is an inverter, 75
, 76 , 85. 86 is the "and" gate, 81, 8
2.88.84 indicates the "Nand" gate, and 89.90 indicates the "Noah" gate. Agent Patent attorney Takeshi Sugiyama (1 other person) R v, Figure 3 R1, Figure 5, Figure 4 Procedural amendment (method) % formula % 1, Indication of case 2, Name of invention data transmission Device 3, relationship with the case of the person making the amendment Patent Applicant Address: 22-22 Nagaike-cho, Abeno-ku, Osaka, Yumi 545 Name (504) Sharp Corporation Representative: Haruo Tsuji 4, Agent

Claims (1)

[Claims] 1. A data transmission device for serially transmitting a plurality of data transferred via a plurality of parallel input-side transmission paths to an output-side transmission path, the data transmission device comprising: a conflict detection means for detecting that two sets of data exist on arbitrary two sets of parallel transmission lines, and that arrival time differences between the two sets of data are within a certain time difference range; and the output. In response to a transmission permission signal being sent from the side transmission line, the data transmission means having the conflict detection means arbitrates the output order according to the congestion of data on each of the plurality of parallel input side transmission lines. , a data transmission device comprising: arbitration control means for transmitting data to the transmission path on the output side.