JPH11191073A - Pci bus processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform continuous operation of a system in accordance with a PCI specification by sending an address and command information stored in a storage register through a dedicated line connected only to a CPU when an abnormality request signal from the CPU is received. SOLUTION: An abnormality detection circuit 23 supervises transaction on a PCI and when it detects abnormality, it outputs an address and a request signal for command information which are stored in a hold register 22. When a storage register 24 inputs the request signal from the circuit 23, it stores the address and command information from the register 22. When a PCI bus interface 25 receives an abnormality detection request signal from the CPU, it outputs the address and command information which are stored in the register 24 onto the PCI bus. Because of such a configuration, when abnormality occurs, the CPU can specify the occurrence place and separate the abnormal part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention can realize continuous system operation while conforming to the PCI bus specification, and can avoid delays even when a large number of devices are connected to the PCI bus, thereby improving system performance. The present invention relates to a PCI bus processing device capable of improving the performance.

[0002]

2. Description of the Related Art FIG. 1 is a block diagram showing a PCI bus processing device connected to a PCI bus and its peripheral configuration. In the drawing, reference numeral 1 denotes a CP for executing error processing in a communication system.
U, 2 denotes a bus master that starts a transaction on the PCI bus 4, 3 denotes a bus slave that is a target of the transaction started by the bus master 2, 4 denotes 33 MHz
(Periphere) operating with a synchronous clock signal of
ral Component Interconnect
t) Bus. The address information and data information carried by the PCI bus 4 are 32 bits long, and these address information and data information are multiplexed on the same 32-bit bus. By multiplexing, there is no need to separate address lines and data lines,
This makes it possible to reduce the number of signals required in the environment of the PCI bus 4 as compared with other bus architectures.

The specification of the PCI bus 4 (PCI Lo)
cal Bus Specification Rev
In the specification 2.1), a master abort, a target abort, a parity error, and a system error are defined as abnormal states, and detection and reporting are optionally defined for each. Therefore, whether or not to perform detection and reporting and what information to collect depends on each PCI device. In the specification of the PCI bus 4,
The bus master 2 must repeatedly execute the transaction replied by the bus slave 3 until the transfer ends normally / abnormally.

A computer system usually includes a plurality of buses, and devices are connected to each bus in the system, and the devices communicate locally with each other via the buses. However, when a device connected to one bus needs to write information to or read information from a device connected to another bus, system-wide communication via a different bus is required. It is said. To enable system-wide communication between devices on this different bus,
Bridges are provided to adapt the communication protocol of one bus to another.

FIG. 15 shows, for example, Digital Equ.
FIG. 2 is a configuration diagram showing a PCI bus bridge of an IP Corp. In the figure, 10 is a PCI bridge body, 11 is a primary PCI bus, and 12 is a secondary P bus.
CI bus 13, arbiter for secondary PCI bus 12, 14 for PCI controller, 15 for primary PC
Reference numeral 16 denotes a data path in a direction from the I bus 11 to the secondary PCI bus 12, and reference numeral 16 denotes a data path in a direction from the secondary PCI bus 12 to the primary PCI bus 11.

Next, the timing of data transfer from the primary PCI bus 11 to the secondary PCI bus 12 will be described. FIG. 16 is a timing chart of data transfer from the primary PCI bus to the secondary PCI bus. PC
When the I-bridge main body 10 receives the address from the primary PCI bus 11 (CY2 in FIG. 16), the PCI controller 14 receives the transaction and determines whether or not the transaction should be transferred to the secondary PCI bus 12 (CY3 in FIG. 16). . If the transfer is to the secondary PCI bus 12, the subsequent data is received and stored in a buffer in the data path 15 in the direction from the primary PCI bus 11 to the secondary PCI bus 12 (CY4 to CY1 in FIG. 16).
3).

At the same time, the PCI controller 14 obtains the right to use the secondary PCI bus 12 by the arbiter 13 and issues a transaction to the secondary PCI bus 12 (CY5 in FIG. 16). However, in the opposite case, that is, in the case of transfer from the secondary PCI bus 12 to the primary PCI bus 11, a bus request is issued to the external arbiter, and data on the data path 16 in the direction from the secondary PCI bus 12 to the primary PCI bus 11 is transmitted. Transfer to the primary PCI bus 11.

[0008] In some fields, when an abnormality occurs in the system, a function that enables the system to operate continuously by specifying an abnormal part and isolating the part is required (for example, a server machine). Therefore, when the PCI bus 4 is applied to a system that requires continuous operation, information collection and
Storage was required.

Further, in a processing apparatus using the PCI bus 4, the connection of the PCI bus 4 is electrically limited to eight devices, and a load of two devices is required when the device is connected via a connector. Since four devices are limited and the number of connections is small, when connecting a large number of devices, the PCI bridge main body 10 must hierarchize.

[0010]

Since the conventional PCI bus processing device is configured as described above, the PCI bus
Is applied to a system requiring continuous operation, it is necessary to collect and store information. If any bus slave 3 in the system keeps returning a retry response due to an abnormality,
There are problems such as not only stopping the processing of the bus master 2 but also failing to detect the cause of the occurrence of the abnormality.

Further, the conventional PCI bridge main body 10 includes:
As described above, reception starts from one PCI bus 4, and a delay occurs for executing data to the other after the address determination and the processing of the other bus arbitration. In such a case, there has been a problem that the delay increases in proportion to the number of hierarchies passing through the bus slave 3 and the performance decreases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and is based on the PCI bus specification.
An object of the present invention is to provide a PCI bus processing device capable of realizing continuous operation of a system.

Further, the present invention relates to a method for connecting a large number of devices to a PC
An object of the present invention is to provide a PCI bus processing device that can avoid delay and improve system performance even when connected to an I bus.

[0014]

SUMMARY OF THE INVENTION A PCI bus processing device according to the present invention detects the start of a transaction on a PCI bus by a transaction start detection circuit, and when a detection signal from the transaction start detection circuit is received, The address and command information on the address / data line and the byte enable line on the PCI bus are held in a holding register. When a transaction on the PCI bus is monitored and an abnormality is detected, the address and command information stored in the holding register are stored. Is output by the abnormality detection circuit. When the request signal from the abnormality detection circuit is input, the address and command information from the holding register are stored in the storage register, and when the abnormality information request signal from the CPU is received, the storage is performed. Address and command stored in register Information by the PCI bus interface is obtained so as to output onto the PCI bus.

The PCI bus processing device according to the present invention
When an abnormal information request signal is received from the PU, the address and command information stored in the storage register are transmitted via a dedicated line connected only to the CPU.

The PCI bus processing device according to the present invention
The start of a transaction on the CI bus is detected by a transaction start detection circuit, and when this detection signal is received, the address and command information on the address / data line and the byte enable line on the PCI bus are held in a holding register, and the PCI A retry response detection signal is output when a retry response on the bus is detected, and an over signal is output from the retry error detection circuit when the detected number of retry responses exceeds the set number of retry responses. When the detection signal is input, the address and command information output from the holding register is stored in the retry register, and when the over signal from the retry error detection circuit is input, the address and command information output from the retry register are stored in the storage register. And CPU Upon receiving the et abnormality information request signal, it is obtained so as to output onto the PCI bus by the PCI bus interface address and command information stored in the storage register.

The PCI bus processing device according to the present invention comprises a first PCI bus and a second PCI bus having different bus protocols.
Arbitration with the bus and synchronization of the bus protocol are adjusted, and data transfer from the first PCI bus to the second PCI bus is performed by the bridge device.
If you have access to the bus, one PCI
Passing transmission data from the bus to the other PCI bus,
When only one of the PCI buses has the access right, the transmission data is received once, and when the access right of both PCI buses is obtained, the received data is transferred to the PCI bus which has obtained the access right. When a transfer signal is received, a switch is switched to a bridge device by a first path switch when a switch signal is received, and a switch is switched to a bridge device by a second path switch when a switch signal is received. When a value is detected and two path switches are switched in conjunction with each other, a switching signal is output by a switch switching control device.

The PCI bus processing device according to the present invention detects the value of the register of the PCI bus processing device located in the lower layer of the PCI bus processing device and changes the setting of the register of the PCI bus processing device.

The PCI bus processing device according to the present invention comprises a first PCI bus processing device having a different bus protocol depending on a bridge device.
The arbitration between the bus and the second PCI bus and the synchronization of the bus protocol are adjusted, and the data is transferred from the first PCI bus to the second PCI bus. The buffer device has access rights to both PCI buses. In this case, the transmission data from one PCI bus is passed to the other PCI bus, and if only one of the PCI buses has an access right, the transmission data is received once and both PCI buses are received. When the access right is obtained, the received data is transferred to the PCI bus from which the access right is obtained, and when the switch signal is received, the data is switched to the bridge device by the first path switch, and the switch signal is received. Then, the bridge device is switched to the bridge device by the second path switch, the address on the first PCI bus is detected by the address decoder, and the data is transferred to the second PCI bus.
Arbiter checks whether the second PCI bus is being used by a device, and the switch switching control device transmits data to the second PCI bus by the address decoder. A switching signal is output to the first path switch and the second path switch when it is determined that transfer to the bus is necessary and when the arbiter determines that the second PCI bus is being used by a device. It is something to do.

A switch switching control device of a PCI bus processing device according to the present invention determines whether or not to output a switching signal based on device information stored in a device information table and a result of address decoding by an address decoder. It was made.

In the PCI bus processing device according to the present invention, a plurality of PCI buses are connected to one bus changeover switch in a star configuration, and the device changeover switch is connected according to a transfer destination.
The CI bus is switched.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 2 shows P according to the first embodiment of the present invention.
FIG. 2 is a configuration diagram illustrating a CI bus processing device, in which FIG.
Reference numeral 0 denotes a PCI bus processing device according to the first embodiment of the present invention, which monitors a transaction on the PCI bus 4 shown in FIG. 1 and, when an abnormality occurs during the transaction,
The address and command information of the transaction are stored. A transaction start detection circuit 21 detects the start of a transaction on the PCI bus 4.
The bus signal FRAME # is input. Reference numeral 22 denotes a holding register for holding information on address / data lines and command / byte enable lines on the PCI bus 4;
The bus signals AD [31: 0] and C / BE [3: 0] are input.

An abnormality detection circuit 23 detects an abnormality on the PCI bus, and detects FRAME #, IR of the PCI bus signal.
DY #, DEVSEL #, TRDY #, STOP #, P
Input ERR # and SERR #. A storage register 24 has a validbit indicating whether or not the address is valid, and stores an address and command information when an abnormality occurs.
25 is a PCI bus interface, and all PCI bus interfaces
Input bus signal.

Next, the operation will be described. First, a schematic operation of the entire communication system will be described with reference to the configuration of FIG. First, the bus master 2 starts a transaction on the PCI bus 4 with respect to the bus slave 3 and, when an abnormality occurs during the transaction, reports the abnormality according to the PCI bus specification. Next, the PCI bus processing device 2
0 monitors a transaction on the PCI bus 4, and stores an address of the transaction and command information when an abnormality occurs during the transaction. And
When the CPU 1 receives the report of the abnormality on the PCI bus 4 from the PCI bus processing device 20, the CPU 1 reads the transaction information stored in the PCI bus processing device 20 by the PCI transaction and analyzes the contents of the abnormality and the module in which the abnormality has occurred. Disconnect the module from the system.

Next, the abnormal state defined in the PCI bus specification and the PCI bus processor 2 when the abnormal state occurs
The operation of 0 will be described. First, the operation of the PCI bus processing device 20 when a master abort (abnormal) occurs will be described with reference to FIGS. FIG. 3 is a timing chart showing an example of a master abort of the PCI bus processing device according to the first embodiment of the present invention. Bus master 2 at time T0
Initiates a transaction on PCI bus 4, P
The transaction start detection circuit 21 in the CI bus processing device 20 detects the start of a transaction at time T1. Then, the holding register 22 receives the signal from the transaction start detection circuit 21 and stores the address / command information at the time T1.

Next, the abnormality detection circuit 23 is connected to the PCI bus 4
The above transaction is monitored, and when a master abort occurs at time T2, the contents of the holding register 22 are stored in the storage register 24, and at the same time, validbit is made valid. Then, the CPU 1 receiving the report of the occurrence of the master abort on the PCI bus 4 reads the storage register 24 in the PCI bus processing device 20 via the PCI bus 4. The PCI bus interface 25 in the PCI bus processing device 20 receives the PCI read transaction from the CPU 1 and returns the value of the storage register 24 to the CPU 1 only when validbit is valid. On the other hand, valid
If the bit is invalid, “FFFFFFFFh” is returned.

A transaction on the PCI bus 4 when a target abort and a parity error occur will be described. FIG. 4 shows P according to the first embodiment of the present invention.
FIG. 5 is a timing chart showing an example of a target abort of the CI bus processing device, and FIG.
6 is a timing chart showing an example of a parity error of the PCI bus processing device due to the following. A transaction is started at time T0, address / command information is stored at time T1, and stored in the storage register 24 at time T2.

As described above, according to the first embodiment, the transaction start detection circuit 21
The start of the above transaction is detected and the holding register 2
2 holds the address / command information, and the abnormality detection circuit 2
3 detects an abnormality on the PCI bus 4 and
Stores the abnormality information, the CPU 1 can identify the abnormality occurrence location when the abnormality occurs,
Since the location where the abnormality has occurred can be separated, effects such as continuous operation of the system can be obtained.

Embodiment 2 FIG. 6 is a configuration diagram showing a PCI bus processing device and its peripheral configuration according to a second embodiment of the present invention. In the figure, the same reference numerals as those in the first embodiment denote the same or corresponding parts, and a description thereof will be omitted.
In the first embodiment, the PCI bus 4 is used when accessing the abnormality information. However, in the second embodiment, when the PCI bus 4 itself does not operate normally, an abnormality occurs. The case where the analysis of a part is possible is shown.
Reference numeral 30 denotes a PCI bus processing unit that monitors transactions on the PCI bus 4 and collects and stores information when an abnormality occurs. Reference numeral 31 denotes a dedicated line for accessing information in the PCI bus processing unit 30.

Next, the operation will be described. First, in FIG. 6, the bus master 2
When a transaction is activated on the bus 4 and an abnormality occurs during the transaction, the abnormality is reported to the CPU 1 in accordance with the specification of the PCI bus 4. Next, the PCI bus processing device 30 monitors a transaction on the PCI bus 4 and stores an address and command information of the transaction when an abnormality occurs during the transaction. On the other hand, when an abnormality is reported on the PCI bus 4, the CPU 1 reads the transaction information stored in the PCI bus processing device 30 via the dedicated line 31 and analyzes the contents of the abnormality and the module in which the abnormality has occurred. Disconnect the module from the system.

Next, the operation of the PCI bus processing unit 30 when a master abort occurs will be described with reference to FIGS. FIG. 7 is a configuration diagram showing a PCI bus processing device according to Embodiment 2 of the present invention. In FIG. 7, reference numeral 32 denotes a dedicated line I / F connected to the storage register 24.
First, when the bus master 2 starts a transaction on the PCI bus 4 at time T0, the transaction start detection circuit 21 in the PCI bus processing device 30 detects the start of the transaction at time T1. Then, the holding register 22 receives the signal from the transaction start detection circuit 21 and stores the address / command information at the time T1. Next, the abnormality detection circuit 23 monitors the transaction on the PCI bus 4 and, when a master abort occurs at time T2, stores the contents of the holding register 22 in the storage register 24.
And at the same time, validbit is made valid.
C receiving a report of occurrence of master abort on PCI bus 4
PU1 is a storage register 2 in the PCI bus processor 30.
4 is read via the dedicated line 31.

Next, the dedicated line I / F unit 32 in the PCI bus processing unit 30 receives the read access from the CPU 1 and stores the storage register 2 only when the valid bit is valid.
4 is returned to the CPU 1, and if the validbit is invalid, "FFFFFFFFh" is returned. Similarly, FIGS. 4 and 5 show transactions on the PCI bus 4 when a target abort and a parity error have occurred, respectively. The transaction starts at time T0 and starts at time T0.
The address / command information is stored at 1 and stored in the storage register 24 at time T2.

As described above, according to the second embodiment, the information in the PCI bus processor 30 can be read via the dedicated line 31, so that the CPU 1
Even when an abnormality occurs in the I bus 4, the location where the abnormality occurs can be specified, and the system can be continuously operated in a part other than the PCI bus 4, and the effect is obtained.

Embodiment 3 FIG. 8 is a configuration diagram showing a PCI bus processing device according to a third embodiment of the present invention. In the figure, the same reference numerals as those in the first and second embodiments denote the same or corresponding parts, and a description thereof will be omitted. . In the third embodiment, even if any target in the system continues to return a retry response due to an abnormality,
An embodiment in which an abnormality occurrence location can be analyzed will be described. 40 is P
When a state in which a retry response is continuously returned more than a set number of times on the CI bus 4 is detected, the PCI bus processing device determines that an abnormality has occurred and holds the abnormality occurrence information.

A retry error detecting circuit 41 monitors a transaction on the PCI bus 4 and detects that a retry has occurred.
IRDY #, DEVSEL #, TRDY #, STOP
#, PERR #, and SERR #. 42, a retry counter for holding the number of retry responses, 43
Is a threshold register for holding a threshold of the number of retries, and an appropriate value is set at the time of system initialization.
Reference numeral 44 denotes a retry register that holds the address of the transaction that has received a retry response.

Next, the operation will be described with reference to FIGS.
When the bus master 2 initiates a transaction to the bus slave 3 and the bus slave 3 responds retry, upon receiving the retry response, the bus master 2 once releases the bus and restarts the transaction from the bus arbitration. The transaction start detection circuit 21 monitors the transaction on the PCI bus 4 and, when a retry response is generated and the value of the retry register 44 is invalid,
At the same time that the value of the holding register 22 is stored in the retry register 44, the value of the retry counter 42 is incremented by one.

Next, the value of the retry counter 42 after the increment is compared with the value of the threshold value register 43, and
If the value is less than the value of the threshold register 43, the state is held. The retry error detection circuit 41 returns to the PCI bus 4
When a retry response is detected above, the retry register 44
Is valid, the value of the holding register 22 is compared with the value of the retry register 44, and only when the values match, the value of the retry counter 42 is incremented by one. If the values of the holding register 22 and the retry register 44 do not match, they are ignored.

Next, the value of the retry counter 42 after the increment is compared with the value of the threshold value register 43, and
If the value is equal to or larger than the threshold register 43, the value of the retry register 44 is stored in the storage register 24, and
enable alidbit. Further, the CPU 1 periodically reads abnormality information in the PCI bus processing device 40 via a PCI bus transaction. The PCI bus interface 25 receives the read access from the CPU 1 and returns the value of the storage register 24 to the CPU 1 only when validbit is valid. On the other hand, if the validbit is invalid, “FFFFFFFFh” is returned.

In the third embodiment, the case where the retry counter 42 and the retry register 44 are one set has been described.
In a system in which a plurality of transactions are retried, the same applies when a plurality of transactions are provided. Storage register 2
Although the information No. 4 is accessed via the PCI bus transaction, a system for accessing using the dedicated line 31 as described in the second embodiment can also be configured.

As described above, according to the third embodiment, when the PCI bus processing unit 40 detects a state in which the retry response is continuously returned on the PCI bus 4 for the set number of times or more, it is determined that an abnormality has occurred, and abnormality occurrence information is determined. Since the information is held, the CPU 1 can specify the location where the abnormality has occurred, and the location where the abnormality has occurred can be separated, so that the system can operate continuously.

Embodiment 4 FIG. FIG. 9 is a diagram showing a schematic configuration of a hierarchical PCI bus processing device, and FIG. 10 is a configuration diagram showing a PCI bus processing device according to a fourth embodiment of the present invention. In the figure, the first to third embodiments are shown.
The same reference numerals denote the same or corresponding parts, and a description thereof will not be repeated. 50 is a PC as a PCI bus bridge
An I bus processing device, 51 is a bridge device for adapting a communication protocol of the primary PCI bus 61 and a protocol of the secondary PCI bus 62, and 52 is a device for increasing an electric load connectable to a bus between the primary PCI bus 61 and the secondary PCI bus 62. This is a buffer device for logically passing through, and when having access rights to both PCI buses 61 and 62, one PCI bus 6
Transmission data from the other PCI buses 61 and 6
2, when only one of the PCI buses 61 and 62 has access right, the transmission data is received once, and when the access right of both PCI buses 61 and 62 is obtained, the transmission data is received. The data is transferred to the PCI buses 61 and 62 having the access right. 53 is the primary PC
A path switch (first path switch) for deciding whether to connect the I bus 61 to the bridge device 51 or the buffer device 52, and a secondary PCI bus 62
Is a path switch (second path switch) for determining whether to connect to the bridge device 51 or the buffer device 52.

Reference numeral 55 denotes a switch switching control device for controlling the path switches 53 and 54, which monitors the value of the register 56 and switches the path switches 53 and 54 in conjunction with each other. By performing write access to the register 56 in the processing device 50, control is performed by software. Reference numeral 56 denotes a register for controlling the path switches 53 and 54 from outside.
61 is a primary PCI bus (first PCI bus) connected to the bridge device 51 or the buffer device 52;
2, a secondary PCI bus (second PCI bus) connected to the bridge device 51 or the buffer device 52;
Is a PCI bus option slot.

Next, the operation will be described. First, when the bridge device 51 is selected, a transaction is received from one side, and after a bus request (arbitration) to the other side, a transaction is generated and transfer processing is performed. In this case, since the primary PCI bus 61 and the secondary PCI bus 62 are independent buses, they can operate independently. That is, the transaction in the primary PCI bus 61 and the transaction in the secondary PCI bus 62 can be executed simultaneously unless there is a transfer to each other's bus.

Next, when the buffer device 52 is selected, the synchronization signal and data bus of the primary PCI bus 61 and the secondary PCI bus 62 are connected to the buffer device 52.
Drive capacity is increased and connected. That is, each operation timing is only a delay of the buffer delay, and the clock timing operates as one bus. Therefore, the primary PCI bus 61 and the secondary PCI bus 62 cannot operate independently, but can communicate with many devices with the same performance as the one-layer bus.

As described above, according to the fourth embodiment, the connection modes having two features are changed to the path switches 53 and 5.
4, the optimal operation of the PCI bus 4 can be selected according to the processing purpose. Even when a large number of devices are connected to the PCI bus 4, delays are avoided and system performance is improved. And the like.

Embodiment 5 FIG. FIG. 11 is a configuration diagram showing a flow of setting of the PCI bus processing device according to the fifth embodiment of the present invention. In the figure, the same reference numerals as those in the first to fourth embodiments denote the same or corresponding parts. Description is omitted. In the fourth embodiment, the connection mode of the PCI bus 4 is selected by register access, but in the fifth embodiment, all connection modes are selected at once in a multi-layer structure. 65 is a host CPU, 66 is a PCI device that the host CPU 65 is trying to access, 67 is a PCI bus processing device to which the primary PCI bus 61 is connected, and 68 is a PCI bus processing device to which the secondary PCI bus 62 is connected. The configuration of the PCI bus processing devices 67 and 68 is the same as that of FIG.

Next, the operation will be described. First, when the host CPU 65 accesses a PCI device 66 several levels lower, the host CPU 65 sets a switch control register of a PCI bus processing device (PCI bridge) 68 on the same layer as the PCI device 66. At this time, the host CP
The register access transaction from the U65 is first sent to the primary PCI bus 61, and the PCI bus processing device (PC
I bridge) 67. Next, as a result of the address decoding, the PCI bus processing device 67 determines that the transaction is to be transferred to the secondary PCI bus 62,
While transmitting to the secondary PCI bus 62, it simultaneously detects that the access is to the switch control register of the lower layer bridge, changes the setting of its own register, and switches the switch. Then, the transaction sent to the secondary PCI bus 62 is received by the PCI bus processing device 68 connected to the secondary PCI bus 62,
The register is changed and the path switches 53 and 54 are switched.

As described above, according to the fifth embodiment, the PCI bus processing device 67 of each layer detects the switch control register access to the PCI bus processing device 68 of the lower layer, and the setting of its own register is changed. And the host CP
All the PCI bus processing units 6 passing through the path to the PCI device 66 in one transaction from the U65
Since the 7, 68 path switches 53 and 54 can be switched, even when a large number of devices are connected to the PCI bus 4, effects such as avoiding delay and improving system performance can be obtained.

Embodiment 6 FIG. FIG. 12 is a configuration diagram showing a PCI bus processing device according to Embodiment 6 of the present invention.
In the figure, the same reference numerals as those in the first to fifth embodiments denote the same or corresponding parts, and a description thereof will be omitted. In the fifth embodiment, the switching of the switches is performed by using a register, that is, the switching is performed by software. In the sixth embodiment, the switching is performed by hardware. 70 is a PCI bus processing device that switches the path switches 53 and 54 by hardware, 71 is a switch switching control device for controlling the path switches 53 and 54, and 72 is a primary PCI bus 61.
And an arbiter 73 for managing the ownership of the secondary PCI bus 62.

Next, the operation will be described. Host CPU
When an access to the lower layer bus occurs from 65 (see FIG. 11) and the PCI bus processor 70 receives the access, the address decoder 72 detects the transmission to the secondary PCI bus 62. At this time, the switch switching control device 71
Reports the usage status of the secondary PCI bus 62 to the arbiter 73
When there is no bus requester, the PCI bus processing device 70 switches the path switches 53 and 54 to the buffer device 52 and connects the primary PCI bus 61 and the secondary PCI bus 62 as one bus. When the secondary PCI bus 62 is in use when receiving from the primary PCI bus 61 or when switching to the buffer device 52, the secondary PCI bus 62 is used.
When the bus use request is issued from the device, the switch switching control device 71 switches the path switches 53 and 54 to the bridge device 51 so that the primary PCI bus 61 and the secondary PCI bus 62 can be used independently.

As described above, according to the sixth embodiment, the switching of the path switches 53 and 54 is performed by hardware, so that maintenance becomes unnecessary and
Since the switches can be controlled more frequently, even when a large number of devices are connected to the PCI bus 4, effects such as improvement in system performance and avoiding delay can be obtained.

Embodiment 7 FIG. FIG. 13 is a configuration diagram showing a PCI bus processing device according to Embodiment 7 of the present invention.
In the figure, the same reference numerals as those in the first to sixth embodiments denote the same or corresponding parts, and a description thereof will be omitted. In the sixth embodiment, the switching to the buffer device 52 is performed when the primary PCI bus 61 or the secondary PCI bus 62 is vacant. In the seventh embodiment, the optimum one is selected using the device information. Things. 80 is a bridge device 5 depending on device information.
1, a PCI bus processing device capable of switching between connection to the buffer device 52, a switch switching control device 81 for switching the path switches 53 and 54, an address 82 of the primary PCI bus 61,
9 is a device information table that specifies a target device from command information and stores information on whether to access the device to the bridge device 51 or to connect to the buffer device 52.

Next, the operation will be described. Primary P
The process up to the reception from the CI bus 61 and the monitoring of the usage status of the secondary PCI bus 62 is the same as in the sixth embodiment.
Thereafter, at the same timing as the address decoding, the PCI bus processing device 80 specifies the device from the address using the device information table 82, and selects the primary PCI bus 61 or the secondary PCI bus 62. For example, when the response speed of the target device is very low, if the path switches 53 and 54 are set to the buffer device 52 side, the upper bus also waits for a response until the response is completed, during which time it cannot be used for another access. In this case, the PCI
Switching the bus processing device 80 to the bridge device 51 and releasing the primary PCI bus 61 improves the overall performance.

In the case of a transaction suitable for storing data in a storage buffer, such as write access, to the same device, switching to the bridge device 51 is appropriate, and a response must be waited for, such as read access. In the case of a transaction, switching to the buffer device 52 is suitable. Such device-specific information is stored in the device information table 82, and an address signal and a command signal of the PCI bus 4 are input to output a switch determination signal. Switch switching control device 81
Switches the path switches 53 and 54 with reference to the device information table 82 at the time of the transfer request to the secondary PCI bus 62 by the address decoder and the timing of detecting the bus unused state by the arbiter 73.

As described above, according to the seventh embodiment, the connection to the bridge device 51 or the connection to the buffer device 52 can be switched depending on the device information. Since the device can be operated, even when a large number of devices are connected to the PCI bus 4, effects such as avoiding delay and improving system performance can be obtained.

Embodiment 8 FIG. FIG. 14 is a configuration diagram showing a PCI bus processing device according to an eighth embodiment of the present invention.
In the figure, the same reference numerals as those in the first to seventh embodiments denote the same or corresponding parts, and a description thereof will be omitted. Embodiments 4 through 7 are based on the primary PC
Although the I bus 61 and the secondary PCI bus 62 are connected, in the eighth embodiment, three or more buses are simultaneously controlled. 90 is a plurality of PCI buses 10
By performing switching management of 1, 102, and 103 at one place, the hierarchy becomes shallower, and a PCI bus processing device 91 that can be controlled more simply.
A bus changeover switch for selecting two of transmission and reception from 102 and 103; 92 is a buffer device 52 and a bridge device 5;
1, a device changeover switch 93 for specifying the target from the reception address and transferring the PCI bus 101,
This is an address decoder for selecting 102 and 103.

Next, the operation will be described. For example, PC
When a transaction occurs on any of the I buses 101, 102, and 103, one of the bus changeover switches 91 switches to accept the transaction. PCI buses 101, 102, and 10 for decoding received addresses by an address decoder 93 and transferring received data.
3 is specified, and the other of the bus changeover switches 91 is switched. This allows the PCI buses 101, 102,
103 is connected. Thereafter, the switching operation between the buffer device 52 and the bridge device 51 is in accordance with the fourth to seventh embodiments.

As described above, according to the eighth embodiment, by performing switching management of the plurality of PCI buses 101, 102, and 103 at one place, the hierarchy becomes shallower,
Since control can be performed more simply, even when a large number of devices are connected to the PCI bus 4, effects such as the ability to avoid delay and improve system performance can be obtained.

[0059]

As described above, according to the present invention, the PC
The start of a transaction on the I bus is detected by a transaction start detection circuit, and when a detection signal from the transaction start detection circuit is received, the address and command information on the address / data line and the byte enable line on the PCI bus are held. In a register,
When a transaction on the PCI bus is monitored and an abnormality is detected, a request signal for the address and command information stored in the holding register is output by the abnormality detection circuit,
When the request signal from the abnormality detection circuit is input, the address and command information from the holding register are stored in the storage register, and when the abnormality information request signal is received from the CPU, the address and command information stored in the storage register are stored. The system is configured to output to the PCI bus by the PCI bus interface, so that the CPU can identify the location of the occurrence of the abnormality when the abnormality occurs, and the system can be continuously operated because the location of the abnormality can be separated. There is an effect that can be.

According to the present invention, when an abnormality information request signal from the CPU is received, the address and command information stored in the storage register are transmitted via the dedicated line connected only to the CPU. So the CPU
Can identify the location of the abnormality even when an abnormality occurs in the PCI bus itself, and the system can operate continuously in a portion other than the PCI bus.

According to the present invention, the start of a transaction on the PCI bus is detected by the transaction start detecting circuit, and when this detection signal is received, the address and the command on the address / data line and the byte enable line on the PCI bus are detected. Hold the information in the holding register,
A retry response detection signal is output when a retry response on the PCI bus is detected, and an over signal is output from a retry error detection circuit when the detected number of retry responses exceeds a set number of retry responses. When the response detection signal is input, the address and command information output from the holding register is stored in the retry register, and when the over signal from the retry error detection circuit is input, the address and command information output from the retry register are stored in the storage register. When an error information request signal is received from the CPU, the address and command information stored in the storage register are output to the PCI bus by the PCI bus interface. Can be Apart because it becomes possible to Ri, the system has the advantage of being able to continuous operation.

According to the present invention, the arbitration between the first PCI bus and the second PCI bus having different communication protocols and the synchronization of the transmission / reception protocol are adjusted, and the data from the first PCI bus to the second PCI bus is adjusted. When the transfer is performed by the bridge device and the buffer device has the access right of both PCI buses, the transmission data from one PCI bus is passed to the other PCI bus, and one of the PC buses is transmitted.
If the user has only the I-bus access right, the transmission data is once received, and when the two PCI bus access rights are obtained, the received data is transferred to the PCI bus having the access right. When the switch signal is received, the first path switch switches to the bridge device. When the switch signal is received, the second path switch switches to the bridge device, and the value of a register to which external data can be written is detected. When the two path switches are switched in conjunction with each other, the switching signal is output by the switch switching control device, so that the optimal operation of the PCI bus can be selected according to the processing purpose, and a large number of devices can be used. Even when connected to a PCI bus, there is an effect that delay can be avoided and system performance can be improved.

According to the present invention, since the value of the register of the PCI bus processor located in the lower layer of the self is detected and the setting of the self register is changed, the path to the PCI device in one transaction is obtained. The path switches of all the PCI bus processing devices passing through can be switched, and even when a large number of devices are connected to the PCI bus, there is an effect that delay can be avoided and system performance can be improved.

According to the present invention, the first PCI bus and the second PCI bus having different bus protocols by the bridge device
The arbitration of the bus and the synchronization of the transmission / reception protocol are adjusted, the data is transferred from the first PCI bus to the second PCI bus, and if the buffer device has the right to access both PCI buses, The transmission data from one PCI bus is passed to the other PCI bus, and one of the PCI buses is transmitted.
When the user has only the bus access right, the transmission data is received once, and when the access right of both PCI buses is obtained, the received data is transferred to the PCI bus for which the access right has been obtained, and is switched. When a signal is received, the first path switch switches to the bridge device. When a switching signal is received, the second path switch switches to the bridge device. The address decoder detects an address on the first PCI bus. It is determined whether or not the data needs to be transferred to the second PCI bus.
It is checked whether or not the PCI bus of the second PCI bus is used by the device, and when the switch switching control device determines that the data needs to be transferred to the second PCI bus by the address decoder, Is configured to output a switching signal to the first path switch and the second path switch when it is determined that the switch is used by the device, so that maintenance is not required and the switch is controlled more frequently. Can be
Even when a large number of devices are connected to the PCI bus, there is an effect that delay can be avoided and system performance can be improved.

According to the present invention, it is configured to determine whether or not to output the switching signal based on the device information stored in the device information table and the result of the address decoding by the address decoder. The system can be operated well, and even when a large number of devices are connected to the PCI bus, there is an effect that delay can be avoided and system performance can be improved.

According to the present invention, a plurality of PCI buses
One bus changeover switch is connected in a star configuration, and the device changeover switch is configured to switch the PCI bus to be connected according to the transfer destination, so that the switching management of a plurality of PCI buses at one place makes the hierarchy shallow, Control can be performed more simply, and even when a large number of devices are connected to the PCI bus, there is an effect that delay can be avoided and system performance can be improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a PCI bus processing device connected to a PCI bus and a peripheral configuration thereof.

FIG. 2 is a configuration diagram showing a PCI bus processing device according to the first embodiment of the present invention.

FIG. 3 is a timing chart illustrating an example of a master abort of the PCI bus processing device according to the first embodiment of the present invention;

FIG. 4 is a timing chart illustrating an example of a target abort of the PCI bus processing device according to the first embodiment of the present invention;

FIG. 5 is a timing chart showing an example of a parity error of the PCI bus processing device according to the first embodiment of the present invention.

FIG. 6 is a diagram showing a PCI bus processing device and its peripheral configuration according to a second embodiment of the present invention;

FIG. 7 is a configuration diagram showing a PCI bus processing device according to a second embodiment of the present invention.

FIG. 8 is a configuration diagram showing a PCI bus processing device according to a third embodiment of the present invention.

FIG. 9 is a diagram showing a schematic configuration of a hierarchical PCI bus processing device.

FIG. 10 is a configuration diagram illustrating a PCI bus processing device according to a fourth embodiment of the present invention.

FIG. 11 is a configuration diagram showing a flow of setting of a PCI bus processing device according to a fifth embodiment of the present invention.

FIG. 12 is a configuration diagram showing a PCI bus processing device according to a sixth embodiment of the present invention.

FIG. 13 is a configuration diagram illustrating a PCI bus processing device according to a seventh embodiment of the present invention.

FIG. 14 is a configuration diagram illustrating a PCI bus processing device according to an eighth embodiment of the present invention.

FIG. 15: Digital Equipment C
FIG. 2 is a configuration diagram illustrating a PCI bus bridge of orp Corporation.

[FIG. 16] From a primary PCI bus to a secondary PC
FIG. 4 is a timing chart of data transfer to the I bus.

[Explanation of symbols]

1 CPU, 4 PCI bus, 5, 20, 30, 40,
50, 70, 80, 90 PCI bus processing device, 21
Transaction start detection circuit, 22 holding register,
23 abnormality detection circuit, 24 storage register, 25 PC
I bus interface, 31 dedicated line, 41 retry error detection circuit, 44 retry register, 51 bridge device, 52 buffer device, 53 path switch (first path switch), 54 path switch (second path switch), 55, 71, 81 switch switching control device, 56 registers, 61 primary PCI bus (first PCI bus), 62 secondary PCI bus (second
PCI bus), 72, 93 address decoder, 73
Arbiter, 82 device information table, 91 bus changeover switch, 92 device changeover switch.

Claims (8)

[Claims] 1. A CPU that monitors a transaction on a PCI bus, collects and stores abnormality information when an abnormality occurs in the transaction, and separates an abnormality occurrence location when an abnormality occurs on the PCI bus. In the PCI bus processing device for outputting the abnormality information, a transaction start detection circuit for detecting the start of a transaction on the PCI bus, and an address on the PCI bus when receiving a detection signal from the transaction start detection circuit A holding register for holding address and command information on a data line and a byte enable line, and a request signal for address and command information stored in the holding register when a transaction on the PCI bus is monitored and an abnormality is detected. An abnormality detection circuit that outputs When a request signal from the abnormality detection circuit is input, a storage register for storing address and command information from the holding register, and when an abnormality information request signal from the CPU is received, an address stored in the storage register A PCI bus interface for outputting command information to the PCI bus. 2. Upon receipt of an abnormality information request signal from a CPU, an address and command information stored in a storage register are transmitted via a dedicated line connected only to the CPU. 2. The PCI bus processing device according to 1. 3. A CPU that monitors a transaction on a PCI bus, collects and stores abnormality information when an abnormality occurs in the transaction, and separates an abnormality occurrence location when an abnormality occurs on the PCI bus. In the PCI bus processing device for outputting the abnormality information, a transaction start detection circuit for detecting the start of a transaction on the PCI bus, and an address on the PCI bus when receiving a detection signal from the transaction start detection circuit A holding register for holding address and command information on a data line and a byte enable line, and a retry response detection signal when a retry response on the PCI bus is detected, and the number of detected retry responses is set. When the number of retry responses is exceeded A retry error detection circuit that outputs an over signal; a retry response detection signal that is input from the retry error detection circuit; a retry register that holds the address and command information output from the holding register; When an overflow signal is input, a storage register that holds the address and command information output from the retry register, and when an abnormality information request signal is received from the CPU, the address and command information stored in the storage register are read. A PCI bus processing device, comprising: a PCI bus interface for outputting data on the PCI bus. 4. A PCI bus processing device in which a plurality of PCI buses are hierarchically connected, wherein a first PCI bus and a second PC having different bus protocols are provided.
A bridge device for adjusting arbitration with the I bus and synchronizing the bus protocol to transfer data from the first PCI bus to the second PCI bus; In the case where there is, the transmission data from one of the PCI buses is passed to the other PCI bus, and when only one of the PCI buses has an access right, the transmission data is temporarily received, and When the access right of both PCI buses is obtained, a buffer device for transferring received data to the PCI bus for which the access right has been obtained, and usually, the first PCI bus is connected to the buffer device, A first path switch for switching to the bridge device when a switching signal is received, and usually connecting the second PCI bus to the buffer device; A second path switch for switching to the bridge device when receiving, and a switch for outputting the switching signal when detecting the value of a register to which external data can be written and interlocking the two path switches. A PCI bus processing device, comprising: a switching control device. 5. The PCI bus processing device according to claim 4, wherein a value of a register of a PCI bus processing device located in a lower layer of the own device is detected, and the setting of the own bus register is changed. 6. A PCI bus processing device in which a plurality of PCI buses are hierarchically connected, wherein a first PCI bus and a second PC having different bus protocols are provided.
A bridge device that adjusts the arbitration of the I bus and the synchronization of the bus protocol and transfers data from the first PCI bus to the second PCI bus; and has a right to access both the PCI buses. In this case, the transmission data from one PCI bus is passed to the other PCI bus, and if only one of the PCI buses has an access right, the transmission data is received once, A buffer device that transfers received data to the PCI bus to which the access right has been granted when the PCI bus access right has been obtained, and usually connects the first PCI bus to the buffer device and performs switching. A first path switch that switches to the bridge device when a signal is received, and usually connects the second PCI bus to the buffer device and transmits the switch signal A second path switch that switches to the bridge device when the data is transmitted, and an address that detects an address on the first PCI bus and determines whether data needs to be transferred to the second PCI bus. A decoder; an arbiter for checking whether the second PCI bus is being used by a device; and an address decoder for transferring data to the second PCI bus.
When the arbiter determines that it is necessary to transfer data to the bus, and when the arbiter determines that the second PCI bus is being used by a device, the first path switch and the second path switch A PCI bus processing device, comprising: a switch switching control device that outputs a switching signal. 7. The switch switching control device determines whether to output a switching signal based on device information stored in a device information table and a result of address decoding by an address decoder. 6. The PCI bus processing device according to 6. 8. The system according to claim 4, wherein a plurality of PCI buses are connected to one bus changeover switch in a star configuration, and the device changeover switch switches the PCI bus to be connected according to a transfer destination. The PCI bus processing device according to any one of the preceding claims.