JPH058462B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] This is a buffer overrun detection method for a memory access system that allows shared access using multi-ports, in order to prevent a read port from accessing memory beyond the address of a write port. Compare the memory access address written to the write port and the memory access address read by the read port to check that the data is being read normally after data has been written. With this configuration, overrun access during read processing can be reliably prevented and the normality of read data can be guaranteed.

[Industrial application field]

The present invention relates to a data transfer processing method between an input/output device and a central processing unit in a computer system, and more particularly to a buffer overrun detection method during asynchronous data transfer between an input/output device and a central processing unit.

For example, when data is transferred asynchronously between an input/output device (hereinafter referred to as I/O) and a central processing unit (hereinafter referred to as CPU), the data is generally transferred in the following manner.

That is, for example, data read from I/O is temporarily stored in a buffer memory in the I/O or in a control device placed between the I/O and the CPU, and when the CPU is ready to transfer the data, the data in the buffer memory is stored. is transferred to the CPU.

Or in the opposite case, the data sent from the CPU is temporarily stored in the buffer memory and then
When O becomes writable, the data in the buffer memory is sent to I/O.

In such a system, there are a large number (three or more) of access ports to the buffer memory, and these ports tend to be shared among a large number of access modules.

Regarding such a memory access system that can be accessed by time sharing using a multi-port, it is desired to reliably and efficiently check whether written data is being read correctly.

[Conventional technology]

FIG. 4 is a block diagram illustrating a conventional example, and FIG. 5 is a diagram illustrating an outline of a memory access system accessed by multi-ports.

The operation of this example is for checking the buffer overrun state, and FIG. 4 shows a case where one read module 1 and one write module 2 are used.

That is, data is transferred from the write module 2 to the buffer memory (hereinafter referred to as BM) 6 at a predetermined transfer rate via the write port 4, and specified by the write port address pointer (hereinafter referred to as AP.W) 4a. Write to the BM6 area.

On the other hand, read module 1 reads data from the area of BM6 specified by read port address pointer (hereinafter abbreviated as AP.R) 3a, thereby transferring data from write module 2 to read module 1. executed.

In this case, the read module 1 needs to read only the data already written by the ride module 2.

Therefore, the comparison circuit 5 compares the "value of AP.W4a" and "value of AP.R3a", that is, whether or not the condition is established that "value of AP.W4a">"value of AP.R3a". The normality of the read data (ie, that there is no buffer overrun condition) is checked.

On the other hand, recently, computer systems have become large-scale, and when configuring a multi-port memory access system, the system is often configured as shown in FIG.

In the case of the multiport memory access system shown in Figure 5, BM6 is access module 1.
(0)~1(n) to multiple access port 3(0)~
3(m) via the capture of any access port 3(i).

That is, access modules 1(0) to 1(n) are
It is possible to read/write to/from BM6 using any of the access ports 3(0) to 3(m). Note that each access port 3(0) to 3(m) is provided with an address pointer for buffer memory access.

In such a multi-port memory access system, for example, data writing to BM6 is performed using access module 1 (0) (hereinafter referred to as write module 1 (0)), and access port 3 (1) (hereinafter referred to as write module 1 (0)) is used to write data to BM6. Port 3 (1)
Write data to BM6 via
When read module 1 (2) reads data written by write module 1 (0) via read mode 3 (m), the write address pointer in write port 3 (1) and read port 3 ( It is necessary to compare the size with the read address pointer in m).

That is, unless the read address pointer value<the write address pointer value, it does not mean that the data written to the BM6 from the read module 1 (2) has been read normally.

This is a buffer overrun state that can occur when the transfer rate of read data at read port 3(m) is generally faster than the transfer rate of write data from write port 3(1).

[Problem that the invention seeks to solve]

However, conventionally, when there are two access ports (a read port and a write port) as shown in Figure 4, a method for detecting a buffer overrun state by providing a means for comparing the size of one address pointer has not been implemented. However, no function has been implemented to check the buffer overrun state in a multiport memory access system based on a specific system operation state.

For example, when applied to a multi-port memory access system using a buffer overrun state detection method when there are two access ports, there are problems such as the hardware configuration becomes enormous and the control thereof becomes complicated.

[Means for solving problems]

FIG. 1 shows a block diagram illustrating the principle of the invention.

The principle block diagram shown in FIG. 1 shows the configuration of a multiport memory access system, and this configuration consists of access modules 1(0) to
1(n), BM6, and access port 4 consisting of the following means:
(0) to 4(m), a task module (hereinafter referred to as TM) 7 that manages the allocation of access ports 4(0) to 4(m), and access ports 4(0) to 4(m). BM common bus (BM-BUS) (2) Use request signal RQ0~
Receive RQm and use permission signal GR0 for it
-GRm to each access port 4(0) to 4(m) every cycle.

In addition, each access port 4(0) to 4(m) has an address pointer means for memory access and an access port 4(0) to 4(m) to be compared.
a comparison target address pointer means that holds the access address of BM6, and an access module 1 that accesses BM6.
ID register means for setting the identifier numbers (0) to 1(n) (hereinafter referred to as ID numbers), comparison means for comparing the ID numbers, and size comparison between the address pointer means and the address pointer means to be compared. A status register means sets a comparison result of the magnitude comparison means, and a driver means and a receiver means each having a set function for setting a signal exchanged via the BM-BUS. ing.

[Effect]

To ensure the prevention of buffer overrun conditions in the case of multi-port memory access systems,
Each access port 4(0) to 4(m) includes an address pointer means for setting its own address pointer value, a comparison target address pointer means for setting an address to be compared in accordance with a processing operation, and an address pointer means. By providing and configuring a size comparison means for comparing the size of the address pointer and the comparison target address pointer means, overrank access during read processing in a multi-port memory access system is reliably prevented and the normality of read data is guaranteed. It becomes possible.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 1 to 3.

FIG. 2 is a block diagram illustrating an embodiment of the present invention, and FIG. 3 is a diagram illustrating a memory access situation in a multi-port. Note that the same reference numerals indicate the same objects throughout the figures.

Access ports 4(0) to 4 in this embodiment
(m) is composed of the following functional blocks as shown in FIG. That is, memory access address pointers APO to APm that hold the memory access addresses of own access ports 4(0) to 4(m) and access ports 4(0) to 4(m) to be compared.
Comparison target address pointers IPLO to APLm that hold the access address of A comparison section 41 that performs a comparison, a magnitude comparison section 42 that performs a magnitude comparison between the address pointers APO to APm and comparison target address pointers APLO to APLm, and a status register ST0 to STm that sets the comparison result of the magnitude comparison section 42. Drivers DID0 to DRIDm and receivers RVI0 to RVIDm access signal input/output with ID-BUS in BM-BUS (2), and signals between access port (hereinafter referred to as AP)-BUS in BM-BUS (2) Drivers DRAP0 to DRAPm and receiver RVAP access input/output of
0 to RVAPm.

For example, if access module 1(0) queries TM7 via common bus (1) and learns that access port 4(0) is available, access module 1(0) queries access port 4(0). 0) in the ID register IO.

Furthermore, the access module 1 (0) sets the start address of the BM6 to which data is to be written in the address pointer APO, and then starts the data writing operation to the BM6. address pointer
APO is incremented by 1 every time one word of data is written to BM6. In addition, access module 1 (0), access port 4
(0) will be hereinafter referred to as light module 1(0) and light port 4(0).

After that, in order to read the data written by the access module 1(n) (hereinafter referred to as read module 1(n)) in the write module 1 (AO), for example, the access module 1(n) (hereinafter referred to as read module 1(n)) queries the TM7, (m) (hereinafter referred to as read port 4(m)) and receives the contents of the ID register IO (set value “0”) received and stored by write module 1 (0) via TM7. .

Next, lead module 1(n) connects lead port 4
(m) Set the received set value (set value "0") in the ID register Im, and point the start address of the data to be read from BM6 to the address pointer.
Set to APm and then start the read operation.

At this time, address pointer APm is incremented by 1 each time data is read from BM6 by 1 word.

During this time, other access module 1 (1)
1(n-1) is already writing/reading through another access port.

At this time, access to BM6 is performed in a time-divided manner as shown in Figure 3, and BM-6 to BM6 is
BUS (2) connects each port 4(0) to 4(m) every cycle a, b, c, ... (P0, P1, P
2, P3, ..., Pm) is the pipeline method used.

ARB8 is BM from each port 4(0) to 4(m)
-BUS2 use request signal RQ0, RQ1,..., RQm
is received and the use permission signal GR0,
One of GR1,...GRm for each cycle a, b,
c, ... to each port 4(0) to 4(m).

Each port 4(0) to 4(m) uses this permission signal.
When GR0, GR1,...GRm are received, BM-
Driver DRID0 to DRIDm to BUS (2),
A method is being used to write/read data to/from BM6 by turning on DRAP0 to DAPm.

Therefore, when read port 4(m) obtains permission to access BM6, that is, when read port 4(m) receives the permission signal,
When GRm is on, drivers DRIDm and DRAPm
turns on. Note that when the use permission signal GRm is off, the receivers RVIDm and RVAPm are on.

When light port 4 (0) obtains usage permission and usage permission signal GR0 is on, BM-BUS (2)
On the internal ID-BUS, the contents of ID register I0 are
-The contents of address pointer AP0 will be placed on the BUS.

On the other hand, read port 4(m) has a use permission signal at this time.
Since GR0 is off, receiver RVIDm,
RVAPm is turned on and light port 4(0)
Contents of ID register I0 and address pointer AP
Receive the contents of 0.

At this time, the contents of the ID register I0 received by the comparator 41 and the ID register of the read port 4(m)
The contents of Im are compared, and if they match, the contents of address pointer AP0 are latched to comparison target address pointer APLm.

Read port 4(m) is the comparison target address pointer
Light port 4 is configured to latch to APLm.
(0) writes data to BM6, (BM-BUS
It is updated each time (2) the right to use is obtained), and the size comparison unit 42 compares the size with the own address pointer APm each time.

If the written data is being read normally, own address pointer APm≦comparison target address pointer APLm (i.e., write port 4(0)
address pointer AP0).

If own address pointer APm>comparison target address pointer APLm, at that point the buffer overrun is set in the status register STm and notified to TM7, thereby detecting the buffer overrun.

〔Effect of the invention〕

According to the present invention as described above, overrun access during read processing in a multiport memory access system can be reliably prevented with a small amount of hardware, and the normality of read data can be guaranteed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the principle of the present invention.
FIG. 2 is a block diagram explaining an embodiment of the present invention;
FIG. 3 is a diagram illustrating a memory access situation in a multi-port, FIG. 4 is a block diagram illustrating a conventional example, and FIG. 5 is a diagram illustrating an outline of a memory access system accessed by a multi-port. In the figure, 1 is the lead module, 1 (0)
~1(n) is the access module, 2 is the write module, 3 is the read port, 3(0) ~3(m), 4
(0) to 4(m) are access ports, 3a is AP.R,
4a is AP.W, 4 is a write port, 5 is a comparison circuit, 6 is BM, 7 is TM, 8 is ARB, 41 is a comparison section, and 42 is a magnitude comparison section.

Claims (1)

[Claims] 1. At least three access modules 1(0) to 1(n) connected via a common bus (1) and capable of accessing the memory 6.
and at least three or more ports 4(0) to 4(n) for accessing the memory 6, and each of the access modules 1(0) to 1(N) has an arbitrary one port in the timeshare. Applicable port 4(0)~4
(m) allows access to the memory 6, and among the access modules 1(0) to 1(n),
Any two access modules 1(0) to 1
(n), one (write module) performs data writing processing to the memory 6 through one port (write port), and the other (read module)
In a shareable memory access system that can read data written in the memory 6 through one other port (read port), each port 4(0) to 4(m) Identifier set by the access module 1(0) to 1(n) in
An ID register that holds an ID number and an address pointer for accessing the memory 6, the ID register at the read port is
the light module is in the light port;
The read port has a setting means by which a value equivalent to the value set in the ID register is set by the read module, and furthermore, the read port is set to the own read port when a port other than the own read port obtains the timing for accessing the memory. a latch means for monitoring the ID register of the port other than the own read port, and latches and updates the address pointer of the port other than the own read port in the own read port when the content matches the ID register in the own port; , checking means for comparing the address pointer latched by the latch means with the address pointer in the own read port and checking that the address pointer in the own read port must always be smaller; A buffer overrun detection method, characterized in that the checking means checks a buffer overrun in a read operation of the read module for the memory 6.