JPH0289154A - Information processing system - Google Patents

Abstract

PURPOSE:To initialize hardware without causing the breakdown of the contents of a memory by prohibiting memory access at the time of resetting hardware stopping the operation of other master module in a state that a bus using right is acquired by the arbitration of an arbiter. CONSTITUTION:When a switch 6 is turned on, a reset control circuit 5 stops the operation of a CPU 3 after the CPU 3 finishes processing which it being executing if any, and outputs a bus using right setting request for a signal line 1. The arbiter 4 stops the operation of all masters by the reset control circuit 5 after the finish of the request of high priority by other master like the master B, etc., if said request exists, and after wards, it outputs an initialization signal through the signal line (n). Thus, the hardware reset is never performed during access or read/write to the memory 2 or the I/O port of each master, and the contents of the memory can be preserved in the state before, resetting the hardware.

Description

[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to an information processing system.

(Prior Art) Conventionally, there is an information processing system in which a plurality of mask modules perform memory access after arbitration of bus usage rights by an arbiter.

To ensure fault tolerance in such systems, if a hardware deadlock occurs, a hardware reset must be performed, or if the system consists of multiple boards, the faulty board must be reset. I try to remove the module as is, or clear only that module before removing it.

However, if you perform a hardware reset or hot-swap while another mask is accessing memory, the register contents of the mask being accessed may be destroyed. Memory contents could be corrupted.

When a hardware deadlock occurs, there is a demand for dumping the memory contents for analysis, but the reliability of the dump output is low because the memory contents cannot be guaranteed with the methods described above.

(Problems to be Solved by the Invention) As described above, the conventional methods for dealing with hardware deadlocks have a problem in that memory contents are not guaranteed.

The present invention has been made in view of the problems of the prior art described above, and its purpose is to provide an information processing system that can initialize hardware without causing destruction of memory contents. There is a particular thing.

[Structure of the invention]

(Means for Solving the Problems) An information processing system of the present invention is an information processing system in which a plurality of mask modules perform memory access after arbitration of bus usage rights by an arbiter. means for stopping the operation of a CPU in one master module among the modules;
After the operation of the PU is stopped, a means for issuing a request to the arbiter for the right to use the bus and acquiring the right to use the bus; and a means for outputting a clear signal to the bus after acquiring the right to use the bus; The present invention is characterized by comprising means for stopping the operation of another master module among the modules, and then outputting an initialization signal to the bus to apply a hardware reset.

(Function) According to the present invention, when performing a hardware reset, the operation of other mask modules is stopped and memory access is prohibited while the right to use the bus has been acquired through arbitration by the rear biter. , it is possible to prevent unauthorized access and maintain the memory contents in their pre-reset state.

(Example) Examples of the present invention will be described below with reference to the drawings.

The figure is a block diagram of an information processing system according to an embodiment of the present invention.

In this figure, 1 is an internal bus, and this internal bus 1
A plurality of modules such as master A and master B are connected to the memory 2 as well as a memory 2.

Master A has a CPU 3 and an arbiter 4, and the CPU
3 and memory 2 are also accessed by master B and other modules. The arbiter 4 arbitrates the right to use the bus for a plurality of masks A, B, etc. connected to the internal bus 1.

The master A is further provided with an additional circuit called a reset control circuit 5, and this reset control circuit 5 has a reset control switch 6, and when this switch 6 is turned on, it controls a hardware reset. ing.

That is, when this switch 6 is turned off, C
By outputting the BRQ signal to the signal line a, the PU 3 requests the arbiter 4 to set the right to use the bus.

Then, if there is a BRQ signal with a higher priority than the BRQ signal from the CPU 3, the arbiter 4 waits for its completion, and if there is none, it immediately sends an ACK signal to the signal line to notify that the right to use the bus has been acquired. Output B for. As a result, the CPU 3 acquires the right to use the bus and accesses the memory 2 through the signal line g.

When master B requests the right to use the bus, it outputs a BRQ signal to signal line C.

Then, the arbiter 4 receives this through the signal line e, and outputs an ACK signal to the signal line 0 when the right to use the bus is acquired.

Master B receives this ACK signal through signal line d, learns that it has acquired the right to use the bus, and accesses CPU 3 and memory 2 through the signal line.

When the switch 6 is turned on, first, the reset control circuit 5
outputs a HOLD signal for stopping the operation of the CPU 3 to the signal line l. Upon receiving this, the CPU 3 finishes any currently running processing and then stops its operation.
In order to notify the termination of the operation and the transfer of bus ownership to j, a HOLDA signal is output to signal line j in response to the HOLD signal.

Then, the reset control circuit 5 outputs a BRQ signal for requesting bus use right setting to the signal line l.

When the arbiter 4 receives this, if there is a request with a high priority due to another mask such as mask B, it waits for the completion of the request, and if there is not, it immediately outputs an ACK signal to the signal line m.

Then, the reset control circuit 5 first outputs a CLR signal to the internal bus 1 through the signal line n, and stops the operation of all masks such as the mask B connected to the internal bus 1. Master B inputs the CLR signal through signal line p.

In this way, after all the masks connected to the internal bus 1 have stopped, a hardware reset is performed by outputting an initialization signal through the signal line n. Master B inputs its initialization signal through the signal line ``.

As a result, a hardware reset will not be performed while accessing or reading/writing the I10 port of memory 2 or each mask, and no unauthorized access to memory 2 will occur due to a hardware reset. The memory contents can be maintained in the state before the hardware reset, and the dump output of the memory 2 can be reliable.

〔Effect of the invention〕

As explained above, according to the present invention, when a hardware reset is performed, the operation of other mask modules is stopped and memory access is prohibited while the right to use the bus has been acquired through arbitration by the arbiter. This has the effect that unauthorized access can be prevented, the memory contents can be maintained in the state before being reset, and high reliability can be obtained in dump output for analyzing the memory contents.

[Brief explanation of the drawing]

The figure is a block diagram of an information processing system according to an embodiment of the present invention. A, B...Mask, 1...Internal bus, 2...Memory, 3...CPtJ, 4...Arbiter, 5...-Reset control circuit, 6...Reset control switch

Claims (1)

[Claims] In an information processing system in which a plurality of master modules access memory after arbitration of bus usage rights by an arbiter, the operation of a CPU in one of the plurality of master modules is provided. means for halting the operation of the CPU; means for issuing a request for the right to use the bus to the arbiter and acquiring the right to use the bus after the operation of the CPU is stopped; and after acquiring the right to use the bus, sending a clear signal to the bus. and a means for outputting an initialization signal to the bus, stopping the operation of another master module among the plurality of master modules, and then outputting an initialization signal to the bus to apply a hardware reset. processing system.