JPH09282297A - Inter-cpu communication system using dual port memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the information transmission efficiency by improving dual port memory(DPRAM) utilization efficiency in the inter-CPU communication of 1:N composed of a main CPU and plural sub CPUs. SOLUTION: At the time of performing the inter-CPU communication using one DPRAM 5 between the main CPU 1 and the plural sub CPUs 2-4, the memory map of the DPRAM is divided into a status area 10 to the sub CPUs composed of areas 14-16 corresponding to the respective sub CPUs, the status area 11 to the main CPU composed of the areas 17-19 similarly and two data areas 12 and 13. By writing control information from the main CPU to the respective sub CPUs in the corresponding areas 14-16, writing the control information from the respective sub CPUs to the main CPU in the corresponding areas 17-19 and informing each other, the main CPU and the plural sub CPUs access both of the bisected data areas 12 and 13 inside the DPRAM.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication system between CPUs using a dual port memory, and particularly to information between one main CPU and a plurality of sub CPUs constituting a multiprocessor system via the dual port memory. The present invention relates to a communication system between CPUs that performs transmission.

[0002]

2. Description of the Related Art In a conventional communication system between CPUs of this type, communication between a main CPU and a plurality (N) of sub CPUs is performed by one dual port memory (usually a dual port RAM (Random Access Memory)).
When implemented by DPRAM (hereinafter abbreviated), the inside of the DPRAM is divided into N (for example, 3) as shown in FIG. 6, and each region is divided into i (i = 1 to N) th sub-C.
Information is transmitted between the main CPU and each sub CPU by allocating each PU individually.

[0003]

In this conventional inter-CPU communication system, when performing 1: N inter-CPU communication, D
An area divided into N is required on the PRAM.
As the number of PUs increases, the number of divisions of the limited DPRAM area increases, and the area amount assigned to each sub CPU decreases. Further, when a large amount of information is exchanged only between the main CPU and a specific sub CPU, the other N-1 areas cannot be accessed by the other sub CPU due to the bus arbitration during that time. Since it is not used, there is a problem in terms of DPRAM utilization efficiency.

[0004]

According to an inter-CPU communication system using a dual port memory of the present invention, information is communicated between one main CPU and a plurality of sub CPUs constituting a multiprocessor system via the dual port memory. In an inter-CPU communication system that performs transmission, the number of divisions of a data area allocated for information transmission on the dual port is limited to two, and an information transmission request is generated between the main CPU and any of the plurality of sub CPUs. It has a configuration in which any usable one of the two divided data areas is dynamically assigned at a time point.

Further, in the above structure, in addition to the divided data area on the dual port memory,
A plurality of counter sub CPU status areas corresponding to each of the plurality of sub CPUs for notifying control information from the main CPU to the plurality of sub CPUs, and control information from the plurality of sub CPUs to the main CPU A plurality of pairs of main CPU status areas corresponding to each of the plurality of sub CPUs, and 2 of each of the plurality of sub CPUs through the pair of sub CPU status areas and the pair of main CPU status areas. It may be configured to perform access control for the divided data area.

Further, the main CPU has an interrupt control line for giving each of the plurality of sub CPUs a trigger for reading the control information set in the pair sub CPU status area of the dual port memory,
When information is transmitted from the main CPU to each of the plurality of sub CPUs, the main CPU designates which side of the divided data area is to be used, and the designation information of this data area is applied. Information is transmitted to the corresponding sub CPU through the corresponding data area by setting the corresponding sub CPU status area corresponding to the sub CPU and notifying the corresponding sub CPU through the interrupt control line. When information is transmitted from each of the sub CPUs to the main CPU, the corresponding sub CPU sets write request information to the data area in the corresponding main CPU status area, and the main CPU When this write request information is recognized by polling, which side of the two divided data areas is to be used is designated, Sub CPU that the designation information of the data area is set to the pair sub CPU status area of the sub CPU corresponding to the relevant, corresponding through said interrupt control line
Can be configured to receive information transmission from the corresponding sub CPU via the corresponding data area.

[0007]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1A is a block diagram showing the configuration of an embodiment of the present invention. The multiprocessor system of this example includes a main CPU 1 and three CPUs # 1, # 2 and # 3.
One sub CPU 2, 3, 4, main CPU 1 and sub C
One dual port RAM (DPRAM) 5 accessed from the PUs 2, 3 and 4 and the sub CPUs 2, 3 and 4
From the main CPU 1 to the sub-CPUs 2, 3 and 4 and interrupt control lines 7, 8 and 9 for giving a trigger for reading control information from the main CPU 1 to the sub CPUs 2, 3 and 4. The bus arbitration circuit 6 restricts simultaneous access to the DPRAM 5 at the hardware level so that only one sub CPU 2 to 4 can access the DPRAM 5 at the same time.

FIG. 1B shows the DPRAM 5 of FIG.
3 is a memory map diagram of FIG. The memory area inside the DPRAM 5 is a paired sub CPU status area 10 for storing control information from the main CPU 1 to each sub CPU 2 to 4, and a paired main CPU status area 11 for storing control information from each sub CPU to the main CPU. , And is largely divided into two data areas 12 and 13 # 1 and # 2 for transmitting actual information (storing transmission information) between the main CPU and each sub CPU. The sub-CPU status area 10 has the sub CPUs (# 1) 2, (# 2) 3, (#
3) Areas 14, 15 and 16 corresponding to 4 are divided, and the main CPU 1 accesses each of the areas 14, 15 and 16 to the corresponding sub CPUs 2, 3 and 4,
An interrupt is transmitted via the interrupt control lines 7, 8 and 9.
Similarly, the main CPU status area 11 has sub CPUs (# 1) 2, (# 2) 3, (# 3) inside thereof.
It is divided into areas 17, 18 and 19 corresponding to four.
Requests from the sub CPUs 2, 3 and 4 to the main CPU 1 consider that the number of sub CPUs is large, and interrupts are not used.
Recognize by polling periodically. Both the main CPU 1 and each of the sub CPUs 2, 3 and 4 can access any of the data areas (# 1) 12 and (# 2) 13, and access control is performed from the main CPU 1 to the sub CPU status area 10 By updating.

2, FIG. 3, FIG. 4 and FIG. 5 are flow charts for explaining the operation of the present invention. 2 shows the main CPU 1
From the main CPU 1 side when transmitting information from a sub CPU to a certain sub CPU (for example, CPU (# 1) 2), FIG. 3 is a sub CPU 2 side procedure in that case, and FIG.
FIG. 5 shows a procedure on the side of the sub CPU 2 when information is transmitted from (for example, the CPU 2) to the main CPU 1, and FIG. 5 shows a procedure on the side of the main CPU 1 in that case. Main C in both Figures 2-5
The information transmission procedure between the PU 1 and the sub CPU 2 is shown, but this is only an example, and in reality all sub CPs are shown.
A similar procedure is practiced for U2,3,4.

Next, the operation of the present invention will be described with reference to FIGS.

First, the operation when information is transmitted from the main CPU 1 to the sub CPU (for example, the sub CPU (# 1) 2) will be described. First, the main CPU 1 is a DPRAM
5, the free state of the data areas (# 1) 12 and (# 2) 13 is checked and one free data area is selected according to a preset selection method (step S in FIG. 2).
101). If the data area (# 1) 12 is selected, it is secured (step S111), and information to be transmitted is written in the secured data area 12 (step S11).
2), DPRAM 5 counter sub CPU status area 10
In the area 14 corresponding to the sub CPU (# 1) 2 of the transmission destination, the control information indicating the "readout instruction of the data area (# 1) 12" is set (step S113), and the sub CPU 2 is operated through the interrupt control line 7. To the main CP of the DPRAM 5 (step S130).
The U status area 11 (areas 17 to 19) is polled to check if there is information from the sub CPUs 2 to 4 (step S131). In the process of step S101, if the data area (# 2) 13 is selected, it is secured (step S121), and similarly to the above, the information to be transmitted is written in the secured data area 13 (step S1).
22), the control information indicating the "readout instruction of the data area (# 2) 13" is set in the area 14 corresponding to the sub CPU (# 1) 2 of the transmission destination in the status area 10 for the sub CPU (step S123). ), And transmits an interrupt to the sub CPU 2 through the interrupt control line 7 (step S13
0) and then poll the main CPU status area 11 (areas 17 to 19) to check if there is information from the sub CPUs 2 to 4 (step S131).
If there is no empty data area in the processing of step S101, the transmission processing of information using the data areas 12 and 13 is performed (step S151), and step S101.
The subsequent processing is repeated.

On the other hand, the sub CPU 2 which has received the interrupt from the main CPU 1 (step S201 in FIG. 3) reads the control information from the self-corresponding status area 14 (step S202), and the information from the data areas 12, 13 " Read instruction "(step S20
3). If it is a "read instruction", it is determined which data area the read destination is (step S204). In the case of the data area (# 1) 12, in the self-corresponding area 17 of the main CPU status area 11, "data area (# 1)"
12 is being read ”is set (step S
211), the transmission information is read from the data area 12 (step S212). When the read destination is the data area (# 2) 13, the data area (# 2) is stored in the self-corresponding area 17 of the main CPU status area 11 as described above.
13 is being read ”is set (step S
221), and the transmission information is read from the data area 13 (step S222). When the reading of the transmission information from the data area 12 or 13 is completed, the control information indicating "no request" is set in the status area 17 (step S2).
31), the information transmission process is terminated (step S23).
2). Further, in the process of step S203, if the instruction is not the "read instruction", another corresponding process is performed (step S241).

Polling processing for the main CPU status area 11 (areas 17 to 19) (step S13 in FIG. 2)
The main CPU 1 which was performing 1) has a status area 17 corresponding to the sub CPU (# 1) 2 which has transmitted the interrupt.
(Step S132), the change is detected, it is checked whether the content is "no request" (step S133), and if "no request", the sub CPU 2
Upon recognizing that the information transmission processing on the side has been completed, the own information transmission processing is ended (step S134). If there is no change in the status of the status area 17 or if the content is not "no request", other applicable processing is performed (step S141), and the processing from step S131 onward is repeated.

Next, from the sub CPU (# 1) 2 to the main C
The operation for transmitting information to PU1 will be described. Sub C
The PU 2 first sets “write request” in its own status area 17 of the main CPU status area 11 of the DPRAM 5 (step S301 in FIG. 4), and waits for an interrupt from the main CPU 1 (step S302).

The main CPU 1 is a main CPU periodically
The status area 11 corresponds to each sub CPU 2 to 4 (area 1
7 to 19) (step S4 in FIG. 5).
01), for example, when the state change of the status area 17 of the sub CPU 2 is detected (step S402), it is determined whether the content is “write request”. If the status of the status area 17 has not changed or the content is not “write request”, other corresponding processing is performed (step S461) and the processing from step S401 onward is repeated. The main CPU1
When the "write request" is detected in the process of step S403,
Data areas (# 1) 12 and (# 2) 13 of the DPRAM 5
The empty state is checked and one empty data area is selected according to a preset selection method (step S404). Here, if the data area (# 1) 12 is selected, it is secured (step S411), and DPRA
In the area 14 corresponding to the sub CPU (# 1) 2 that is the transmission request source in the sub CPU status area 10 of M5, the control information indicating the "write instruction of the data area (# 1) 12" is set (step S412). ), And transmits an interrupt to the sub CPU 2 through the interrupt control line 7 (step S43
0) and then poll the main CPU status area 11 (areas 17 to 19) to check if there is information from the sub CPUs 2 to 4 (step S431).
In the process of step S404, the data area (# 2)
If 13 is selected, it is secured (step S42
1), in the same manner as above, the sub CPU status area 10
In the area 14 corresponding to the sub CPU (# 1) 2 which is the transmission request destination, the control information indicating the “write instruction of the data area (# 2) 13” is set (step S422), and the sub control is performed through the interrupt control line 7. An interrupt is transmitted to the CPU 2 (step S430), and then the main CPU status area 11 (areas 17 to 19) is polled to execute the sub CP.
Check if there is information from U2-4 (step S
431). If there is no free data area in the processing of step S404, the information transmission processing using the data areas 12 and 13 is performed (step S451), and the processing from step S404 onward is repeated.

On the other hand, the sub CPU 2 which has received the interrupt from the main CPU 1 (step S303 in FIG. 4) reads the control information from the self-corresponding status area 14 (step S304), and stores the information "" in the data areas 12 and 13. It is checked whether it is a "write instruction" (step S305).
If it is a "write instruction", it is determined which data area is the write destination (step S306). Data area (# 1)
In the case of 12, the control information indicating "writing of data area (# 1) 12" is set in the self-corresponding area 17 of the main CPU status area 11 (step S31).
1) Write transmission information in the data area 12 (step S312). When the writing destination is the data area (# 2) 13, the status of the main CPU status area 11 is the same as above.
In the self-corresponding area 17, the “data area (# 2) 13
Control information indicating "writing in progress" is set (step S32
1) Write the transmission information in the data area 13 (step S322). When the writing of the transmission information to the data area 12 or 13 is completed, the control information indicating "no request" is set in the status area 17 (step S331),
Wait for an interrupt from the main CPU 1 (step S33
2). Further, in the processing of step S305, if the instruction is not the "write instruction", other corresponding processing is performed (step S351), and the processing from step S302 is repeated.

Polling processing for the main CPU status area 11 (areas 17 to 19) (step S43 in FIG. 5)
The main CPU 1 which was performing 1) has a status area 17 corresponding to the sub CPU (# 1) 2 which has transmitted the interrupt.
(Step S432), if a change is detected, it is checked whether the content is "no request" (step S433). If "no request", the sub CPU 2
It is recognized that the side information writing process has been completed, and the transmission information is read from the corresponding data areas 12 and 13 (step S434). If there is no change in the status of the status area 17 or if the content is not "no request", other corresponding processing is performed (step S441), and the processing from step S431 onward is repeated. The main CPU1 carries out step S43.
When the transmission information reading process of 4 is completed, the sub CPU 2
The control information indicating "reading of the corresponding data area is completed" is set in the status area 14 (step 43).
5) Then, an interrupt is transmitted to the sub CPU 2 through the interrupt control line 7 (step S436), and the information transfer process ends (step S437).

After writing the transmission information in the data area, the sub CPU 2 waiting for an interrupt from the main CPU (step S332 in FIG. 4) receives the interrupt (step S333), and then the self-corresponding status area 14
The control information is read from (step S334), and it is checked whether the information from the data areas 12 and 13 is "read complete" (step S335). When the reading is completed, the information transfer process is ended (step S336). If the reading is not completed, other relevant processing is performed (step S341) and the processing from step S332 is repeated.

As described above, this system is a DPR
A data area 12 allocated for information transmission on the AM5,
The number of divisions of 13 is limited to two, and a plurality of status areas 14 to 16 corresponding to the individual sub CPUs and a plurality of sub CPUs 2 from the main CPU 1 provided to the plurality of (3) sub CPUs 2 to 4 are provided. From 4 to the main C
By using the plurality of status areas 17 to 19 corresponding to the individual sub CPUs for the PU 1, the main CPU 1 and the plurality of sub CPUs 2 to 4 are set to the DPRAM 5
Both internal data areas 12 and 13 can be accessed, and efficient information transmission is realized.

The actual value written in each of the status areas 14 to 19 is used in the coded form of each meaning used in the transmission procedure. Also, the main CPU
1 indicates which sub CPU (# 1) 2, (# 2) 3, (# 3) depending on the priority of the status detection result by polling the status areas 17, 18 and 19 and various other processes.
It is scheduled whether or not to transmit information to the mobile station 4.

[0022]

As described above, according to the present invention, when the information transmission between the main CPU and the plurality of sub CPUs is performed using one dual port memory, the information transmission is performed on the dual port. The number of divisions of the allocated data area is limited to two, and the main CPU and multiple sub CPUs
One of the two divided data areas that can be used is dynamically allocated when an information transmission request is made between the sub-CPU and each of the sub-CPUs. It can be used to the maximum, and it is possible to improve the utilization efficiency of the dual port memory.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing an embodiment of the present invention, where FIG. 1A shows the overall configuration, and FIG. 1B shows the area configuration of a dual port memory (DPRAM).

FIG. 2 is a flow chart for explaining the operation of the present invention,
7 shows processing on the main CPU side when information is transmitted from the main CPU to the sub CPU.

FIG. 3 is a flow chart for explaining the operation of the present invention,
7 shows processing on the sub CPU side when information is transmitted from the main CPU to the sub CPU.

FIG. 4 is a flow chart for explaining the operation of the present invention,
7 shows processing on the sub CPU side when information is transmitted from the sub CPU to the main CPU.

FIG. 5 is a flow chart for explaining the operation of the present invention,
The processing on the main CPU side when information is transmitted from the sub CPU to the main CPU is shown.

FIG. 6 is a diagram showing a memory map of a DPRAM used in the conventional technique.

[Explanation of symbols]

 1 Main CPU 2, 3, 4 Sub CPU 5 Dual port memory (DPRAM) 6 Bus arbitration circuit 12, 13 Data area

Claims (3)

[Claims] 1. A multiprocessor system comprising 1
In an inter-CPU communication system for transmitting information between one main CPU and a plurality of sub CPUs via a dual port memory, the number of divisions of a data area allocated for information transmission on the dual port is limited to two, and A dual port memory characterized by dynamically allocating any available one of the two divided data areas at the time of the information transmission request between the main CPU and any one of the plurality of sub CPUs. Communication system between CPUs. 2. Corresponding to each of the plurality of sub CPUs for notifying the control information from the main CPU to the plurality of sub CPUs, in addition to the divided data area on the dual port memory. The plurality of sub CPU status areas and the plurality of sub Cs for notifying control information from the plurality of sub CPUs to the main CPU
A plurality of main CPU status areas corresponding to each of the PUs are provided, and access control to the divided data area for each of the plurality of sub CPUs is performed through the pair sub CPU status area and the main CPU status area. The inter-CPU communication system using the dual port memory according to claim 1, which is performed. 3. The main CPU to the plurality of sub-Cs
Pair of sub-ports of the dual port memory for each PU
When the main CPU has an interrupt control line for triggering the reading of the control information set in the PU status area and information is transmitted from the main CPU to each of the plurality of sub CPUs, the main CPU is It is specified which side of the data area divided into two is to be used, the specification information of this data area is set in the counter-to-sub CPU status area corresponding to the corresponding sub CPU, and the corresponding sub CPU is set to the corresponding sub CPU through the interrupt control line. By notifying, the information is transmitted to the corresponding sub CPU via the corresponding data area, and when the information is transmitted from each of the plurality of sub CPUs to the main CPU, the corresponding sub CPU corresponds to itself. Write request information to the data area is set in the status area for main CPU, and the main CPU executes polling. When the write request information is recognized by, which side of the divided data area is to be used is designated, and the designation information of this data area is set in the counter sub CPU status area corresponding to the corresponding sub CPU. 3. The CPU using the dual port memory according to claim 2, wherein information is transmitted from the corresponding sub CPU through the corresponding data area by notifying the corresponding sub CPU through the interrupt control line. Communications system.