JPH04245363A - Bus arbitration system - Google Patents

Abstract

PURPOSE:To improve the use efficiency of a bus by accessing an I/O equipment which has small data width even during the use of a bus by one bus master by utilizing the rest of bus width by another bus master when only part of the bus width is used. CONSTITUTION:The bus BUS with the bus width 3n to which input/output equipments 11, 12, and 13 with data width 2n, 3n, and (n) are connected is divided into unit buses BUS1-BUS3 with the bus width (n), and bus arbiters 31-33 in a bus arbitration part 30 arbitrates the unit buses BUS1-BUS3 according to request signals REQ1-REQ2 and send permission signals ACK1-ACK3 back. The bus masters 21 and 22 accesses the target I/O equipment after the permission signals allowing the use of the unit buses where the target I/O equipment is connected are all sent back.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus arbitration system for buses to which input/output devices having different data widths (hereinafter referred to as I/O devices) are connected.

0002

[Prior Art] Generally, an I
The data width of /O devices varies, such as 8 bits, 16 bits, and 32 bits. Therefore, I/O devices with different data widths may be incorporated into one system.

[0003] In such a system, the I/O device having the widest data width among the I/O devices used in the system is
A bus (I/O access bus) with a bus width (usually the same width as the widest data width) that can be connected to I/O devices is provided.
It was common to connect the /O device to a master device (bus master) for access. Connected to this bus is a bus arbitration circuit that receives access requests (bus use requests for I/O device access) from each master and performs bus arbitration.

[0004] When the bus arbitration circuit receives an access request from a master, it checks the state of the bus, and if the bus is free, performs control such as granting access permission to the requesting master. If the bus is not available, access permission will not be granted until the bus is available.

[0005] Now, in the above computer system, let us take as an example a system in which an 8-bit I/O device and a 16-bit I/O device are connected to a 32-bit width I/O access bus. , a certain master has 8-bit I/O
When accessing a device, only an 8-bit portion of the 32-bit bus is used, and the remaining 24-bit portion is essentially free. However, in the past, the state of such a 32-bit bus was treated as if the entire bus was in use and not free. Therefore, other masters can use the remaining 24 bits mentioned above to
Even if an attempt was made to access the bit I/O devices at the same time, the bus arbitration circuit would not grant permission, so the access could not be made.

[0006]

[Problems to be Solved by the Invention] As mentioned above, in the conventional bus arbitration method, during the period when a certain bus master is using the bus, even if only a part of the bus width is used, the entire bus width is It was treated as being in use and not vacant. This allows other bus masters to use unused portions of the bus to perform I/Os with small data widths.
There was a problem in that even if an attempt was made to access the device, permission to use the bus could not be obtained.

[0007] The present invention has been made in view of the above circumstances, and its purpose is to allow another bus master to take over the remaining bus width even if a certain bus master is using the bus. I/I with small data width by using the
The object of the present invention is to provide a bus arbitration method that can access O devices.

[0008]

[Means for Solving the Problems] The present invention handles a bus to which input/output devices with different data widths are connected by dividing it into a plurality of unit buses of a predetermined bus width, and handles the bus in response to access requests from each bus master. bus arbitration means for performing bus arbitration for each unit bus, and by this bus arbitration means, a desired I/O
The bus master accesses the I/O device when the use of several unit buses necessary for accessing the I/O device is all permitted.

[0009]

[Operation] In the above structure, when the bus master wishes to access an I/O device of a certain data width, it issues an access request (bus use request) to the bus arbitration means. Upon receiving an access request from a bus master, the bus arbitration means requests access to each unit bus to the requesting bus master based on whether each unit bus is free (or not in use). Give permission/disapproval. As a result, if the requesting bus master is permitted to use all of the several unit buses necessary to access the target I/O device, the requesting bus master can access the same I/O device via the several unit buses.
Access equipment. In other words, even if another bus master is using the bus, if only part of the bus width is used, the requesting bus master may use the remaining bus portion depending on the data width of the target I/O device. This makes it possible to access the same I/O device.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of a computer system to which the present invention is applied. In the same figure,
BUS is an I/O system bus with a bus width of 3n. The system bus BUS consists of three unit buses BU with bus width n.
Consists of S1 to BUS3.

For example, the system bus BUS has three I
/O devices 11, 12, and 13 are connected. Further, two bus masters 21 and 22, for example, which access the I/O devices 11 to 13 using the system bus BUS (unit buses BUS1 to BUS3) are also connected to the system bus BUS. Here, the data width of the I/O device 11 is 2n, and the unit buses BUS1 and BUS2 of the system bus BUS
It is connected to the. Further, the data width of the I/O device 12 is 3n, and the unit buses BUS1 to BUS of the system bus BUS
Connected to BUS3. Furthermore, the data width of the I/O device 13 is n, and the unit bus BU of the system bus BUS
S3 is connected.

The bus masters 21 and 22 include
, 22 (request signal REQ1,
REQ2), a bus arbitration section 30 that performs bus arbitration is connected to each of the unit buses BUS1 to BUS3. The bus arbitration unit 30 selects the unit bus BUS in response to request signals REQ1 and REQ2 from the bus masters 21 and 22.
1, and returns a permission signal ACK1 when the bus BUS1 is vacant. The bus arbitration unit 30 further selects the unit bus BUS in response to request signals REQ1 and REQ2 from the bus masters 21 and 22.
2, and returns the permission signal ACK2 when the same bus BUS2 is vacant, and the unit bus BUS according to the request signals REQ1 and REQ2.
3, and returns a permission signal ACK3 when the bus BUS3 is vacant.

Next, the bus arbitration operation in the system shown in FIG. 1 will be explained. First, the bus master 21
I with a data width of 2n connected to US1 and BUS2
Assume that an attempt is made to access the /O device 11. In this case, the bus master 21 outputs the request signal REQ1 to the bus aviters 31 to 33 (in the bus arbitration unit 30).

[0014] The bus attachers 31 to 33 are connected to the bus master 21.
When the request signal REQ1 is received from , the status of the corresponding unit buses BUS1 to BUS3 is checked, and the status of the corresponding unit buses BUS1 to BUS3 is checked.
Only when BUS3 is vacant, the same bus BUS1~B
Active authorization signal A to authorize use of US3
Outputs CK1 to ACK3.

[0015] The bus master 21, as in this example,
Request signal REQ1 to access device 11
When the I/O device 11 is output, permission signals ACK1 and ACK2 that permit use of the unit buses BUS1 and BUS2 to which the I/O device 11 is connected are monitored. and bus master 2
1 is a permission signal AC in response to a request signal REQ1.
When both K1 and ACK2 become active, the I/O device 11 is activated via unit buses BUS1 and BUS2.
access.

Now, while the bus master 21 is accessing the I/O device 11, the bus master 22 accesses the unit bus BU.
Assume that it becomes necessary to access the I/O device 13 connected to S3 and having a data width of n. In this case, the bus master 22 outputs the request signal REQ2 to the bus aviters 31 to 33.

[0017] The bus attachers 31 to 33 are connected to the bus master 22.
When the request signal REQ2 is received from the controller, bus arbitration is performed in the same way as when the request signal REQ1 is received, and the use of the corresponding unit buses BUS1 to BUS3 is permitted only when the corresponding unit buses BUS1 to BUS3 are free. outputs active permission signals ACK1 to ACK3 for Here, since only the unit bus BUS3 is vacant, only the bus aviter 33 outputs the active permission signal ACK3.

The bus master 22, as in this example,
Request signal REQ2 to access device 13
If the I/O device 13 is connected to the unit bus BUS3, the permission signal ACK3 is output.
to monitor. Then, when the bus master 22 receives the active permission signal ACK3 from the bus avita 33 in response to the request signal REQ2 as described above, the bus master 22 receives the unit bus B.
The operation of accessing the I/O device 13 via the US3 is started. As a result, I/O device 1 by bus master 21
In parallel with the access to I/1 by bus master 22,
Access to the O device 13 is performed.

It is assumed that the access by the bus master 21 to the I/O device 11 eventually ends, and only the access to the I/O device 13 by the bus master 22 continues. In this state, in the bus master 21, unit buses BUS1 to B
I/O device 1 with a data width of 3n connected to US3
Assume that it is necessary to access 2. in this case,
The bus master 21 again outputs the request signal REQ1 to the bus aviters 31-33.

While the bus master 22 is accessing the I/O device 13 (via the unit bus BUS3), the bus master 21
When the request signal REQ1 is output from the bus avitor 31, the permission signals ACK1 and ACK2 from the bus aviters 31 and 32 become active immediately, but the permission signal ACK3 from the bus avita 33 remains active until the bus master 22 finishes accessing the I/O device 13. Not active. When the bus master 21 outputs a request signal REQ1 to access the I/O device 12, it monitors permission signals ACK1 to ACK3 that permit use of unit buses BUS1 to BUS3 to which the I/O device 12 is connected. . Then, the bus master 21 performs the I/O operation via the unit buses BUS1 to BUS3 at the time when all the permission signals ACK1 to ACK3 become active (in this embodiment, when the access to the I/O device 13 by the bus master 22 is completed). The operation to access the O device 12 is started.

With the I/O device access according to the above bus arbitration, the system shown in FIG.
O devices 11 and 13 are accessed frequently by I whose bus width is large.
If the access frequency is higher than the access frequency to the /O device 12, the system bus BUS is used more efficiently and the system performance is greatly improved.

Note that in the system of FIG. 1, bus master 2
Request signals REQ1 and REQ2 from 1 and 22 at the same time
Although the configuration does not take into account bus arbitration based on priority control when a This can be handled by applying priority control similar to conventional bus arbitration. For example, a function is provided in the bus masters 21 and 22 to monitor access requests (request signals) from other bus masters,
When a permission signal is returned from the bus arbitration unit 30, it is possible to deal with the situation by configuring a configuration in which the bus master with the highest priority among the bus masters in the access request state can use the permitted bus.

In addition, request signals REQ1 and REQ from the bus masters 21 and 22 are stored in the bus aviters 31 to 33.
It is also possible to provide a function to perform bus arbitration based on priority control in response to No. 2, and to selectively output a permission signal to the bus master with the highest priority. In this configuration, unlike the system of FIG. 1, there are two types of permission signals from the bus aviters 31 to 33, one for the bus master 21 and one for the bus master 22.

However, in the above bus arbitration, bus master 2
Request signals REQ1 and REQ2 from 1 and 22 at the same time
When this is issued, a problem arises in that a bus master with a low priority cannot use the unit bus necessary for accessing the target I/O device even if the unit bus is vacant. As a countermeasure against this problem, it is conceivable to adopt a configuration in which the bus masters 21 and 22 output request signals only to the bus masters that perform bus arbitration for the unit buses necessary for accessing the target I/O device. In such a configuration, for example, the bus master 21 outputs a request signal only to the bus abiters 31 and 32 in order to access the I/O device 11, and at the same time, the bus master 22 outputs a request signal to the bus abiters 31 and 32 in order to access the I/O device 13. If the request signal is output only to bus master 21, 2
2 can simultaneously access the target I/O devices 11 and 13, respectively.

[0025] In the above embodiment, the case where there are two bus masters has been described, but the present invention can be similarly applied to a case where there are three or more bus masters, and the same applies to the number of I/O devices. Further, in the embodiment described above, a case has been described in which the system bus BUS is divided into three parts, but the invention is not limited to this. However, I/O connected to the system bus BUS
It is most preferable to divide the smallest data width of the data width of the device into units and perform bus arbitration for each divided bus (unit bus) in terms of improving the usage efficiency of the system bus BUS.

[0026]

[Effects of the Invention] As detailed above, according to the present invention,
By dividing a bus to which input/output devices with different data widths are connected into multiple unit buses of a predetermined bus width and performing bus arbitration for each unit bus, it is possible to eliminate the possibility that a certain bus master is using the bus. If only a part of the bus width is used, another bus master can use the remaining part to access an I/O device with a small data width. In a system where /O devices are frequently accessed, bus usage efficiency is significantly increased and system performance is greatly improved.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing an embodiment of a computer system to which a bus arbitration method of the present invention is applied.

[Explanation of symbols]

BUS...System bus, BUS1-BUS3...Unit bus, 11-13...I/O equipment, 21-23...Bus master,
30... Bus arbitration department, 31-33... Bus Abita.

Claims (1)

[Claims] Claim 1: In a computer system comprising a bus to which input/output devices having different data widths are connected, a plurality of unit buses having a predetermined bus width constituting the bus, and accessing the input/output devices via the bus. a plurality of bus masters that perform bus arbitration for each of the unit buses in response to access requests from the bus masters; A bus arbitration method that accesses the same input/output device when the use of all of the above-mentioned unit buses necessary for the above-mentioned operation is permitted.