WO2004102404A1

WO2004102404A1 - Data transfer apparatus

Info

Publication number: WO2004102404A1
Application number: PCT/JP2003/005984
Authority: WO
Inventors: Masatoshi Koshiba
Original assignee: Fujitsu Limited
Priority date: 2003-05-14
Filing date: 2003-05-14
Publication date: 2004-11-25
Also published as: JPWO2004102404A1

Abstract

A data transfer apparatus has a storage circuit to which data are transferred via a common bus, peripheral circuits, and data transfer circuit. Each peripheral circuit has a buffer connected to the common bus and outputs a data transfer request depending on the data quantity of the buffer. The data transfer circuit respond to each data transfer request, to carry out data transfer between the corresponding buffers and the storage circuit. Each of low-speed peripheral circuits except a high-speed peripheral circuit with the highest transfer rate out of the peripheral circuits outputs a data transfer request in a predetermined time after the quantity of data in the buffer reaches a quantity of data to be outputted. The high-speed peripheral circuit outputs a data transfer request in a time shorter than a predetermined time after the buffer data quantity reachea a quantity of data in the buffer to be outputted. Thus, the order of data transfer by the request of the low-speed peripheral circuit and that of data transfer by the request of the high-speed peripheral circuit are changed. As a result, data that are indispensably transferred within a fixed period are reliably transferred.

Description

Description Data transfer device Technical field

The present invention relates to a data transfer device that transfers data by direct memory access (DMA) transfer. Background art

In general, a data transfer device directly transfers data between peripheral circuits and memory through a bus without using a CPU as in software transfer (program transfer) in order to perform high-speed and large-capacity data transfer. It has a DMA transfer function to transfer data. The DMA transfer is performed by a DMAC (DMA Controller). When a peripheral circuit requests DMA transfer, the DMAC requests the CPU to release the bus. If the CPU can release the bus, it passes the right to use the bus to the DMAC and puts the bus into a high-impedance state. The DMAC transfers the data of the peripheral circuit (or memory) that requested the DMA transfer to the memory (or the peripheral circuit that requested the DMA transfer) through the bus. The DMAC returns the right to use the bus to the CPU upon completion of the DMA transfer.

Generally, a DMAC has a plurality of channels for performing DMA transfer independently of each other, and the priority is determined among the channels. For example, when the DMAC receives a DMA transfer request to a higher-priority channel while a lower-priority channel is performing a DMA transfer, the DMAC determines the minimum unit of transfer block for the lower-priority channel. After the DMA transfer is completed, the higher priority channel is made to perform the DMA transfer. When the DMA transfer of the higher priority channel is completed, the DMAC causes the lower priority channel to continue the interrupted DMA transfer. For example, moving image data used for displaying moving images generally requires data transfer within a certain period of time. Therefore, such DMA transfer of moving image data is realized by assigning to a channel having a higher priority. However, if the access time (data read time or data write time) of the peripheral circuit that outputs the DMA transfer request assigned to the lower priority channel is long, that is, if the transfer rate is small, the following problems occur. Will happen. If a DMA transfer of moving image data is requested to a higher priority channel during DMA transfer of a lower priority channel, the lower priority channel cannot immediately suspend DMA transfer. . As a result, data subject to DMA transfer of a channel with a higher priority may not be transferred within a certain period. As a result, the moving image cannot be displayed normally.

Also, if DMA transfer requests to a channel with a higher priority frequently occur, a DMA transfer request to a channel with a lower priority may not be accepted. That is, a channel with a low priority cannot perform DMA transfer even if it receives a DMA transfer request.

On the other hand, in a system composed of a central processing unit connected by a bus and a plurality of communication control adapters, the purpose of maximizing the transfer capability of the bus when performing DMA transfer via the bus is to A method of changing the data transfer speed of each communication control adapter is disclosed in, for example, Japanese Patent Application Laid-Open No. 5-134977. The prior art documents related to the present invention are listed below.

(Patent Document)

(1) Japanese Patent Application Laid-Open No. 5-134797 Disclosure of the Invention

SUMMARY OF THE INVENTION An object of the present invention is to provide a data transfer device capable of reliably transferring data that must be transferred within a certain period.

Another object of the present invention is to provide a data transfer device capable of reliably performing data transfer in response to a data transfer request from any peripheral circuit.

In one form of the data transfer device of the present invention, the data transfer device includes a common bus used for data transfer, a storage circuit to which data is transferred via the common bus, a plurality of peripheral circuits, and a data transfer circuit. And Each peripheral circuit has a buffer connected to the common bus, and outputs a data transfer request according to the data amount of the buffer. De The data transfer circuit performs data transfer between the corresponding buffer and the storage circuit in response to each data transfer request. Each of the low-speed peripheral circuits except the high-speed peripheral circuit with the highest transfer rate among the peripheral circuits outputs a data transfer request after a predetermined time from when the amount of data in the corresponding buffer becomes the amount to output the data transfer request. I do. The high-speed peripheral circuit outputs the data transfer request after a time shorter than a predetermined time after the data amount of the corresponding buffer becomes the amount to output the data transfer request. .

By delaying the timing at which a low-speed peripheral circuit outputs a data transfer request by a predetermined time, the data transfer circuit can precede a data transfer request from a high-speed peripheral circuit that should normally be accepted after a data transfer request from a low-speed peripheral circuit. Can be accepted. Therefore, the order of the data transfer in response to the data transfer request from the low-speed peripheral circuit and the data transfer in response to the data transfer request from the high-speed peripheral circuit can be switched. As a result, when a high-speed peripheral circuit outputs a data transfer request that is indispensable for a certain period of time, the data transfer can be reliably performed.

In another form of the data transfer device of the present invention, each low-speed peripheral circuit has a register for setting a predetermined time. Each low-speed peripheral circuit outputs a data transfer request after a predetermined time set in the register, after the amount of data in the buffer reaches the amount to output the data transfer request.

By providing a register in each peripheral circuit, the predetermined time can be made variable. Therefore, it is possible to cope with a change in the transfer rate of the low-speed peripheral circuit and a change in the number of data transfer requests that can be accepted by the data transfer circuit.

In another form of the data transfer device of the present invention, the data transfer circuit preferentially performs data transfer in response to a data transfer request having the highest priority and performs data transfer every time a predetermined amount of data is transferred. Rotate the priority of the data transfer request. Specifically, every time a predetermined amount of data transfer is performed, the data transfer circuit sets the priority of the data transfer request corresponding to the performed data transfer to the lowest, and sets the priority of the other data transfer requests to each. Bring it up. Therefore, data transfer can be reliably performed in response to a data transfer request from any peripheral circuit.

In another aspect of the data transfer device of the present invention, the predetermined time until the low-speed peripheral circuit outputs a data transfer request is set longer as the transfer rate is smaller. For this reason, Data transfer in response to a data transfer request from a low-speed peripheral circuit having a high transfer rate can be prevented from being delayed due to the effect of data transfer in response to a data transfer request from a low-speed peripheral circuit having a low transfer rate.

In another form of the data transfer device of the present invention, the high-speed peripheral circuit outputs the data transfer request immediately after the data amount of the buffer becomes the amount to output the data transfer request. Therefore, it is possible to prevent the data transfer in response to the data transfer request from the high-speed peripheral circuit from being performed unnecessarily late.

In another form of the data transfer device of the present invention, the data transfer circuit is a direct memory access controller that performs data transfer by direct memory access transfer. Even when the data transfer circuit is configured as a direct memory access controller, data that must be transferred can be reliably transferred within a certain period. In another form of the data transfer device of the present invention, a peripheral circuit in which data is written to a buffer by data transfer should output a data transfer request when the data amount of the buffer becomes smaller than a predetermined amount. Recognize. This prevents the buffer from being empty. As a result, the amount of data in the buffer can be optimally controlled, and malfunction of peripheral circuits can be prevented.

In another aspect of the data transfer device of the present invention, a peripheral circuit from which data is read from the buffer by data transfer should output a data transfer request when the data in the buffer becomes larger than a predetermined amount. Recognize. Therefore, it is possible to prevent the buffer from overflowing. As a result, the amount of data in the buffer can be optimally controlled, and malfunction of peripheral circuits can be prevented.

In another aspect of the data transfer device of the present invention, the data in the buffer of the high-speed peripheral circuit is moving image data. For this reason, in general, moving image data, which is data that must be transferred within a certain period, can be reliably transferred.

In another aspect of the data transfer device of the present invention, the data in the buffer of the high-speed peripheral circuit is audio data. For this reason, in general, voice data, which is data that must be transferred within a certain period, can be reliably transferred.

In another aspect of the data transfer device of the present invention, the peripheral circuit and the data transfer circuit are formed on individual semiconductor chips. Peripheral circuits and data transfer circuits are separate Even if it is formed on a conductive chip, it is possible to reliably transfer data that must be transferred within a certain period.

In another form of the data transfer device of the present invention, the peripheral circuit and the data transfer circuit are formed on the same semiconductor chip. Even when the peripheral circuit and the data transfer circuit are formed on the same semiconductor chip, it is possible to reliably transfer data that must be transferred within a certain period. Brief description of the drawings

FIG. 1 is a block diagram showing a first embodiment of the data transfer device of the present invention. FIG. 2 is an explanatory diagram illustrating an example of the DMA transfer according to the first embodiment.

FIG. 3 is an explanatory diagram showing another example of the DMA transfer in the first embodiment. FIG. 4 is a block diagram showing a second embodiment of the data transfer device of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a first embodiment of the data transfer device of the present invention.

The data transfer device 100 has semiconductor chips 10, 12, ROM 14, SDRAM 16 (storage circuit), external bus EBUS and SDRAM dedicated bus SBUS.

Semiconductor chip 10 has CPU core 10a, external bus interface 10b, S

It has DRAM interface 10c, DMAC 10d (data transfer circuit) and main bus MBUS.

The CPU core 10a controls each unit according to a program recorded in the ROM 14, and executes various arithmetic processes. The external bus interface 10b functions as an interface when exchanging data with the ROM 14 and the semiconductor chip 12. The SDRAM interface 10c functions as an interface when exchanging data with the SDRAM 16.

The DMAC 10d has channels CH0 to CH2 for performing DMA transfer independently of each other. The activation factors of channels CH0 to CH2 are in DMA transfer requests R0 to R5. Each can be set from 6. In response to the assigned DMA transfer request, channels CH0 to CH2 perform the DMA transfer between the buffer of the peripheral circuit (one of P0 to P5) that output the assigned DMA transfer request and the SDRAM 16. carry out. The channels CH0 to CH2 have, as an initial value, a higher priority as the channel number is smaller, that is, a priority expressed by a relationship of CH0>CHI> CH2. In the DMAC 10d, the channel with the highest priority performs the DMA transfer with priority.

The DMAC 10d rotates the priority between channels each time a predetermined amount of DMA transfer is performed. Specifically, each time a predetermined amount of DMA transfer is performed, the DMAC I Od lowers the priority of the channel that has performed the DMA transfer and raises the priority of each of the other channels.

The main bus MBUS connects the CPU core 10a, the external bus interface 10b, the SDRAM interface 10c, and the DMAC 10d to each other, and enables data transfer between them.

The semiconductor chip 12 has an external bus interface 12a, peripheral circuits P0 to P5, and a local bus LBUS (common bus).

The external bus interface 12 a functions as an interface for exchanging data with the semiconductor chip 10.

The peripheral circuit P0 operates as a video signal input circuit, and has a buffer BUF0 and a register REG0 connected to the local bus LBUS. The value of register REG0 can be set arbitrarily. The peripheral circuit P0 stores moving image data generated from a video signal supplied from a video input terminal (not shown) in a buffer BUF0. The peripheral circuit P0 recognizes that the data transfer request R0 should be output when the data amount of the buffer BUF0 becomes larger than a predetermined amount, and issues the data transfer request R0 after a predetermined time set in the register REG0. Actual output.

In response to the data transfer request R0, the channel to which the data transfer request R0 is assigned in the DMAC 10d is responded to by the DMA transfer via the SDRAM dedicated bus SBUS, main bus MBUS, external bus EBUS and local bus LBUS. Then, read data from buffer BUF0 and write the read data to SDRAM16. The peripheral circuit P1 operates as a video signal output circuit and connects to the local bus LBUS. It has a buffer BUF1 and a register REG1 to be connected. The value of register REG1 can be set arbitrarily. The peripheral circuit P1 generates a video signal from the moving image data stored in the buffer BUF1, and outputs the video signal from a video output terminal (not shown). The peripheral circuit P1 recognizes that the data transfer request R1 should be output when the data amount of the buffer BUF1 becomes smaller than a predetermined amount, and after a predetermined time set in the register REG1, requests the data transfer request R1. R1 is actually output.

In response to the data transfer request R1, the channel to which the data transfer request R1 in DMAC10d is assigned via the dedicated bus SBUS, the main bus MBUS, the external bus EBUS, and the local bus LBUS in response to the data transfer request R1. Data is read from SDRAM 16 by DMA transfer, and the read data is written to buffer BUF1. The peripheral circuit P2 operates as an audio signal input circuit, and has a buffer BUF2 and a register REG2 connected to the local bus LBUS. The value of register REG2 can be set arbitrarily. The peripheral circuit P2 stores audio data generated from an audio signal supplied from an audio input terminal (not shown) in a buffer BUF2. The peripheral circuit P2 recognizes that the data transfer request R2 should be output when the data amount of the buffer BUF2 becomes larger than a predetermined amount.After a predetermined time set in the register REG2, the peripheral circuit P2 issues the data transfer request R2. Actual output.

In response to the data transfer request R2, the channel to which the data transfer request R2 in DMAC10d is assigned is transmitted via the dedicated bus SBUS, the main bus MBUS, the external bus EBUS, and the local bus LBUS in response to the data transfer request R2. Data is read from buffer BUF2 by DMA transfer, and the read data is written to SDRAM16. The peripheral circuit P3 operates as an audio signal output circuit, and has a buffer BUF3 and a register REG3 connected to the local bus LBUS. The value of register REG3 can be set arbitrarily. The peripheral circuit P3 generates an audio signal from the audio data stored in the buffer BUF3 and outputs the audio signal from an audio output terminal (not shown). The peripheral circuit P3 recognizes that the data transfer request R3 should be output when the data amount of the buffer BUF3 becomes smaller than the predetermined amount, and actually executes the data transfer request R3 after a predetermined time set in the register REG3. Output to

The channel to which data transfer request R3 in DMAC10d is assigned is In response to data transfer request R3, data is read from SDRAM 16 by DMA transfer via SDRAM dedicated bus SBUS, main bus MBUS, external bus EBUS and local bus LBUS, and the read data is written to buffer BUF3. Including. Peripheral circuit P4 operates as a PC card interface compliant with PCMCIA (Personal Computer Memory Card International Association) 2. \ / JEI DA (Japan Electronic Industry Development Association) 4.2, and a buffer connected to local bus LBUS It has a BUF4 and a register REG4. The value of register REG4 can be set arbitrarily. When reading data from the PC card inserted into the PC card slot (not shown), the peripheral circuit P4 stores the data read from the PC card in the buffer BUF4. The peripheral circuit P4 recognizes that the data transfer request R4 should be output when the data amount of the buffer BUF4 becomes larger than the predetermined amount.After a predetermined time set in the register REG4, the peripheral circuit P4 issues the data transfer request R4. Actually output.

In response to the data transfer request R4, the channel to which the data transfer request R4 in the DMAC 10d is assigned is transferred by the DMA transfer via the S DRAM dedicated bus SBUS, the main bus MBUS, the external bus EBUS and the local bus LBUS. Read data from buffer BUF4 and write the read data to SDRAM16. The peripheral circuit P5 operates as a USB (Universal Serial Bus) 1.1-compliant USB interface, and has a buffer BUF5 and a register REG5 connected to the local bus LBUS. The value of register REG5 can be set arbitrarily. When transmitting data to the USB (not shown), the peripheral circuit P5 transmits the data stored in the buffer BUF5 to the USB. The peripheral circuit P5 recognizes that the data transfer request R5 should be output when the data amount of the buffer BUF5 becomes smaller than a predetermined amount, and after a predetermined time set in the register REG5, the peripheral circuit P5 actually executes the data transfer request R5. Output to.

In response to the data transfer request R5, the channel to which the data transfer request R5 in the DMAC 10d has been assigned responds to the data transfer request R5 by DMA transfer via the SDRAM dedicated bus SBUS, main bus MBUS, external bus EBUS and local bus LBUS. And reads data from SDRAM 16 and writes the read data to buffer BUF5. ' The local path LBUS connects the external bus interface 12a and the peripheral circuits P0 to P5 to each other, and enables data transfer between them.

The SDRAM 16 temporarily stores a program to be executed by the CPU lOa, data being processed, and the like. The external bus EBUS connects the semiconductor chips 10 and 12 and the ROM 14 to each other, and enables data transfer between them. The SDRAM dedicated bus SBUS connects the semiconductor chip 10 and the SDRAM 16 to each other, and enables data transfer between them.

Hereinafter, the operation of the data transfer device 100 will be described.

FIG. 2 shows an example of the DMA transfer when the peripheral circuits P1 and P4 are operated. DMA transfer requests Rl and R4 are assigned to channels CH0 and CHI, respectively. Since the data in the buffer BUF1 of the peripheral circuit P1 is moving image data, high-speed DMA transfer is required for channel CH0, and two DMA transfers must be completed within L1 for a certain period of time. Since the data in the buffer BUF4 of the peripheral circuit P4 is data read from the PC card, channel CH1 does not require high-speed DMA transfer and performs time-free DMA transfer.

Note that the transfer rate of the peripheral circuit P1 is much higher than the transfer rate of the peripheral circuit P4. That is, the time required for the DMA transfer performed by channel CH1 is much longer than the time required for the DMA transfer performed by channel CH0. In other words, the peripheral circuit P1 operates as a high-speed peripheral circuit, and the peripheral circuit P4 operates as a low-speed peripheral circuit. The upper part of FIG. 2 shows an example of the DMA transfer in the data transfer device 100 of the present invention. In FIG. 2A, the peripheral circuit P1 recognizes that the data amount of the buffer BUF1 has become smaller than a predetermined amount during the DMA transfer of the channel CH1, and immediately outputs a DMA transfer request R1. Here, the value of the register REG1 is preset to 0 which is smaller than the predetermined time T1. In FIG. 2 (b), the local path LBUS is occupied by the DMA transfer of channel CH0 after the completion of the DMA transfer of channel CH1.

In FIG. 2C, the peripheral circuit P4 recognizes that the data amount of the buffer BUF4 has become larger than a predetermined amount. However, the peripheral circuit P4 does not output the DMA transfer request R4 until the predetermined time T1 has elapsed. Here, the value of register REG4 is Four

10 Predetermined time Tl is preset. In FIG. 2 (d), the peripheral circuit P1 recognizes that the data amount of the buffer BUF1 has become smaller than a predetermined amount, and immediately outputs a DMA transfer request R1. In FIG. 2 (e), the local bus LBUS is occupied by DMA transfer of channel CH0. Therefore, channel CH0 can complete two DMA transfers within a certain period of time L1.

In FIG. 2 (f), the peripheral circuit P4 recognizes the elapse of the predetermined time T1, and outputs a DMA transfer request R4. In FIG. 2 (g), the local bus LBUS is occupied by the DMA transfer of the channel CH1 after the completion of the DMA transfer of the channel CH0. The DMAC 10d rotates the priority between channels every time a predetermined amount of data transfer is performed. For this reason, in FIG. 2 (f), even if the data transfer request R4 conflicts with the data transfer request R1, the DMAClod causes the channel CH1 to perform the DMA transfer. Therefore, the DMAC I Od reliably executes the DMA transfer in response to any data transfer request assigned to the channels CH0 and CHI. The lower part of FIG. 2 shows an example of a DMA transfer before applying the present invention. Therefore, when the peripheral circuit P4 recognizes that the data amount of the buffer BUF4 has become smaller than the predetermined amount, the peripheral circuit P4 immediately outputs the DMA transfer request R4. In FIG. 2 (h), the peripheral circuit P1 recognizes that the data amount of the buffer BUF1 has become smaller than a predetermined value while performing the DMA transfer of the channel CH1, and immediately outputs the DMA transfer request R1. In FIG. 2 (i), the local path LBUS is occupied by the DMA transfer of the channel CH0 after the completion of the DMA transfer of the channel CH1.

In FIG. 2 (j), the peripheral circuit P4 recognizes that the data amount of the buffer BUF1 has become smaller than the predetermined amount during the DMA transfer of the channel CHI, and immediately outputs the DMA transfer request R4. In FIG. 2 (k), the local bus LBUS is occupied by DMA transfer of channel CH1.

In FIG. 2 (1), the peripheral circuit P1 recognizes that the data amount of the buffer BUF1 has become smaller than a predetermined amount during the DMA transfer of the channel CH1, and immediately outputs a DMA transfer request R1. In FIG. 2 (m), the local bus LBUS is occupied by the DMA transfer of the channel CH0 after the completion of the DMA transfer of the channel CH1. Therefore, channel CH0 must complete two DMA transfers within L1 for a certain period. Can not. That is, the video signal output from the video output terminal is interrupted.

As described above, by delaying the timing at which the peripheral circuit P4 outputs the DMA transfer request R4 by the predetermined time T1, the DMAC 10d precedes the DMA transfer request R1 that would otherwise be accepted after the DMA transfer request R4. Accept. Therefore, the order in which the DMA transfer performed by the channel CH1 and the DMA transfer performed by the channel CH0 are switched. As a result, channel CH0 reliably completes two DMA transfers within L1 for a certain period.

FIG. 3 shows an example of the DMA transfer when the peripheral circuits P3, P4, and P5 are operated.

DMA transfer requests R3, R4, and R5 are assigned to channels CH0, CH1, and CH2, respectively. Since the data in the buffer BUF3 of the peripheral circuit P3 is audio data, high-speed DMA transfer is required for channel CH0, and two DMA transfers must be completed within a certain period of time L2. Since the data in the buffer BUF4 of the peripheral circuit P4 is data read from the PC card, channel CH1 does not require high-speed DMA transfer and performs time-free DMA transfer. Since the data in the buffer BUF5 of the peripheral circuit P5 is data to be transmitted to the USB, the channel CH2 does not require a faster DMA transfer than the channel CH1, and performs time-free DMA transfer.

Note that the transfer rate of the peripheral circuit P3 is much higher than the transfer rate of the peripheral circuit P4. That is, the time required for the DMA transfer performed by channel CH1 is much longer than the time required for the DMA transfer performed by channel CH0. The transfer rate of the peripheral circuit P5 is lower than that of the peripheral circuit P4. That is, the time required for the DMA transfer performed by channel CH2 is longer than the time required for the DMA transfer performed by channel CH1. In other words, the peripheral circuit P3 operates as a high-speed peripheral circuit, and the peripheral circuits P4 and P5 operate as low-speed peripheral circuits.

In FIG. 3A, the peripheral circuit P4 outputs a DMA transfer request R4 during the execution of the DMA transfer of the channel CH2. In FIG. 3B, the local path LBUS is occupied by the DMA transfer of the channel CH1 after the completion of the DMA transfer of the channel CH2. In FIG. 3C, the peripheral circuit P5 recognizes that the data amount of the buffer BUF5 has become smaller than a predetermined amount. However, the peripheral circuit P5 does not output the DMA transfer request R5 until the predetermined time T3 has elapsed. Here, the value of the register REG5 is preset to a predetermined time T3. In FIG. 3 (d), the peripheral circuit P3 outputs a DMA transfer request R3 during the execution of the DMA transfer of the channel CH1. In FIG. 3 (e), the local bus LBUS is occupied by the DMA transfer of the channel CH0 after the completion of the DMA transfer of the channel CH1.

In FIG. 3 (f), the peripheral circuit P4 recognizes that the data amount of the buffer BUF4 has become larger than a predetermined amount. However, the peripheral circuit P4 does not output the DMA transfer request R4 until the predetermined time T2 has elapsed. Here, the value of the register REG4 is set in advance to a predetermined time T2 smaller than the predetermined time T3. In FIG. 3 (g), the peripheral circuit P3 recognizes that the data amount of the buffer BUF3 has become smaller than a predetermined amount, and immediately outputs a DMA transfer request R3. Here, the value of the register REG3 is preset to 0 which is shorter than the predetermined time T2, # 3. In FIG. 3 (h), the low-power bus LBUS is occupied by DMA transfer on channel CH0. Therefore, channel CH0 can complete two DMA transfers within a certain period of time L2.

In FIG. 3 (i), the peripheral circuit P4 recognizes the elapse of the predetermined time T2 and outputs a DMA transfer request R4. In FIG. 3 (j), the local bus LBUS is occupied by the DMA transfer of the channel CH1 after the completion of the DMA transfer of the channel CH0. In FIG. 3 (k), the peripheral circuit P5 recognizes the elapse of the predetermined time T3 and outputs a DMA transfer request R5. In FIG. 3 (1), the local bus LBUS is occupied by the DMA transfer of the channel CH2 after the completion of the DMA transfer of the channel CH1.

As described above, by delaying the timing at which the peripheral circuits P4 and P5 output the DMA transfer requests R4 and R5 by the predetermined times T2 and Τ3, respectively, even when the two low-speed peripheral circuits Ρ4 and Ρ5 operate simultaneously, Channel CH0 ensures that two DMA transfers are completed within L1 for a fixed period. Further, by setting the predetermined time T3 of the peripheral circuit P5 to be longer than the predetermined time T2 of the peripheral circuit P4, it is possible to prevent the DMA transfer of the CH1 from being delayed due to the influence of the DMA transfer of the channel CH1.

As described above, the first embodiment has the following advantages. By delaying the timing at which the low-speed peripheral circuit outputs a data transfer request by a predetermined time, the DMAC 10d precedes the data transfer request from the high-speed peripheral circuit that should normally be accepted after the data transfer request from the low-speed peripheral circuit. Can be accepted at any time. Therefore, the order in which the data transfer in response to the data transfer request from the low-speed peripheral circuit and the data transfer in response to the data transfer request from the high-speed peripheral circuit can be changed. As a result, when a high-speed peripheral circuit outputs a transfer request for data that must be transferred within a certain period, data (moving image data and audio data) that must be transferred within a certain period can be reliably transferred.

By providing the registers REG0 to REG5 in the peripheral circuits P0 to P5, the predetermined time from when the data transfer requests R0 to R5 are output to when they are actually output can be varied. Therefore, it is possible to cope with a change in the transfer rate of the peripheral circuits P0 to P5 and a change in the number of acceptable DMA transfer requests (the number of channels) in the DMA CIOd.

The DMAC 10d responds to any data transfer request assigned to the channels CH0 to CH2 in order to rotate the priority between channels each time a predetermined amount of DMA transfer is performed. Can be reliably implemented.

By setting the predetermined time of the low-speed peripheral circuit to be longer as the transfer rate is lower, data transfer in response to a data transfer request from the lower-speed peripheral circuit with a higher transfer rate can be performed by transferring data from the lower-speed peripheral circuit with a lower transfer rate. It is possible to prevent delays due to the effect of data transfer in response to the request.

FIG. 4 shows a second embodiment of the data transfer device of the present invention. The same elements as those described in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

The data transfer device 200 has a semiconductor chip 30, a ROM 14, an SDRAM 16 (memory circuit), an external bus EBUS, and a dedicated bus SBUS for SRAM. The semiconductor chip 30 includes a CPU core 10a, an external bus interface 10b, an SDRAM interface 10c, a DMAC 10d (data transfer circuit), a bus bridge BB, peripheral circuits P0 to P5, a main path MBUS and a local bus. It has a bus LBUS (common bus). That is, in the data transfer device 200, DMAC I O d Peripheral circuits P0 to P5 are formed on the same semiconductor chip 30. The data transfer device 200 is different from the data transfer device 200 in that the DMAC 1d and the peripheral circuits P0 to P5 are formed on separate semiconductor chips 10 and 20 except that the DMA transfer path is different. The operation is the same as that of the data transfer device 100 of the first embodiment.

The bus bridge BB functions as an interface for exchanging data between the main bus MBUS and the low-power bus LBUS. Accordingly, the channels CH0 to CH2 of the DMA C Od respond to the assigned DMA transfer request. The assigned DMA via the local bus LBUS, the main bus MBUS, and the dedicated path SBUS for the DRAM. Executes DMA transfer between the buffer of the peripheral circuit that has output the transfer request and SDRAM 16.

As described above, also in the second embodiment, the same effects as in the first embodiment can be obtained.

In the first and second embodiments, examples have been described in which the peripheral circuit P4 (or the peripheral circuit P5) operates as a PC card interface (or a USB interface). The present invention is not limited to such an embodiment. For example, the peripheral circuit P4 (or the peripheral circuit P5) operates as an I ² C (Inter Integrated Circuit) interface that does not require much high-speed DMA transfer between the buffer BUF4 (or the buffer BUF5) and the SDRAM 16. Is also good.

As described above, the present invention has been described in detail. However, the above-described embodiment and its modifications are merely examples of the present invention, and the present invention is not limited thereto. Obviously, modifications can be made without departing from the present invention. Industrial potential

The data transfer device of the present invention can reliably transfer data that must be transferred within a certain period.

The data transfer device of the present invention can cope with a change in the transfer rate of the low-speed peripheral circuit and a change in the number of data transfer requests that can be accepted by the data transfer circuit.

The data transfer device of the present invention responds to data transfer requests from any of the peripheral circuits, and can reliably perform data transfer.

In the data transfer device of the present invention, data from a low-speed peripheral circuit having a high transfer rate Data transfer in response to a transfer request can be prevented from being delayed due to the effect of data transfer in response to a data transfer request from a low-speed peripheral circuit with a low transfer rate.

Claims

The scope of the claims

(1) a common bus used for data transfer,

A storage circuit to which data is transferred via the common bus;

A plurality of peripheral circuits each having a buffer connected to the common bus and outputting a data transfer request in accordance with the data amount of the buffer;

A data transfer circuit for performing data transfer between the corresponding buffer and the storage circuit in response to each of the data transfer requests;

Each of the low-speed peripheral circuits excluding the high-speed peripheral circuit having the highest transfer rate among the peripheral circuits transmits the data transfer after a predetermined time from when the data amount of the corresponding buffer becomes the amount to output the data transfer request. Output the request,

The data transfer request, wherein the high-speed peripheral circuit outputs the data transfer request after a time shorter than the predetermined time after the data amount of the corresponding buffer becomes an amount to output the data transfer request. apparatus.

(2) In the data transfer device according to claim 1,

Each of the low-speed peripheral circuits has a register for setting the predetermined time, and after the data amount of the buffer reaches an amount to output the data transfer request, the predetermined time set in the register. A data transfer device for outputting the data transfer request later.

(3) In the data transfer device according to claim 1,

The data transfer circuit prioritizes and performs data transfer in response to the data transfer request having the highest priority, and changes the priority of the data transfer request every time a predetermined amount of data transfer is performed. A data transfer device characterized by rotating.

(4) In the data transfer device according to claim 1,

The data transfer device, wherein the predetermined time of the low-speed peripheral circuit is set longer as the transfer rate is lower.

(5) In the data transfer device according to claim 1,

The high-speed peripheral circuit outputs the data transfer request immediately after the amount of data in the buffer reaches an amount to output the data transfer request. Data transfer device.

(6) In the data transfer device according to claim 1,

The data transfer device, wherein the data transfer circuit is a direct memory access controller that performs data transfer by direct memory access transfer.

(7) In the data transfer device according to claim 1,

Among the peripheral circuits, a peripheral circuit to which data is written to the buffer by data transfer recognizes that the data transfer request should be output when the data amount of the buffer becomes smaller than a predetermined amount. A data transfer device characterized by the above-mentioned.

(8) In the data transfer device according to claim 1,

Among the peripheral circuits, a peripheral circuit from which data is read from the buffer by data transfer recognizes that the data transfer request should be output when the data amount of the buffer becomes larger than a predetermined amount. A data transfer device characterized by the above-mentioned.

(9) In the data transfer device according to claim 1,

The data transfer device, wherein the data in the buffer of the high-speed peripheral circuit is moving image data.

(10) In the data transfer device according to claim 1,

The data transfer device, wherein the data of the buffer of the high-speed peripheral circuit is audio data.

(11) The data transfer device according to claim 1, wherein the peripheral circuit and the data transfer circuit are formed on separate semiconductor chips.

(1 2) In the data transfer device according to claim 1,

The data transfer device, wherein the peripheral circuit and the data transfer circuit are formed on the same semiconductor chip.