JPH07114510A - Control system for fifo threshold value control dma - Google Patents

Abstract

PURPOSE:To eliminate the need for DMA actuation by a processor and to efficiently use FIFO in an I/O by providing a circuit which detects the conditions of the DMA actuation in I/O, making the I/O perform the DMA actuation by itself and control the actuation conditions by itself. CONSTITUTION:A control circuit DMAC 23 is so constituted that DMA from an I/O 2 having transfer data to a transfer destination I/O 5 is actuated when the number of data in the FIFO 231 of the I/O 2 exceeds a certain threshold value. The DMAC 23 is provided with a threshold value control means which dynamically varies the data quantity threshold value for actuating the DMA according to the use state of the FIFO 231. Then the amount of data taken in from a network 11 is monitored by the DMAC 23 at all times and compared with the threshold value, the bus right for a bus where the transfer destination is present is requested on condition that they match each other, and thus the bus right is obtained to perform the DMA. Further, the threshold value is dynamically varied to a proper value each time DMA is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA controller between I / Os existing in different networks, and relates to a DMA system in which DMA activation by a processor is reduced.

[0002]

2. Description of the Related Art In a system having a DMAC for transferring data from a system bus or network to another I / O by DMA in a system as shown in FIG.
For example, in order to absorb the time difference between the timing when the DMAC can secure the bus right of the processor bus and the timing when the data is output from the system bus (or network), a buffer memory configured by a FIFO is placed in the DMAC to transfer the transfer data. There is a technique for holding the bus right of the processor until it can be secured. If the processor has a high-speed transfer mode such as a burst mode, the processor bus can be effectively used to secure a certain amount of data in the buffer memory.

However, there have been cases where the buffer memory overruns or underruns due to factors such as the size and transfer frequency of the buffer memory and the rate of bus right acquisition. Even if overrun or underrun did not occur, there was a possibility that the buffer memory was often empty due to the nature of the activated DMA, and there was a difference that the buffer memory became full soon. . As a solution to this problem, as disclosed in Japanese Patent Laid-Open No. 4-364556 regarding prefetch buffer control, a technique for allocating a buffer capacity according to the performance of a channel device that sends (receives) data. was there.

[0004]

In the technique of allocating the buffer capacity according to the performance of the channel device, the DMAC stores the performance of each channel device in advance, or the DMA is activated. There was a need for a method for the channel device to notify the DMAC of its own transfer capability in some way. Therefore, there are problems that the number of connection lines from the channel device to the DMAC is increased, and that the transfer capability must be set to the DMAC when adding the channel device. The present invention provides a DMAC that appropriately manages the buffer amount without managing such special transfer capability information.

[0005]

In order to solve the above problems, D from an I / O having transfer data to a transfer destination I / O
The control circuit is configured to activate the MA when the number of data in the FIFO of the I / O having the transfer data exceeds a certain threshold, and this control circuit controls the data amount for activating the DMA. Threshold control means is provided for dynamically changing the threshold value according to the usage of the FIFO.

[0006]

According to the DMA system of the present invention, the amount of data in the I / O that takes in data from the network
Always monitors and compares with a threshold value, and on the condition that they match, a bus right request is made to the bus master of the bus having the transfer destination I / O, and when the bus right is obtained, DMA is performed. Then, every time DMA is performed, the threshold value is dynamically changed to an appropriate value.

The condition for terminating the DMA is as in normal DMA, according to the number of transfer words set in advance by the processor, or when the FIFO becomes empty.

[0008]

Embodiments of the DMA according to the present invention will be described below. FIG. 1 is an example of the configuration of a system for performing DMA according to the present invention. 2 captures network data and I / O
I / O for transferring data to the network 5, and data from the network is transferred to the D
It is taken into the FIFO 231 of the MAC 23, and at this time, the value of the write pointer 2311 is sequentially incremented by the increment pulse 211. The value of the write pointer 2311 is input to the FIFO status detection unit 2324 in the address / request control unit 232. This FIFO status detection unit 2324 detects the full or empty state of the FIFO based on the values of the write pointer 2311 and the read pointer 2312, and determines the number of data in the FIFO by the activation comparator 2
It is output to 325a.

When the above-described sequence is repeated and the amount of data stored in the FIFO 22 by the network interface unit 21 becomes equal to the value of the threshold value register 2321a, the output of the activation comparator 2325a becomes valid and the request generator 2327 is set. The request signal 2327a is output, and the bus right is requested by the bus right request signal 2331 to the bus arbiter 4 via the bus interface unit 233.

After this, the bus right permission signal 233 to the I / O2
When 2 is output, the data in the FIFO 231 is transferred to the transfer destination I / O 5 via the bus interface unit 233. At this time, the bus interface unit 233 generates the transfer acknowledge signal 2333, and the read pointer 2312 is updated by this, and the bus interface unit 2 is sequentially updated.
The value of the FIFO data input to 33 changes. The transfer acknowledge signal 2333 is also input to the transfer amount counter 2326 that counts the number of words transferred to the I / O 5. When the I / O of the transfer destination does not have the FIFO structure, the address generated by the address generation unit 2328 is output, but the transfer acknowledge signal is also used for this address update.

The end of DMA is indicated by the byte count register 2
If the mode register 2322 for selecting whether to follow 323 or when the FIFO 231 becomes empty is set to follow the set value of the byte counter register, the transfer from I / O2 to I / O5 is repeated. The request generator 2327 is reset by the output of the termination comparator 2325b which becomes valid when the data amount in the FIFO 231 becomes equal to the value of the byte count register 2323. On the other hand, if the mode register 2322 is set not to follow the byte count register 2323, the request generator 2327 is reset when the FIFO status detection circuit 2324 outputs the empty signal 2324a.

The threshold control circuit 2321 updates the value of the internal threshold register 2321a every time DMA is executed. As a configuration example of this circuit, the FIFO status detection circuit 23 is provided between the start of DMA and the generation of the reset signal of the request generator 227.
If 24 does not output the overflow signal 2324a, the value of the threshold register 2321a is incremented. Conversely, when the overflow signal 2324a is detected, the value of the threshold value register 2321a is decremented. The threshold value dynamically takes an appropriate value while the DMA is repeated in this manner.

Although the above description has been made with respect to the case where the DMAC has a built-in FIFO, considering a threshold detecting means, that is, a new FIFO having a threshold control circuit 2321, such a FIFO is shown in FIG. DMA
It is also conceivable to place it outside C and use the DMAC as an address / request generator.

[0014]

As described above, according to the present invention, the I / O itself performs the DMA activation by providing the circuit for detecting the DMA activation condition inside the I / O, and the I / O activates the activation condition.
Since the O is controlled by itself, the DMA activation by the processor is not necessary and the FIFO in the I / O is efficiently used.

[Brief description of drawings]

FIG. 1 is a system diagram to which a DMA system using the present invention is applied.

FIG. 2 is a diagram showing a part of a DMA controller for implementing the present invention.

FIG. 3 is a system diagram to which a DMA system using the present invention is applied.

FIG. 4 is a configuration diagram of a system that transfers data from an I / O on a network to another I / O.

[Explanation of symbols]

11, 12 ... Network, 2 ... I / O for transferring network data to memory, 21 ... Network interface section, 211 ... Write pointer update signal, 22 ...
FIFO when not built in DMAC, 23 ... DMA
Controller 231, ... FIFO, 2311 ... FIF
O write pointer, 2312 ... FIFO read pointer, 2321 ... Threshold control circuit, 2321a ... DM
A start threshold register, 2322 ... DMA end mode register, 2323 ... Byte count register, 23
24 ... FIFO status detection circuit, 2324a ... Overflow signal, 2324b ... Empty signal, 232
4c ... In-FIFO data amount signal, 2325a ... DMA start comparator, 2325b ... DMA end comparator, 2326 ... Transfer word number counter, 2327 ... DMA
Request generator, 2327a ... DMA request signal, 2328 ... Transfer destination address generator, 23
28a ... Address register, 2328b ... Address incrementer, 2328c ... Transfer destination address, 233 ... Bus interface section, 2331 ... Bus request signal,
2332 ... Bus acknowledge signal, 2333 ... Transfer acknowledge signal, 3 ... System bus having I / O2,
4 ... Arbiter, 5 ... Transfer destination I / O, 6 ... Processor, 6
Register setting path by one processor.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Motonao Sawada, 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa, Ltd., System Development Laboratory, Hitachi, Ltd. (72) Hiroshi Sato, 810 Shimoimaizumi, Ebina, Kanagawa Hitachi, Ltd. Factory Office Systems Division

Claims (4)

[Claims] 1. A DMA control system from a transfer source I / O device to a transfer destination I / O device, wherein the transfer source I / O device has a DMA control device inside, and the DMA control device transfers data. Ex I
FI that stores the data that the I / O acquires from the network
The transfer destination I is detected by detecting that the FO and the number of data stored in the FIFO match or exceed the threshold value set in advance by the setting means in the DMA control device.
Threshold control DMA having means for initiating a data transfer to a bus in which an I / O device is present
control method. 2. A DMA control system from a transfer source I / O device to a transfer destination I / O device, wherein the means for performing the DMA exists inside the transfer source I / O, and also the transfer source I / O. Means for detecting the coincidence or exceeding by accumulating the data existing inside the source I / O fetched from the network and comparing the accumulated number with the threshold value set in the internal setting means. A FIFO threshold control DMA control method comprising means for starting transfer to a transfer destination I / O through an interface with a FIFO included therein. 3. A means for counting the number of data stored internally, a means for setting an arbitrary value from the outside, and a means for comparing the count value with the set value. A FIFO threshold control DMA control method having means for notifying a result to the outside. 4. In the DMA from the transfer source I / O device to the transfer destination I / O device, the transfer source I is set as a condition for starting the DMA.
/ O is a DMA control method that uses the output of a means for comparing the amount of data fetched from the network to the internal FIFO with a value preset in the internal setting means, and the value set in the setting means is used. A FIFO threshold control DMA system having a threshold control circuit that dynamically increases and decreases.