US20040003164A1

US20040003164A1 - PCI bridge and data transfer methods

Info

Publication number: US20040003164A1
Application number: US10/180,115
Authority: US
Inventors: Patrick Boily
Original assignee: Alcatel Canada Inc
Current assignee: Nokia Canada Inc
Priority date: 2002-06-27
Filing date: 2002-06-27
Publication date: 2004-01-01
Also published as: EP1391828A3; US7146451B2; EP1391828A2; US20060015672A1

Abstract

A bridge for interconnecting a processor to a peripheral device by way of a PCI bus may have a read buffer. The bridge autonomously requests data from the peripheral device and places received data in the read buffer. The processor reads the data from the receive buffer. The bridge may have a write buffer. The bridge accumulates data in the write buffer until a triggering event occurs. Upon the occurrence of a triggering event the bridge sends the data in the receive buffer to the peripheral device in a burst.

Description

TECHNICAL FIELD

The invention relates generally to computing and specifically to transferring data across PCI interfaces.

BACKGROUND

PCI (Peripheral Component Interconnect) buses are used commonly in personal computers. PCI chipsets are readily available. PCI buses operating at 33 MHz, 66 MHz and 133 MHz are currently available. However, PCI buses are undesirably inefficient for handling bursty data transfers. In various applications there is a need to transfer a bursty data stream between components.

It is known that the efficiency with which data can be transferred across a PCI bus can be increased by sending data in long bursts. Transferring a burst of data across a PCI bus incurs some overhead. It takes a system-dependent amount of time to set up a PCI bus to make a burst transfer. After the transfer is established a DWord (32 bits) can be transferred on every PCI clock cycle. Where the data transfer is bursty it is not always possible to organize the data into long bursts for transfer across a PCI bus.

There have been efforts to improve the efficiency of data transfer by providing microprocessors which have longer word capabilities between 32 and 64 bytes. Standard compilers typically do not support these capabilities. This makes it necessary to program in assembly language to take advantage of longer word transfer capabilities.

Another way to increase the efficiency with which data is transferred across a PCI bus involves providing an external DMA component. The DMA component performs burst data transfers. However each data transfer involves overhead such as setting up source and destination pointers before the burst transfer. This is not efficient unless the bursts are long.

Davis et al., U.S. Pat. No. 6,298,407 discloses a PCI-to-PCI bridge which includes a control register. Values in the control register specify storage conditions to be met by read and write queues of the bridge.

There are many applications, including various telecommunication applications, where it would be desirable to use a PCI bus but a PCI bus cannot maintain a desired throughput due to the bursty nature of the data being transmitted.

SUMMARY OF THE INVENTION

This invention provides apparatus and methods for transferring data between a processor and a peripheral device across a data bus. The data bus comprises a PCI bus in many embodiments of the invention.

A First aspect of the invention provides a bridge apparatus for permitting a processor to access data from at least one peripheral device. The bridge apparatus comprises a PCI bus interface; a processor interface; a read buffer accessible to a processor by way of the processor interface; and, a controller. The controller is configured to periodically request data from one or more peripheral devices by way of the PCI bus interface and to store the requested data in the read buffer for access by the processor. A processor connected by way of the processor interface can read the data from the read buffer without the need to read data from the peripheral device across the PCI interface. In some embodiments the controller is configured to autonomously request the data from the one or more peripheral devices. The controller may be configured to request the data at a rate in the range of on the order of once every hundreds of microseconds to once every tens of milliseconds. Each autonomous read cycle may comprise several bursts, each of a size for optimal transmission by the PCI protocol being used.

In some embodiments of the invention the bridge apparatus has a write buffer and the controller is configured to: receive by way of the processor interface data addressed to contiguous addresses in a peripheral device connected to the bus; accumulate the received data in the write buffer; and, send the accumulated data in one or more bursts to the peripheral device by way of the PCI bus interface upon the occurrence of one of one or more triggering events. The one or more triggering events including a receipt by way of the processor interface of data addressed to an address non-contiguous with the received data. The one or more triggering events may also include, without limitation, one or more of: the presence in the write buffer of a threshold amount of data; the passage of a specified time since an oldest data was written to the write buffer; the bridge apparatus determining by way of the processor interface that the processor is attempting to communicate with another device; the bridge apparatus receiving by way of the processor interface for transmission to a peripheral device data consisting of less than one full long word; the bridge apparatus receiving by way of the processor interface a read request, and so on.

The peripheral device may comprise an ATM traffic shaper.

Another aspect of the invention provides apparatus for permitting a processor to write data to at least one peripheral device. The apparatus comprises: a PCI bus interface; a write buffer accessible to the processor; and a controller. The controller is configured to: receive by way of the processor interface data addressed to contiguous addresses in a peripheral device accessible by way of the PCI bus interface; accumulate the received data in a write buffer; and, upon the occurrence of one or one or more triggering events, send the accumulated data to the contiguous addresses as a burst by way of the PCI bus interface. The one or more triggering events include a receipt by way of the processor interface of data addressed to an address non-contiguous with data accumulated in the write buffer.

The bridge apparatus may have a plurality of write buffers. In such cases the controller may be configured to: accumulate the received data in a first one of the plurality of write buffers; and upon receiving by way of the processor interface, the data addressed to an address non-contiguous with the received data, place the data addressed to an address non-contiguous with the received data into a second one of the plurality of write buffers.

A further aspect of the invention provides a method for transferring data across a bus. The bus may be a PCI bus. The method comprises: at a bridge connected to the bus, receiving from a processor data addressed to contiguous addresses in a peripheral device connected to the bus; accumulating the received data in a write buffer; and, sending the accumulated data to the peripheral device upon the occurrence of one of one or more triggering events, the one or more triggering events including a receipt from the processor of data addressed to a non-contiguous address.

In some embodiments the method includes: at the bridge, periodically generating requests for data from at least one peripheral device; in response to the requests for data receiving one or more bursts of data from the at least one peripheral device; and, storing the received data in a read buffer accessible to the processor.

Further aspects of the invention and features of specific embodiments of the invention are described below.

BRIEF DESCRIPTION OF THE DRAWINGS

In drawings which illustrate non-limiting embodiments of the invention, [0017]
FIG. 1 is a block diagram of apparatus including a bridge according to the invention; [0018]
FIG. 2 is a block diagram of a bridge according to an embodiment of the invention; [0019]
FIG. 3 is a block which schematically illustrates a write buffer in a bridge; [0020]
FIGS. 4A and 4B are diagrams which schematically illustrates a pair of write buffer in a bridge; and, [0021]
FIG. 5 is a block diagram of apparatus including a bridge having a read buffer.[0022]

DESCRIPTION

Throughout the following description, specific details are set forth in order to provide a more thorough understanding of the invention. However, the invention may be practiced without these particulars. In other instances, well known elements have not been shown or described in detail to avoid unnecessarily obscuring the invention. Accordingly, the specification and drawings are to be regarded in an illustrative, rather than a restrictive, sense. [0023]
There are some applications for which, in theory, a PCI bus has enough bandwidth to be used but, in practice, the PCI bus cannot maintain a required throughput due to the inefficient way in which current PCI buses handle the transmission of data which comes in small bursts. This is true, for example, for some some telecommunications applications. In the following description a telecommunication system is used to explain the operation of the invention. The invention may also be applied outside the telecommunications field. [0024]
FIG. 1 shows a [0025] system 10 according to the invention. System 10 includes a processor 12. Processor 12 could be, for example, a Motorola™ PowerPC™ microprocessor such as a MPC8260. Processor 12 has a local bus 14 through which it can communicate with a memory 16 and with a bridge 20. Bridge 20 permits processor 12 to communicate with other parts of system 10 by way of a PCI bus 22. The operation of the PCI bus is described in the PCI Local Bus Specifications available from the PCI Special Interest Group (PCI-SIG) of Portland, Oreg. (currently at Revision 2.2) and also in Solari et al. PCI Hardware & Software Architecture and Design published by Annabooks ISBN 0-929392-59-0 and Shanley, PCI System Architecture published by MindShare ISBN 0-201-40993-3, all of which are incorporated herein by reference.
[0026] PCI bus 22 connects bridge 20 to one or more peripheral devices including at least one device with which processor 12 needs to communicate. In the illustrated embodiment, bridge 20 is connected to a traffic shaper 24 which shapes ATM (Asynchronous Transfer Mode) packets. The packets may comprise AAL2 (ATM Adaptation Layer 2) protocol units.
As shown in FIG. 2, [0027] bridge 20 comprises a read buffer 30. Read buffer 30 improves the performance of requests by processor 12 to read data from traffic shaper 24, as described below. Bridge 20 also comprises a FIFO (First In First Out) write buffer 32 and a write buffer controller 34. Write buffer 32 and write buffer controller 34 improve the performance of requests by processor 12 to write data to devices on PCI bus 22 including traffic shaper 24.
[0028] Bridge 20 conserves bandwidth by accumulating requests from processor 12 to write data to devices on PCI bus 22 in write buffer 32. Bridge 20 sends the accumulated requests as a burst across PCI bus 22. Write buffer controller 34 causes any data in write buffer 32 to be sent upon the occurrence of specified events. These events may include:
a threshold amount of data has been accumulated in [0029] write buffer 32;
a timeout occurs (e.g. a specified time has passed since the oldest data was written to write buffer [0030] 32);
in cases where [0031] bridge 20 recognizes a command for the transfer of a specified quantity of data, an amount of data specified by the command is present in write buffer 32;
[0032] processor 12 issues a read request to bridge 20;
[0033] processor 12 attempts to write less than a full long word;
[0034] processor 12 is communicating with another device; and,
[0035] processor 12 directs non-contiguous data for transmission by bridge 20 (i.e. there is data accumulated in write buffer 32 and bridge 20 receives from processor 12 data for transmission to an address which is not contiguous with the addresses of the data already accumulated in write buffer 32).
FIG. 3 illustrates [0036] write buffer 32 schematically. Data words 35 are added to write buffer 32 beginning with a first word 35A. Controller 34 permits additional data to be added to write buffer 32 until a trigger event occurs. the trigger event causes controller 34 to send all of the data in write buffer 32 across PCI bus 22 to its destination in a burst. Controller 34 may, for example, send all of the data in write buffer 32 when write buffer 32 contains a threshold amount of data. In FIG. 3 the threshold is indicated by arrows 36. The threshold may, for example, correspond to 64 words of data. Some PCI bus architectures are particularly efficient at transferring data in bursts of 64 long words each.
A bridge according to some preferred embodiments of the invention has a plurality of individually controlled write buffers [0037] 32. This permits data to be accumulating in one write buffer 32 while a burst of data is being sent from another write buffer 32. Each write buffer 32 may accumulate data for a single destination. Bridge 20 may have more than four write buffers 32 and may have, for example, five write buffers 32.
FIGS. 4A and 4B illustrates a situation in which two sets of data arrive at [0038] bridge 20 for transmission to peripheral devices on PCI bus 22. First, a data word 35B arrives at bridge 20 data word 35B is addressed to a location having an address A1. Data words 35C through 35F arrive at bridge 20. These data words are addressed to locations contiguous with A1. All of data words 35B through 35F accumulate in a first write buffer 32-1. This situation is shown in FIG. 4A. The threshold amount 36 of data for sending the data in write buffer 32-1 has not been reached.
Next, as shown in FIG. 4B, a [0039] data word 35G arrives at bridge 20. Data word 35G is addressed to an address A2, which is not contiguous with the block of addresses of words 35B through 35F. The arrival of data word 35G triggers the sending of data words 35B through 35F as a burst across PCI bus 22 to locations in a peripheral device at locations identified by the addresses A1 to A1+(N*4), where N is the number of long words contained in the buffer. Bridge 20 places data word 35G into a second write buffer 32-2 and waits for an event to trigger the transmission of data in second write buffer 32-2
In cases where [0040] processor 12 requires periodic access to data from a device on PCI bus 22, bridge 20 may be configured with a read buffer 30. For example, FIG. 5 shows a case where traffic shaper 24 contains a block of data 40 which includes data to which processor 12 requires periodic access. Bridge 20 is configured to periodically request the data of block 40. In the illustrated embodiment, requests for data 40 are generated by controller 34 in response to time information from a timer 38. These requests are preferably generated autonomously by bridge 20 (i.e. after bridge 20 has been configured to maintain a copy of data 40 in read buffer 30, bridge 20 generates the necessary requests automatically).
Requests for the data of [0041] block 40 are preferably implemented by bridge 20 writing to a control register in traffic shaper 24. These requests may be made periodically at a desired rate. For example, in some embodiments, the requests may be generated on the order of once every hundreds of microseconds to tens of milliseconds. Upon reception of the periodical requests, the controller 34, acting as an initiator, reads data from block 40 to its internal read buffer 30 across the PCI bus 22 in one or more bursts. The bursts may be chosen to have sizes which are optimal for the efficient transfer of data across PCI bus 22. The data of block 40 may be transmitted to read buffer 30 on an “opportunity” basis. Traffic shaper 24 may write the data of block 40 to read buffer 30 at a low-priority level.
[0042] Processor 12 has immediate access to data in read buffer 30 by way of local data bus 16. Read buffer 30 preferably comprises a dual port memory so that processor 12 can read data from read buffer 30 at the same time as data 40 is being written to read buffer 30.
The combination of accumulating write requests in a [0043] write buffer 32 to make more efficient use of PCI bus 22 in the write direction and providing a bridge which stores data 40 from a PCI slave device in a locally accessible read buffer 30 can provide dramatic improvements in the efficiency with which bursty data can be transmitted across a PCI bus.
[0044] Bridge 20 may be implemented in a FPGA (Field Programmable Gate Array) or custom ASIC (Application Specific Integrated Circuit). The invention may be implemented as a set of configuration instructions which cause a FPGA to be configured or an ASIC to be created to implement bridge 20. The instructions may be provided in a hardware description language (HDL) and recorded on any suitable computer-readable medium.
Certain implementations of the invention comprise computer processors which execute software instructions which cause the processors to perform a method of the invention. For example, one or more processors in a [0045] controller 34 for a bridge 20 may implement the methods of the invention by executing software instructions in a program memory accessible to the processors. The invention may also be provided in the form of a program product. The program product may comprise any medium which carries a set of computer-readable signals comprising instructions which, when executed by a computer processor, cause the data processor to execute a method of the invention. Program products according to the invention may be in any of a wide variety of forms. The program product may comprise, for example, physical media such as magnetic data storage media including floppy diskettes, hard disk drives, optical data storage media including CD ROMs, DVDs, electronic data storage media including ROMs, flash RAM, or the like or transmission-type media such as digital or analog communication links.
Where a component (e.g. a software module, processor, assembly, device, circuit, etc.) is referred to above, unless otherwise indicated, reference to that component (including a reference to a “means”) should be interpreted as including as equivalents of that component any component which performs the function of the described component (i.e., that is functionally equivalent), including components which are not structurally equivalent to the disclosed structure which performs the function in the illustrated exemplary embodiments of the invention. [0046]
As will be apparent to those skilled in the art in the light of the foregoing disclosure, many alterations and modifications are possible in the practice of this invention without departing from the spirit or scope thereof. Accordingly, the scope of the invention is to be construed in accordance with the substance defined by the following claims. [0047]

Claims

What is claimed is:

1. Bridge apparatus for permitting a processor to access data from at least one peripheral device, the apparatus comprising:

a PCI bus interface;

a processor interface;

a read buffer accessible to a processor by way of the processor interface; and,

a controller configured to periodically request data from one or more peripheral devices by way of the PCI bus interface and to store the requested data in the read buffer for access by the processor.

2. The bridge apparatus of claim 1 wherein the controller is configured to periodically request the data from the one or more peripheral devices at a rate in the range of on the order of once every hundreds of microseconds to once every tens of milliseconds.

3. The bridge apparatus of claim 1 wherein the data comprises a block of data on the peripheral device.

4. A system comprising the bridge apparatus of claim 1 together with a processor connected to the processor interface and a peripheral device connected to the PCI bus interface by way of a PCI bus.

5. The system of claim 4 wherein the data comprises a block of data on the peripheral device.

6. The system of claim 5 wherein the peripheral device is configured to send the data in the block of data to the read buffer across the PCI bus in one or more bursts.

7. The system of claim 6 wherein the PCI bus is configured to deliver the one or more bursts at a lowest priority.

8. The bridge apparatus of claim 1 comprising a write buffer, wherein the controller is configured to:

receive by way of the processor interface data addressed to contiguous addresses in a peripheral device connected to the bus;

accumulate the received data in the write buffer; and,

send the accumulated data in one or more bursts to the peripheral device by way of the PCI bus interface upon the occurrence of one of one or more triggering events, the one or more triggering events including a receipt by way of the processor interface of data addressed to an address non-contiguous with the received data.

9. The bridge apparatus of claim 8 wherein the one or more triggering events include the presence in the write buffer of a threshold amount of data.

10. The bridge apparatus of claim 9 wherein the threshold amount of data is 64 long words.

11. The bridge apparatus of claim 8 wherein the one or more triggering events include the passage of a specified time since the oldest data was written to the write buffer.

12. The bridge apparatus of claim 8 wherein the one or more triggering events include the bridge apparatus determining by way of the processor interface that the processor is attempting to communicate with another device.

13. The bridge apparatus of claim 8 wherein the one or more triggering events include the bridge apparatus receiving by way of the processor interface for transmission to a peripheral device data consisting of less than one full long word.

14. The bridge apparatus of claim 8 wherein the one or more triggering events include the bridge apparatus receiving by way of the processor interface a read request.

15. A system comprising the bridge apparatus of claim 8 together with a processor connected to the processor interface and a peripheral device connected to the PCI bus interface by way of a PCI bus.

16. The system of claim 15 wherein the data comprises a block of data on the peripheral device.

17. The system of claim 16 wherein the peripheral device is configured to send the data in the block of data to the read buffer across the PCI bus in one or more bursts.

18. The system of claim 17 wherein the PCI bus is configured to deliver the one or more bursts at a lowest priority.

19. The system of claim 15 wherein the one or more triggering events include the presence in the write buffer of a threshold amount of data.

20. The system of claim 19 wherein the threshold amount of data is 64 long words.

21. The system of claim 15 wherein the one or more triggering events include the passage of a specified time since the oldest data was written to the write buffer.

22. The system of claim 15 wherein the one or more triggering events include the bridge apparatus determining by way of the processor interface that the processor is attempting to communicate with another device.

23. The system of claim 15 wherein the one or more triggering events include the bridge apparatus receiving by way of the processor interface for transmission to a peripheral device data consisting of less than one full long word.

24. The system of claim 15 wherein the one or more triggering events include the bridge apparatus receiving by way of the processor interface a read request.

25. The system of claim 15 wherein the peripheral device comprises an ATM traffic shaper.

26. The bridge apparatus of claim 8 comprising a plurality of write buffers wherein, the controller is configured to accumulate the received data in a first one of the plurality of write buffers and, upon receiving by way of the processor interface, the data addressed to an address non-contiguous with the received data, place the data addressed to an address non-contiguous with the received data into a second one of the plurality of write buffers.

27. The bridge apparatus of claim 26 wherein the plurality of write buffers comprises at least four write buffers.

28. The bridge apparatus of claim 1 wherein the PCI bus interface, processor interface; read buffer and controller are implemented on a Field Programmable Gate Array.

29. A computer readable medium containing instructions for configuring a field programmable gate array to implement the bridge apparatus of claim 28.

30. The bridge apparatus of claim 8 wherein the PCI bus interface, processor interface; read buffer and controller are implemented on a Field Programmable Gate Array.

31. A computer readable medium containing instructions for configuring a field programmable gate array to implement the bridge apparatus of claim 30.

32. Apparatus for permitting a processor to write data to at least one peripheral device, the apparatus comprising:

a PCI bus interface;

a write buffer accessible to the processor;

a controller configured to:

receive by way of the processor interface data addressed to contiguous addresses in a peripheral device accessible by way of the PCI bus interface;

accumulate the received data in a write buffer; and,

upon the occurrence of one or one or more triggering events, send the accumulated data to the contiguous addresses as a burst by way of the PCI bus interface;

wherein the one or more triggering events include a receipt by way of the processor interface of data addressed to an address non-contiguous with data accumulated in the write buffer.

33. The bridge apparatus of claim 32 wherein the one or more triggering events include the presence in the write buffer of a threshold amount of data.

34. The bridge apparatus of claim 33 wherein the threshold amount of data is 64 long words.

35. The bridge apparatus of claim 32 wherein the one or more triggering events include the passage of a specified time since an oldest data was written to the write buffer.

36. The bridge apparatus of claim 32 wherein the one or more triggering events include the bridge apparatus determining by way of the processor interface that the processor is attempting to communicate with another device.

37. The bridge apparatus of claim 32 wherein the one or more triggering events include the bridge apparatus receiving by way of the processor interface for transmission to a peripheral device data consisting of less than one full long word.

38. The bridge apparatus of claim 32 wherein the one or more triggering events include the bridge apparatus receiving by way of the processor interface a read request.

39. The bridge apparatus of claim 32 comprising a plurality of write buffers wherein, the controller is configured to:

accumulate the received data in a first one of the plurality of write buffers; and

upon receiving by way of the processor interface, the data addressed to an address non-contiguous with the received data, place the data addressed to an address non-contiguous with the received data into a second one of the plurality of write buffers.

40. The bridge apparatus of claim 39 wherein the plurality of write buffers comprises at least four write buffers.

41. A method for transferring data across a bus, the method comprising:

at a bridge connected to the bus, receiving from a processor data addressed to contiguous addresses in a peripheral device connected to the bus and accumulating the received data in a write buffer;

sending the accumulated data to the peripheral device upon the occurrence of one of one or more triggering events, the one or more triggering events including a receipt from the processor of data addressed to a non-contiguous address.

42. The method of claim 41 wherein the bus comprises a PCI bus.

43. The method of claim 42 wherein the one or more triggering events include the presence in the write buffer of a threshold amount of data.

44. The method of claim 41 wherein the threshold amount of data is 64 long words.

45. The method of claim 42 wherein the one or more triggering events include the passage of a specified time since an oldest data was written to the write buffer.

46. The method of claim 42 wherein the one or more triggering events include the processor attempting to communicate with a device other than the bridge.

47. The method of claim 42 wherein the one or more triggering events include the bridge receiving for transmission to a peripheral device data consisting of less than one full long word.

48. The method of claim 42 wherein the one or more triggering events include the bridge receiving a read request.

49. The method of claim 42 wherein the peripheral device comprises a traffic shaper.

50. The method of claim 42 comprising:

at the bridge, periodically generating requests for data from at least one peripheral device;

in response to the requests for data receiving one or more bursts of data from the at least one peripheral device; and,

storing the received data in a read buffer accessible to the processor.

51. The method of claim 50 wherein the peripheral device comprises a traffic shaper.

52. The method of claim 51 comprising generating the requests with a period in the range of on the order of once every one request per 100 microseconds to one request per 100 milliseconds.

53. The method of claim 51 comprising generating the requests with a period in the range of one request per 1 millisecond to one request per 10 milliseconds.

54. The method of claim 50 comprising sending the one or more bursts of data from the peripheral device to the bridge at a low priority.