SU1539779A1 - Device for servicing inquiries - Google Patents

Abstract

The invention relates to automation and computing and can be used in data exchange systems with priority customer service. The purpose of the invention is to simplify the device. The device contains a register 1, a group of counters 4 ₁ -4 _k , a generator of 16 clock pulses, two groups of elements AND 3 ₁ -3 _k , 10 ₁ -10 _k , element And 14, trigger 13, three elements OR 2,12,17, a group of elements AND-NOT 5, an element OR-NOT 15 and block 7 analysis of codes. The device provides the choice of servicing the subscriber who is assigned the highest priority, taking into account the time of his stay in the queue. Submissions from subscribers are recorded in register 1 with simultaneous transfer of 4 established priority codes to the corresponding counters. The selection of the priority subscriber is made by simultaneously analyzing the codes from the outputs of the counters 4 on the basis of a bitwise comparison of the same-named bits of these codes in block 7. 2 Il.

Description

The invention relates to automation and computing and can be used in data exchange systems with priority customer service.

The aim of the invention is to simplify the device.

FIG. 1 shows a block diagram of the proposed device; in fig. 2 - structural analysis of codes.

The device (FIG. 1) contains the register 1, the element OR 2, the group of elements AND 3, the group of counters 4, the group of elements AND-NOT 5, the information inputs 6 of the code analysis block 7, the information outputs 8 and the signal output 9 of block 7, element group AND 10, device outputs 11, element OR 12, trigger 13, element AND 14, element OR NOT 15, generator 16 clock pulses, element OR 17, device request outputs 18, device start input 19, $ 20 stop devices and groups of code inputs 21 devices.

Block 7 analysis of codes (Fig. 2) includes channels 22, each of which contains an element AND NOT 23 and, starting with the second, in addition a group of elements OR 24 and a group of elements AND 25. In addition, block 7 contains the element OR 26, the group of elements And 27, the group of elements OR-NOT 28 and the group of elements 29 of the ban.

The device works as follows.

The initial state is characterized by the fact that the trigger 13, the counters 4 and the register 1 are set to the state O (not shown), the inputs 18, 19 and 20 and the outputs 11 do not have signals, the state of the inputs 21 of the device is arbitrary.

When a request for service is received from the subscriber, a pulse appears at the corresponding input 18 of the device, which sets the corresponding register register 1 register value to 1 m and allows the subscriber priority code from the corresponding group of inputs 21 to be received from the corresponding group of inputs 21. The priorities of the user accounts can have arbitrary values from 1, with higher values of codes corresponding to higher priority levels.

0

Q 5

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0

When the bits of the register 1 are set to 1, the corresponding element AND 3 is opened at the first input, and if in this counter 4 there is no greatest code (the units are not in all its bits), the element 3 is open at the second input with a single signal from the output of the element of the same name AND-NOT 5. Therefore, the pulses of the generator 16 arrive through the elements AND 3 at the counting inputs of the corresponding counters 4, in which increasing sequences of priority code values are formed. This takes into account the waiting time of a queued quota.

If the priority code in the counter 4 reaches the highest value, then the same element AND 3 of the group is locked at the second input by zero Signal from the output of the corresponding element IS-NOT 5, which prevents the input of pulses to the counting input of this counter. four,

The initial start signal from input 19 through the element OR 12 enters the single input of the trigger 13 and sets it to the leading edge 1. If at this moment the second input of the AND 14 element has a single signal from the output of the OR-NOT 15 element, which indicates the absence of pulses of the request at the inputs 18 and the pulse at the output of the generator 16 and about 5c-transients at the outputs of block 7 occurring during the duration of the pulses of requests and the pulse at the output of the generator 16, the elements of And 10 unlock through the third inputs. If there is a request in register 1 with a single signal from the output of the element OR 2, elements 10 are opened at the fourth inputs. The signal from output 8 of block 7, corresponding to the priority subscriber, opens the second element of group 10 at the second input. A single signal from the output 9 of the block 7 through the first inputs open elements And 10.

The signal generated at output 11 initiates the start of service for the corresponding subscriber,. In addition, according to this signal, the corresponding register bit 1, the corresponding group 4 counter and trigger 13 through the OR element 17 are set to O. After the trigger 13 is set to the zero state, the And 14 for the

closes while locking the elements of AND I 0 of the group.

Element And 14 blocks the transmission of the next signal to output 11 for the duration of subscriber servicing, and in counters 4 for which And 3 elements are open, the formation of an increasing code sequence continues.

A new device operation cycle starts when the device 20 has a response signal from the subscriber. On this signal, similar actions are performed, as well as on the initial start signal.

Select the subscriber with the highest prio-. The routine is based on the analysis of priority codes in block 7 as follows.

Priority codes from the inverse outputs of the counters of the 4 groups are received in block 7 of the priority request selection. The analysis of these codes is performed in a fractional way, starting with the higher bits.

Consider the operation of block 7 for K 3 and for different values of priority codes.

If there are no requests in register 1, zero codes are set in the counters 4. From the zero outputs of the counters, inputs 7 in block 7 receive codes that contain units in all digits.

So, at the inputs of the element IS-NOT 23 of the last channel 22 there are single signals. Similarly, at the inputs of the NAND 23 elements of the remaining channels 22, through the corresponding elements of OR 24, there are also single signals from the inputs 6. Thus, at the outputs of each element of the NAND 23, zero signals are established, the closing elements AND 25 and the elements 27. At the same time At the inputs of all elements of the CLI-NOT 28, zero signals are present. At the outputs of the elements OR-NO 28, a code 111 is generated, which is converted by the prohibition elements 29 into a unitary one. In this case, at the outputs 8 of the block 7, the code 100 is set, and at the output 9 by the OR element 26, to the inputs of which zero signals are supplied from the outputs of the AND – NE 23 channels 22, a zero signal is formed, which blocks the K 10 elements.

Thus, in the absence of requests in register 1, unit 7 generates a single signal, which in this case is false. To expel

ten

15

20

25

5Q 30

35

40

55

6

The effect of such a signal is OR 26.

Let in the process of operation in all counters 4 the maximum values of codes are set, i.e. units in all digits. In this case, zero codes are set at the zero outputs of the counters.

Since the inputs of the NAND 23 element of the last channel 22 contain zero signals, a single signal is set up at its output, which opens the AND 25 elements of the penultimate channel. 22, -, On the second, the inputs of these elements contain zero signals from the inputs 6. Therefore, zero signals are formed at the outputs of the AND 25 elements.

Thus, in this case, with equal priority codes formed at the outputs of counters 4, the code 111 is generated at the outputs of the OR-NOT elements 28. This code is converted by the prohibition elements 29 into unitary 100. At the output of the OR element 26, a single signal is opened that opens And 10.

Prohibition elements 29 are needed to select a priority subscriber from a number of subscribers (the priority increases with the subscriber number), for which, for a number of reasons, the same priority codes can be generated in counters 4. Such situations arise when, at the moment of transmission of the priority code from input 21, if there is a request from the input 18 of the same name to the corresponding counter 4 in another of them due to the arrival of generator pulses 16. a code similar to that received can be generated. In addition, with a significant wait time, a number of codes can be set in a number of counters. So, if in one of them this code reaches such a value, then the corresponding element IS-NE 5 generates a zero signal that blocks the flow of generator pulses 16 to the counting input of this counter 4. The counting of pulses continues in other counters, in which the maximum values can be set. codes.

To exclude the issuance of spurious signals to the outputs 11, when all the counters 4 are set to the zero state, which indicates the absence of requests in the register 1 of the application, the OR 2 element is used.

In the case of a zero signal, from its output the elements AND 10 are closed at the fourth inputs.

Claims (1)

Invention Formula A device for servicing requests containing a register, a group of counters, a clock pulse generator, two groups of elements AND, an element AND, a trigger, three elements OR, a group of elements NAND, an element OR NONE, and the information inputs of the register are inputs of device requests and below1 Keyed to the same inputs of the element 15 20 35 this OR NOT and the clock inputs of the corresponding group counters, the output of each digit of the register is connected to the first input of the element I of the same name and the first group, the output of which is connected to the counting input of the same name group, whose information input group is the corresponding code input of the device, The direct outputs of each counter of the 25 group are connected to the inputs of the same name AND NAND group, the output of which is connected to the second input of the same element AND of the first group, the third input of which is connected OQ with the output of the clock pulse generator and the corresponding input of the OR-NOT element, the output of which is connected to the first input of the AND element, the second input of which is connected to the single output of the trigger, the output of the AND element is connected to the first inputs of all AND elements of the second group whose outputs are device outputs and connected to the reset inputs of the register, the reset inputs of the corresponding group counters and the inputs of the first OR element, the output of which is connected to the zero input of the trigger, the single input of which is connected to the output of the second the OR element, the first and second inputs of which are the inputs of the device start and stop, respectively; the output of the third element OR is connected to the first input of the first AND element of the second group, characterized in that, in order to simplify the device, it contains a code analysis unit the inputs of which are connected to the inverse outputs of the counters of the group, the output of the element I is connected to the second inputs of the elements AND of the second group, starting from the second, the third input of each element AND the second group of co40 50 0 five 0 five 5 Q 0 0 dinene with the signal output of the code analysis block, each information output of which is connected to the fourth input of the AND group of the same name of the second group, the register outputs are connected to the inputs of the third OR element, and the code analysis block contains the OR element, the group of OR-NOT elements, the prohibition element group, the group AND elements, channels, and in each channel, except the last, a group of AND elements, a group of OR elements and an AND-NOT element, the last channel contains an AND-NOT element, the output of each first group of inputs of the code analysis block is connected to the first the input of the element of the same name OR of the first channel and the first input of the element of the same name AND group, the outputs of which are connected to the first inputs of the elements of the same name OR-NOT; the outputs of the elements of AND-NOT channels are connected to the inputs of the element OR whose output is the signal output of the code analysis unit, the second the inputs of the elements OR of the group of each channel are connected to the outputs of the elements of the same name AND group of this channel, the output of the AND-N element of the first channel is connected to the second inputs of the AND elements of the group, the output of the AND-NOT element of each channel, starting from the second, connected to the first inputs of the AND group of the previous channel, the inputs of each group of inputs to the code analysis block, starting from the second, connected to the second inputs of the same AND elements of the previous channel, the output of each AND element of each channel is connected to the corresponding input of the same name the element OR of all previous channels and the corresponding input of the element of the same name OR — NOT a group, the last group of inputs of the code analysis block is connected to the inputs of the AND-IS element of the last channel, the outputs are Each OR channel, except the last one, is connected to the inputs of the AND-NOT element of its own channel, the output of the first element OR-NOT group and the outputs of the prohibition elements of the group are the group of information outputs of the code analysis block, the output of each element OR-NOT group, starting from the last, connected to the direct input of the previous element of the group ban, the output of each element of the OR-NOT group is connected to the inverse inputs of the same name and all subsequent elements of the group ban.