SU1075264A2 - Device for servicing queries - Google Patents

Abstract

USING FOR DELIVERY OF INQUIRIES by ivc.st. 898435, about t -. l and ch yu 6 e with the fact that with. In order to improve speed, it additionally contains the element ILINE and a group of decoders, the inputs of which are connected to the outputs of the respective priority register registers and the outputs to the corresponding inputs of the output OR-NOT, the output of which is connected to the third inputs of the elements AND II of the second group. .

Description

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4 The invention relates to computing technology / in particular, to priority request processing devices. By bus 898435, a device for servicing requests is known, which contains a register of requisitions, the first group of S & P elements, the first OR element, a group of priority registers, the AND element, a control trigger, the second OR element, a reversible counter, a frequency divider, a second group of AND elements, a comparison circuit group , pulse generator, the output of which is connected to the direct input of the element AND, the first inverse input of which is connected to the inverse output of the control trigger, the second inverse input - to the output of the first OR element and to the reset input of the control trigger No, the direct input of which is under the keys to the output BTOpofo of the OR element, whose inputs are the control inputs of the device, the register outputs of the order are connected to the first inputs of the AND elements of the first group, the outputs of which are connected to the installation inputs in O of the respective priority registers, the inputs of the register The requests are informational inputs of the device, and the outputs of the group comparison circuits are connected to the second inputs of the elements AND of the first group. gpa, the outputs of which are half connected to the inputs of the first element OR and the corresponding reset inputs are the register, the outputs of which are connected to the first inputs of the AND elements of the second group, the second inputs of which are connected to the output of the frequency divider, and the outputs to the counting inputs of the corresponding priority registers mouth the new inputs of which are input code buses of the device, and the outputs of priority registers are connected to the first inputs of the group comparison circuits, the second inputs of which are connected to the output of the reversible counter, the counting input of which is connected to the output of the And element, the setting input of the reverse counter connected to the output the second element OR, and the reading input is to the output of the first OR, the output of the pulse generator is connected to the input of the frequency divider, the outputs of the AND elements of the first group are 1 output buses, devices. The device works as follows. Before the start of the work cycle in. priority register-registers post priority codes, which determine the priority of the respective subscribers. Requests from subscribers are received in the corresponding register bits of the application, the number of bits of which is equal to the number of subscribers. The pulses from the pulse generator through a frequency divider, which can be used as a conventional counter, arrive at the counting inputs of those priority register counters for which there are applications in the application register. In these counters, an incrementing sequence of numbers is formed, starting with the previously applied priority code. By the start-up signal, the counter and the control trigger are set to one, allowing the pulses to flow from the generator to the counter, at the output of which a decreasing binary number is generated. Both sequences with register and counter counters are compared in the respective comparison circuits. If the codes at the output of the comparison circuit corresponding to the highest priority source of the request, coincide. an impulse appears, which, arriving at the output bus of the device, sets the corresponding register register, register register, and control trigger into O. The next cycle of operation of the device begins with the arrival of a response signal from the subscriber. Prior to the arrival of the response signal, impulses are received through the frequency divider from the generator to those priority register registers for which there are requests in the application register. This takes into account the waiting time of the queued queuing and eliminates the long stay of the low priority queuing application 1J. The drawback of the device is the low speed due to the waiting time of the queuing queuing. The aim of the invention is to increase speed by analyzing priority codes. The goal is achieved by the fact that the device for servicing requests additionally contains an OR-NOT element and a group of decoders whose inputs are connected to the outputs of the corresponding registers, the group priority, and the outputs to the corresponding inputs of the OR-NOT element whose output is connected to the third input i and elements And the second group. The drawing shows a block diagram of the device. The device for servicing the requests contains the register 1 request, the information inputs 2 of the device, the priority priority registers 3, the AND 4, OR 5. and 6 elements, the counter 7, the group comparison circuits 8. Elements 9 of the first grupp, trigger 10 controls, control inputs 11 and 12 of the device,

Claims (1)

DEVICE DAY SERVICE DAY No. 898435, about T - <l and most of all with the fact that, with · .... In order to improve performance, it additionally contains an ILINE element and a group of decoders whose inputs are connected to the outputs of the corresponding group priority registers, and the output to the corresponding inputs of the OR-HE element, the output of which is connected to the third inputs of the AND elements of the second group. .