SU1211718A1 - Device for sorting numbers - Google Patents

Description

The invention relates to automation and computing and can be used in specialized output machines and: data processing devices.

The purpose of the invention is to increase the speed.

The drawing shows a functional diagram of the device.

The device contains h registers 1, p decoders 2, the number of elements OR 3, (1-1) prohibition elements 45 encoder 5, n comparison circuits 6, h elements AND 7, result register 8, cyMMatop 9, delay element 10, and element I- NOT 11, groups of output elements And 12 and 13, inputs 14 sorting 5th numbers of the device,. inputs 15 specify the initial address of the device, output 16 of the end of sorting, outputs 17 of the sorted number, clock input 18 and output 19 of the device address.

Consider the printable build and operation of the device.

The initial state of the device is characterized by the fact that in registers 1, inputs 14 accept an array of initial numbers, and in adder 9 a memory code, beginning with which it is necessary to place a sorted array of numbers

The initial numbers are converted by decoders 2, the output signals from the same outputs of which are combined by the corresponding elements of sh 3,:

Let an array of numbers have the following form: o, 4, 02 5, 05. .

With these initial data, the operation of the decoders 2 and the elements of SH 3 is explained in Table 1.

The table shows that the number of outputs of the decoders, and therefore the number of the element OR 3 uniquely, correspond to the value of the number, and the output single signals of the elements of ШШ 3 are arranged in order of increasing values of the numbers. In addition, with equal binary codes in the array

numbers (a,, 0) single signals are formed by the corresponding elements OR 34 and 3. Thus, the ordered

The array should have the following form: b, 1, 3, 4, and these numbers should be placed in the selected

2117182

: memory areas, the code of the initial adres. of which is A д d is taken into the adder 9.

The positional code of the output signals of the elements OR 3 10111 is applied to the elements of prohibition 4, included in the priority scheme. So, a single signal from the output element

d; OR 3, closes on the inverse entrances all subsequent elements of the ban. In this case, a position code 10000 is formed at the input of the encoder 5. The encoder 5 converts this code to binary 001, which is received in result register 8. In addition, in the comparison circuit 6, the codes coincide, a single signal from the output of which enters

2Q at the first input element And 7y. At the output of the element AND NOT 11, the unit signal is absent, therefore, a clock pulse is received from the computer at input 18. By this impulse address

25 adder 9 through the group of elements And 13 enters the outputs 19, and the binary code of the first number from the register 8 of the result through the group of elements And 12 goes to the outputs 17. After some time, determined by the delay in the delay element 10, in the adder 9. the next address

thirty

45

and set in O register 1y, which excludes from the analysis the number of poison, 5 Delay time is selected based on the required time of reception in the computer address and the value of numbers with you; moves 17 and 19.

After setting in О the register IjHa outputs of the elements OR 3, the next position code 00111 is formed, and the code 00100- at the input of the encoder 5. In this case, a binary code 011 is received in the result register 8, and a single signal is generated in the comparison circuit 65. On the next clock pulse from the input 18, the values of the number 011 and the code

 the addresses A ,, are fed into the computer, and in the device the register 1 is set to O and the next address P ,, is formed in the adder 9. At the same time, at the outputs of the elements OR 3, a POSITION code 00010 is running for 55, and a binary code 100 for the output of the encoder 5. In codes 6, and 6 for comparison, the codes coincide.

On the next pulse at input 18, the value of the number 100 is the code of the address of the AZ, entered into the computer, registers 1 and D are set to O, and in the adder 9 the address of the next number is formed. By the next clock pulse, the number 101 is written to the address A4 and the device is set to About registers

and 1 ,. In this case, all registers 1

2 6

turns out to be in the zero state, and a single signal is generated at the output of the NANDI element 11, which arrives at the computer as a signal of the end of sorting.

Thus, an array of six numbers is sorted into four clock signals.

Claims (1)

DEVICE FOR SORTING NUMBERS, containing both registers, tt AND elements, where h is the number of sortable numbers, and comparison schemes, (n-1) inhibit elements, a result register, two groups of output AND elements, an adder, the first group of inputs of which are connected to the inputs of the task the initial address of the device, and the outputs are connected to the information inputs of the output elements of the first group, the outputs of which are the outputs of the device address, the outputs of the result register are connected to the information inputs of the output elements of the second group, the outputs of which are the outputs of the sorted number of the device, the control inputs of the output elements And the first and second groups are connected to the clock input of the device, the inputs of the sorted numbers of the device are connected to the information inputs of the corresponding registers, the outputs of which are connected to the first groups of inputs of the corresponding comparison circuits,? the inverse inputs of the prohibition elements from the 8th to the (n-1) th are combined (E = 1,2, ..., 0-1), which is characterized by the fact that, in order to increase the speed, they are introduced into it (tn-i) elements of prohibition, And decoders, tn elements of OR, where ttt = 2 ^h , (m-1) elements of prohibition, delay element, encoder and AND-NOT element, the output of which is the output of the end of the device’s sorting, and the inputs connected to the outputs of the encoder, the inputs of the result register and the second groups of inputs of all comparison circuits, the outputs of the comparison circuits are connected to the first inputs of the corresponding AND elements, the outputs of which connected to the installation inputs to the zero state of the corresponding registers, the outputs of which are additionally connected to the inputs of the corresponding decoders, the i-th output of the j-th decoder, where i = 1,2 ..... tn; j = 1,2, ..., η, are connected to the jth input of the ίth OR element, the output of the first OR element is connected to the first input of the encoder and. the first inverse inputs of the inhibit elements, the output to the ith element OR, where k = 2,3, ..., m, is connected to the direct input of the (k-1) th inhibit element and to the ith inverse input of the kth element prohibition, the output of the pth prohibition element, where p = 1,2, ..., (sh-1), is connected to the (p + 1) th input of the encoder, the device’s clock input is connected to the second inputs of all elements through a delay element AND. 1 . 1