SU1615720A1 - Multichannel device for servicing requests in coming order - Google Patents

Abstract

The invention relates to automation and computing technology and can be used in designing a software control system for a group of CNC machines from a computer. The purpose of the invention is to increase speed. The device contains two counters 1, 2, two decoder 3, 4, comparison circuit 5, element OR 6, two formers 7, 8 pulses, group 9 of elements OR, group 10 of channels. Each channel of group 10 has a register 19 and a group of 20 elements I. The device allows to increase the operating efficiency of the serving device due to the group processing of requests of a group of subscribers. 2 Il.

Description

(21) 4667957 / 24-24 (22) 02.17.89 (46) 12.23.90. Bul ; (72) FK Ayginin. A.D. Borzenkov, A.M.Gusarov, N.I.Ogorodnev and A.A.Ukhabin (53) 684.325 (088.8)

(56) USSR Author's Certificate N 817715, cl. G 06 F 9/46, 1979,

USSR Author's Certificate 1 1008744, cl. G 06 F 9/46, 1981.

(54) MULTI-CHANNEL DEVICE FOR SERVICING REQUESTS FOR PROCEDURE

(57) The invention relates to automation and

computer technology and can be used in the design of a software control system for a group of machine tools with a CPU from a computer. The purpose of the invention is to increase speed. The device contains two counters 1 2 two decoders 3, 4, comparison circuit 5, element OR 6, two formers 7.8 pulses, group 9 elements OR, group 10 channels. Each channel of group 10 has a register 19 and a group of 20 elements I. The device allows to increase the operating efficiency of the serving device due to the group processing of requests of a group of subscribers. 2 Il.

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The invention relates to computing and can be used in the design of a software control system for a group of computer numerical control equipment from a computer.

The purpose of the invention is to increase speed.

FIG. 1 is a block diagram of the device; in fig. 2 is a block diagram of a kana device (Fig. 1) contains the first 1 and second 2 counters, the first 3 and second 4 decoders, the comparison circuit 5, the element OR 6, the first 7 and the second 8 pulse shapers, a group of 9 OR elements, a group of 10 channels, a group of 11 information outputs, an output 12 of an interrupt, a group of 13 information inputs, a clock input 14, a device reset output 15, a group of 16 and 17 outputs of the first and second decoder 3 and 4, respectively, and a group 18 of channel outputs of group 10.

Each channel 10 has (FIG. 2) a register 19 and a group of 20 elements I.

The device works as follows

Before starting the device mouth; is reset by a logical 1 signal at input 15 of the reset, holding the registers 19 of the channels of group 10 and counters 1 and 2 are zeroed out, and at the output 12 of the device a logical 1 signal is generated.

Binary codes of subscriber requests arrive at a group of 13 information inputs successively at random times. Upon receipt of each binary request code of any of the subscribers, a logical 1 signal is generated at the output of the OR 6 element and is fed to the input of the first imaging unit 7 pulses. The first pulse shaper 7 calibrates the duration of the output pulse, independent of the duration of the input pulse. A single pulse from the output of the first driver 7 pulses goes to the gate input of the first decoder 3 and to the inverse counting input of the first counter 1. At the corresponding output of the first decoder 3, a single pulse is generated to the clock input of the register 19 of the corresponding channel of group 10, and the entry is made the binary code of the subscriber’s request to register 19 of this channel. On the trailing edge of a single pulse at the output of the first driver 7, a unit is added to the contents of the first counter, and a logical O signal is generated at the output 12 of the device. The binary codes of the other antenna elements of the device are written similarly.

Binary codes of requests written to the registers of the 19 channels of group 10 are read out when there is a logical signal O at the output 12 of the device along the leading edge of a single pulse at the output of the second driver 8 pulses when the signal of the logical 1 arrives at 0 clock input 14 of the device. A single pulse from the output of the second driver 8 pulses is fed to the gate input of the second decoder 4. At the same time, a single pulse is generated at the corresponding output of the second decoder 5, which is fed to the second inputs of the And element of the group 20 of the corresponding channel of group 10. The binary request code written to register 19 the corresponding channel of the group 0 of the units 10, is fed to the group of 18 outputs of this channel of the group of 10 and through the corresponding inputs of the elements of OR of group 9 to the group of 11 information outputs of the device.

The sign of the end of reading of binary 5 request codes from the registers 19 of the channels of group 10 is the formation of a logical 1 signal at the output 12 of the device.

If necessary, the reading of the binary SO codes of subscriber requests can be suspended after reading the next binary request code in the presence of a logical signal O at the output 12 of the device, for example, in the absence of a free computing resource of the serving device.

The continuation of the reading of the binary codes of subscriber requests is carried out by the logical 1 signal at the device clock input 14 40, and the read address in the second counter 2 will be one more than the previous one.

Claims (1)

Claims. A multichannel device for servicing 46 requests in the order of arrival contains channels, two counters, two decoders, a group of OR elements whose outputs are connected to a group of information outputs of the device, an OR element, 50 inputs of which are connected to a group of information inputs of the device, outputs of counters connected to the inputs of the decoders, each of the channels contains a register, a group of elements I, the first inputs 55 of which are connected respectively to a group of bit outputs of the register of their channel, the outputs of elements And the groups of each channel are connected to the corresponding inputs of the elements of the same name OR group, the inputs of zeroing the registers of all channels are connected to the inputs of zeroing the first and second counters and connected to the general reset input of the device, characterized in that, in order to improve the speed of the device, Two pulse generators and a comparison circuit are introduced, the group of information inputs of the device is connected to groups of information inputs of registers of all channels, the clock input of the register of each channel is connected correspondingly at the same output of the first decoder, the gate input of which is connected to the counting input of the first counter and connected to the output of the first shaper0 owls whose input is connected to the output of the OR element, the output groups of the first and second counters are connected to the first and second groups of inputs of the comparison circuit, the output of which is the interrupt output of the device, the second inputs of the AND groups of each channel are connected respectively to the same outputs of the second decoder, strobe the input of which is connected to the counting input of the second counter and connected to the output of the second pulse driver, the input of which is connected to the clock input of the device,