SU1283778A1 - Interphase for linking group of computers - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used for informational interfacing of different types of computers operating as part of a group of interconnected information processing systems. The aim of the invention is to increase speed. The device contains a group of memory blocks a group of input and output registers, two groups of comparison nodes, five groups of elements OR, two groups of nodes of elements AND, a group of elements AND, a pulse generator, a counter, an output register, a group of encoders, an element ShZh, an element I. 1 il.

Description

ABOUT)

with:

Yu

X

with

| vl

00

The device relates to automation and computing technology and can be used for informational interfacing of different types of computers, working as part of a group of interconnected computers. data processing systems. The purpose of the invention is to improve speed.

The drawing shows a diagram of an apparatus for interfacing a group (of K) of computers.

The device contains a group of K input registers 1, a group of M; nodes 2 comparisons, a group of K blocks 3 memory, an element OR 4, a group of H nodes of elements AND 5 (H is the number of necessary information transcoding), a group of H encoders 6, a group of H output registers 7, a group of K comparison nodes 8, a group of K nodes And 9 elements, a pulse generator 10, an element AND P, a counter 12, a group of elements OR 13-16, a group of elements AND 17, an output register 18, a group of K input-output buses 19 of the device and a group of elements OR 20.

The device is compatible as follows.

A standard information message from one of the objects (computer) arrives at the input of the device through the input-output line, and participates in the information exchange. Each informational message contains a message type, the actual information part and the address of the subscriber to whom the message is intended. The size of the registers of the group of input registers is determined by the size of the information messages of a specific subscriber (source) connected to the input-output highway. From the third group of information outputs of the group register, information about the type of message is fed to the inputs of all group comparison nodes, in which the downing code is compared with predetermined information about possible message types (M; determined by the number of different types of messages that can come from the i-ro object ).

The comparison signal is generated at the output of one of the nodes, and will initiate a call to the corresponding memory cell of the memory block 3. In each cell of the memory record 15

20

25

Next information: a clock resolution signal, an additional counter code, the specific value of which is determined by the necessary frequency of information output to the subscriber - consumer, the encoder connection mask, which determines which of the encoders should perform the necessary conversion to the input information. The clock frequency resolution signal from a certain memory block is fed to the corresponding input of the element OR A, the output of which removes the signal that allows the clock frequency to pass from the generator 10 through the AND II element to the counting input of the counter 12, to the information input of which an additional code counter taken from the output bus of the first group of elements OR 13, to the corresponding inputs of which the additional counter code comes from the corresponding memory block 3. Thus, from the output of the counter A signal for allowing the output of recalculated information to a subscriber to a consumer with a frequency determined by an additional counter code, which, in turn, is determined by a given exchange algorithm for each type of information message.

Encryption connection mask, removed from the output of the corresponding

35 of the memory block 3, is fed to the corresponding inputs of the second group of elements OR 14, from the output of which is fed to the second inputs H of the nodes of the elements AND 5, to the first inputs of which

40 are supplied with information from the output of the third group of elements OR 15, to the inputs of which information comes from the first group of information outputs of the register of the group of input registers 5 I. The mask code determines the corresponding encoder 6, to the input of which information is allowed. Each encoder is designed to convert information of a certain type, and their number is determined by the number of exchange information of the same type represented in various encoding systems.

thirty

The transformed information from the output of the corresponding encoder 6 is written to the corresponding output register 7, from where it goes to the corresponding inputs of the fourth

the group of elements OR 16 and by the enable signal of the counter 12 through the group of elements And 17 is written into the output register 18.

The address of the subscriber to whom the converted information is intended, from the second group of information outputs of the group of input registers 1, passes through the third group of elements OR 20 to the inputs K of comparison nodes 8, in which the received code is compared with the preset information about possible addresses of information output. The comparison signal is generated at the output of one of the comparison nodes, permitting the passage of the transformed information from the register 18 through the corresponding group of elements AND 9 into the output highway connected with the user agent - the information consumer.

Claims (1)

Invention Formula A device for interfacing a group of computers that contains a group of input registers, a group of memory blocks, a pulse generator, a counter, five groups of OR elements, an OR element, an AND element, two groups of AND node nodes, an output register of an AND group, and information inputs the input registers of the group are connected to the information, address and control outputs of the computers of the group, the outputs of the nodes of the elements And the first group are connected to the information inputs of the computers of the group, with a group of information the bit outputs of the memory blocks of the group are connected to the corresponding bit inputs of the OR elements and the corresponding bit inputs of the NL elements of the first and second groups, the first groups of information bit outputs of the input registers of the connection group with the corresponding bit inputs of the OR elements of the third group, group the outputs of which are connected with the first groups of inputs are corresponding. nodes of elements And 837784 The second group, the second groups of inputs of which are connected to the corresponding groups of outputs of the elements OR of the second group, the group of output-5 DON elements OR of the first group is connected to the group of information inputs of the counter, the counting input of which is connected to the outputs of the element AND, the first and second inputs fO of which are connected to the outputs of the OR element and the pulse generator, respectively, the first groups of inputs of nodes AND of the first group are connected to groups of information discharges of 1x outputs of the receiver, whose information inputs are connected to the outputs of elements AND of the group, the first and second groups of inputs are connected to counter outputs and elements OR 20 of the fourth group, respectively, the second groups of informational 1P) 1x bit outputs of the input registers of the group are connected to corresponding groups of the bit inputs of the elements OR the fifth 25 groups characterized by that, in order to increase speed, two groups of comparison nodes, a group of encoders, a group of output registers are introduced into it, while the third the groups of information bit outputs of the input registers of the group are connected to the corresponding groups of inputs of the comparison nodes of the first group, the output groups of which are connected to the corresponding groups of address inputs of the group's memory blocks, the group of outputs of the nodes of the elements And the second group are connected to the corresponding inputs of the group encoders, the outputs which connect 1 to the information inputs of the output registers of the group, information inputs of the output registers of the group, information outputs of which are connected to the corresponding groups of inputs of the elements OR of the fourth group, the group of outputs of the elements OR of the fifth group are connected to the corresponding inputs of the comparison nodes of the second group, the outputs of which connected with the second groups of inputs of nodes of elements AND of the first group. nineteen eight W